yowasp-yosys 0.44.0.0.post760__py3-none-any.whl → 0.45.0.0.post775__py3-none-any.whl

yowasp_yosys/share/gowin/cells_sim.v

@@ -618,6 +618,21 @@ module OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);
 	parameter HWL = "false";
 endmodule
 
+module OSER4_MEM (Q0, Q1, D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET)  ;
+    parameter GSREN = "";
+    parameter LSREN = "";
+    parameter HWL = "";
+    parameter TCLK_SOURCE = "";
+    parameter TXCLK_POL = "";
+
+    input D0, D1, D2, D3;
+    input TX0, TX1;
+    input PCLK, FCLK, TCLK, RESET;
+    output  Q0,  Q1;
+
+    parameter ID = "";
+endmodule
+
 module OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);
 	output Q1;
 	output Q0;
@@ -729,6 +744,21 @@ RESET, CALIB, D);
 	parameter LSREN = "true";
 endmodule
 
+module IDES4_MEM (Q0, Q1, Q2, Q3, D, WADDR,
+RADDR, CALIB, PCLK, FCLK, ICLK, RESET)  ;
+parameter GSREN = "";
+parameter LSREN = "";
+
+input D, ICLK, FCLK, PCLK;
+input [2:0] WADDR;
+input [2:0] RADDR;
+input CALIB, RESET;
+
+output Q0,Q1,Q2,Q3;
+
+parameter ID = "";
+endmodule
+
 module IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
 RESET, CALIB, D);
 	input D;
@@ -842,6 +872,28 @@ module IDDRC(D, CLK, CLEAR, Q0, Q1);
 	parameter Q1_INIT = 1'b0;
 endmodule
 
+module DQS(DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID, RBURST, RFLAG,
+WFLAG, DQSIN, DLLSTEP, WSTEP, READ, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR,
+HOLD, RCLKSEL, PCLK, FCLK, RESET) ;
+    input DQSIN,PCLK,FCLK,RESET;
+    input [3:0] READ;
+    input [2:0] RCLKSEL;
+    input [7:0] DLLSTEP;
+    input [7:0] WSTEP;
+    input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;
+
+    output DQSR90, DQSW0, DQSW270;
+    output [2:0] RPOINT, WPOINT;
+    output RVALID,RBURST, RFLAG, WFLAG;
+
+    parameter FIFO_MODE_SEL = "";
+    parameter RD_PNTR = "";
+    parameter DQS_MODE = "";
+    parameter HWL = "";
+    parameter GSREN = "";
+    parameter ID = "";
+endmodule
+
 (* blackbox *)
 module ODDR(D0, D1, TX, CLK, Q0, Q1);
 	input D0;

yowasp_yosys/share/nanoxplore/arith_map.v

@@ -0,0 +1,76 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2024  Miodrag Milanovic <micko@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+(* techmap_celltype = "$alu" *)
+module _80_nx_cy_alu (A, B, CI, BI, X, Y, CO);
+	parameter A_SIGNED = 0;
+	parameter B_SIGNED = 0;
+	parameter A_WIDTH = 1;
+	parameter B_WIDTH = 1;
+	parameter Y_WIDTH = 1;
+
+	(* force_downto *)
+	input [A_WIDTH-1:0] A;
+	(* force_downto *)
+	input [B_WIDTH-1:0] B;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] X, Y;
+
+	input CI, BI;
+	(* force_downto *)
+	output [Y_WIDTH-1:0] CO;
+    (* force_downto *)
+    wire [Y_WIDTH-1:0] COx;
+
+	wire _TECHMAP_FAIL_ = Y_WIDTH <= 2;
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] A_buf, B_buf;
+	\$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf));
+	\$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf));
+
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] AA = A_buf;
+	(* force_downto *)
+	wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
+
+	genvar i;
+	generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
+		NX_CY_1BIT #(.first(i==0))
+			alu_i (
+			.CI(i==0 ? CI : COx[i-1]),
+			.A(AA[i]),
+			.B(BB[i]),
+			.S(Y[i]),
+			.CO(COx[i])
+		);
+
+	end: slice
+	endgenerate
+
+	NX_CY_1BIT alu_cout(
+		.CI(COx[Y_WIDTH-1]),
+		.A(1'b0),
+		.B(1'b0),
+		.S(CO[Y_WIDTH-1])
+	);
+
+   /* End implementation */
+   assign X = AA ^ BB;
+endmodule

yowasp_yosys/share/nanoxplore/brams.txt

@@ -0,0 +1,50 @@
+ram block $__NX_RAM_ {
+	option "STD_MODE" "NOECC_48kx1" {
+		# only 32k used
+		abits 15;
+		widths 1 per_port;
+	}
+	option "STD_MODE" "NOECC_24kx2" {
+		# only 16k used
+		abits 14;
+		widths 2 per_port;
+	}
+	ifndef IS_NG_MEDIUM {
+		option "STD_MODE" "NOECC_16kx3" {
+			abits 14;
+			widths 3 per_port;
+		}
+	}
+	option "STD_MODE" "NOECC_12kx4" {
+		# only 8k used
+		abits 13;
+		widths 4 per_port;
+	}
+	ifndef IS_NG_MEDIUM {
+		option "STD_MODE" "NOECC_8kx6" {
+			abits 13;
+			widths 6 per_port;
+		}
+	}
+	option "STD_MODE" "NOECC_6kx8" {
+		# only 4k used
+		abits 12;
+		widths 8 per_port;
+	}
+	option "STD_MODE" "NOECC_4kx12" {
+		abits 12;
+		widths 12 per_port;
+	}
+	option "STD_MODE" "NOECC_2kx24" {
+		abits 11;
+		widths 24 per_port;
+	}
+	cost 64;
+	init no_undef;
+	port srsw "A" "B" {
+		clock anyedge;
+		clken;
+		rdwr no_change;
+		rdinit none;
+	}
+}

yowasp_yosys/share/nanoxplore/brams_init.vh

@@ -0,0 +1,23 @@
+function [409600-1:0] bram_init_to_string;
+    input [49152-1:0] array;
+    input integer blocks;
+    input integer width;
+    reg [409600-1:0] temp; // (49152+2048)*8 48K bit data + 2k commas
+    reg [24-1:0] temp2; 
+    integer i;
+    integer j;
+begin
+    temp = "";
+    for (i = 0; i < 2048; i = i + 1) begin
+        if (i != 0) begin
+            temp = {temp, ","};
+        end
+        temp2 = 24'b0;
+        for (j = 0; j < blocks; j = j + 1) begin
+            temp2[j*width +: width] = array[{j, i[10:0]}*width +: width];
+        end
+        temp = {temp, $sformatf("%b",temp2[23:0])};
+    end
+    bram_init_to_string = temp;
+end
+endfunction

yowasp_yosys/share/nanoxplore/brams_map.v

@@ -0,0 +1,84 @@
+module $__NX_RAM_ (...);
+
+parameter INIT = 0;
+parameter OPTION_STD_MODE = "NOECC_24kx2";
+
+parameter PORT_A_WIDTH = 24;
+parameter PORT_B_WIDTH = 24;
+
+parameter PORT_A_CLK_POL = 1;
+
+input PORT_A_CLK;
+input PORT_A_CLK_EN;
+input PORT_A_WR_EN;
+input [15:0] PORT_A_ADDR;
+input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
+wire [24-1:0] A_DATA;
+output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
+
+parameter PORT_B_CLK_POL = 1;
+
+input PORT_B_CLK;
+input PORT_B_CLK_EN;
+input PORT_B_WR_EN;
+input [15:0] PORT_B_ADDR;
+input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
+wire [24-1:0] B_DATA;
+output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
+
+`include "brams_init.vh"
+
+localparam raw_config1_val = OPTION_STD_MODE == "NOECC_48kx1" ? 16'b0000000000000000:
+                             OPTION_STD_MODE == "NOECC_24kx2" ? 16'b0000001001001001:
+                             OPTION_STD_MODE == "NOECC_16kx3" ? 16'b0000110110110110:
+                             OPTION_STD_MODE == "NOECC_12kx4" ? 16'b0000010010010010:
+                             OPTION_STD_MODE == "NOECC_8kx6"  ? 16'b0000111111111111:
+                             OPTION_STD_MODE == "NOECC_6kx8"  ? 16'b0000011011011011:
+                             OPTION_STD_MODE == "NOECC_4kx12" ? 16'b0000100100100100:
+                             OPTION_STD_MODE == "NOECC_2kx24" ? 16'b0000101101101101:
+                             16'bx;
+
+localparam A_REPEAT  =  24 / PORT_A_WIDTH;
+localparam B_REPEAT  =  24 / PORT_B_WIDTH;
+
+assign A_DATA = {A_REPEAT{PORT_A_WR_DATA[PORT_A_WIDTH-1:0]}};
+assign B_DATA = {B_REPEAT{PORT_B_WR_DATA[PORT_B_WIDTH-1:0]}};
+
+NX_RAM_WRAP #(
+    .std_mode(OPTION_STD_MODE),
+    .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .raw_config0(4'b0000),
+    .raw_config1(raw_config1_val[15:0]),
+    .mem_ctxt($sformatf("%s",bram_init_to_string(INIT,A_REPEAT,PORT_A_WIDTH))),
+) _TECHMAP_REPLACE_ (
+    .ACK(PORT_A_CLK),
+    //.ACKS(PORT_A_CLK),
+    //.ACKD(), // Not used in Non-ECC modes
+    //.ACKR(),
+    //.AR(),
+    //.ACOR(),
+    //.AERR(),
+    .ACS(PORT_A_CLK_EN),
+    .AWE(PORT_A_WR_EN),
+
+    .AA(PORT_A_ADDR),
+    .AI(A_DATA),
+    .AO(PORT_A_RD_DATA),
+
+    .BCK(PORT_B_CLK),
+    //.BCKC(PORT_B_CLK),
+    //.BCKD(), // Not used in Non-ECC modes
+    //.BCKR()
+    //.BR(),
+    //.BCOR(),
+    //.BERR(),
+    .BCS(PORT_B_CLK_EN),
+    .BWE(PORT_B_WR_EN),
+    .BA(PORT_B_ADDR),
+    .BI(B_DATA),
+    .BO(PORT_B_RD_DATA)
+);
+endmodule

yowasp_yosys/share/nanoxplore/cells_bb.v

@@ -0,0 +1,127 @@
+// NX_RAM related
+(* blackbox *)
+module NX_ECC(CKD, CHK, COR, ERR);
+    input CHK;
+    input CKD;
+    output COR;
+    output ERR;
+endmodule
+
+//TODO
+(* blackbox *)
+module NX_IOM_BIN2GRP(GS, DS, GVON, GVIN, GVDN, PA, LA);
+    input [1:0] DS;
+    input GS;
+    output [2:0] GVDN;
+    output [2:0] GVIN;
+    output [2:0] GVON;
+    input [5:0] LA;
+    output [3:0] PA;
+endmodule
+
+//TODO
+(* blackbox *)
+module NX_SER(FCK, SCK, R, IO, DCK, DRL, I, DS, DRA, DRI, DRO, DID);
+    input DCK;
+    output [5:0] DID;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    input FCK;
+    input [4:0] I;
+    output IO;
+    input R;
+    input SCK;
+    parameter data_size = 5;
+    parameter differential = "";
+    parameter drive = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter slewRate = "";
+    parameter spath_dynamic = 1'b0;
+    parameter standard = "";
+endmodule
+
+//TODO
+(* blackbox *)
+module NX_DES(FCK, SCK, R, IO, DCK, DRL, DIG, FZ, FLD, FLG, O, DS, DRA, DRI, DRO, DID);
+    input DCK;
+    output [5:0] DID;
+    input DIG;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    input FCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input IO;
+    output [4:0] O;
+    input R;
+    input SCK;
+    parameter data_size = 5;
+    parameter differential = "";
+    parameter dpath_dynamic = 1'b0;
+    parameter drive = "";
+    parameter inputDelayLine = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+endmodule
+
+//TODO
+(* blackbox *)
+module NX_SERDES(FCK, SCK, RTX, RRX, CI, CCK, CL, CR, IO, DCK, DRL, DIG, FZ, FLD, FLG, I, O, DS, DRA, DRI, DRO
+, DID);
+    input CCK;
+    input CI;
+    input CL;
+    input CR;
+    input DCK;
+    output [5:0] DID;
+    input DIG;
+    input [5:0] DRA;
+    input [5:0] DRI;
+    input DRL;
+    output [5:0] DRO;
+    input [1:0] DS;
+    input FCK;
+    output FLD;
+    output FLG;
+    input FZ;
+    input [4:0] I;
+    inout IO;
+    output [4:0] O;
+    input RRX;
+    input RTX;
+    input SCK;
+    parameter cpath_registered = 1'b0;
+    parameter data_size = 5;
+    parameter differential = "";
+    parameter dpath_dynamic = 1'b0;
+    parameter drive = "";
+    parameter inputDelayLine = "";
+    parameter inputSignalSlope = "";
+    parameter location = "";
+    parameter locked = 1'b0;
+    parameter outputCapacity = "";
+    parameter outputDelayLine = "";
+    parameter slewRate = "";
+    parameter spath_dynamic = 1'b0;
+    parameter standard = "";
+    parameter termination = "";
+    parameter terminationReference = "";
+    parameter turbo = "";
+    parameter weakTermination = "";
+endmodule