yowasp-yosys 0.43.0.0.post751__py3-none-any.whl → 0.45.0.0.post775__py3-none-any.whl

yowasp_yosys/share/gowin/cells_sim.v

@@ -618,6 +618,21 @@ module OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);
 	parameter HWL = "false";
 endmodule
 
+module OSER4_MEM (Q0, Q1, D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET)  ;
+    parameter GSREN = "";
+    parameter LSREN = "";
+    parameter HWL = "";
+    parameter TCLK_SOURCE = "";
+    parameter TXCLK_POL = "";
+
+    input D0, D1, D2, D3;
+    input TX0, TX1;
+    input PCLK, FCLK, TCLK, RESET;
+    output  Q0,  Q1;
+
+    parameter ID = "";
+endmodule
+
 module OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0);
 	output Q1;
 	output Q0;
@@ -729,6 +744,21 @@ RESET, CALIB, D);
 	parameter LSREN = "true";
 endmodule
 
+module IDES4_MEM (Q0, Q1, Q2, Q3, D, WADDR,
+RADDR, CALIB, PCLK, FCLK, ICLK, RESET)  ;
+parameter GSREN = "";
+parameter LSREN = "";
+
+input D, ICLK, FCLK, PCLK;
+input [2:0] WADDR;
+input [2:0] RADDR;
+input CALIB, RESET;
+
+output Q0,Q1,Q2,Q3;
+
+parameter ID = "";
+endmodule
+
 module IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK,
 RESET, CALIB, D);
 	input D;
@@ -842,6 +872,28 @@ module IDDRC(D, CLK, CLEAR, Q0, Q1);
 	parameter Q1_INIT = 1'b0;
 endmodule
 
+module DQS(DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID, RBURST, RFLAG,
+WFLAG, DQSIN, DLLSTEP, WSTEP, READ, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR,
+HOLD, RCLKSEL, PCLK, FCLK, RESET) ;
+    input DQSIN,PCLK,FCLK,RESET;
+    input [3:0] READ;
+    input [2:0] RCLKSEL;
+    input [7:0] DLLSTEP;
+    input [7:0] WSTEP;
+    input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD;
+
+    output DQSR90, DQSW0, DQSW270;
+    output [2:0] RPOINT, WPOINT;
+    output RVALID,RBURST, RFLAG, WFLAG;
+
+    parameter FIFO_MODE_SEL = "";
+    parameter RD_PNTR = "";
+    parameter DQS_MODE = "";
+    parameter HWL = "";
+    parameter GSREN = "";
+    parameter ID = "";
+endmodule
+
 (* blackbox *)
 module ODDR(D0, D1, TX, CLK, Q0, Q1);
 	input D0;
@@ -867,8 +919,12 @@ module ODDRC(D0, D1, CLEAR, TX, CLK, Q0, Q1);
 	parameter INIT = 0;
 endmodule
 
+(* blackbox, keep *)
 module GSR (input GSRI);
-	wire GSRO = GSRI;
+endmodule
+
+(* blackbox, keep *)
+module BANDGAP (input BGEN);
 endmodule
 
 (* abc9_box, lib_whitebox *)
@@ -1901,3 +1957,14 @@ output OSCOUT;
 parameter FREQ_DIV = 100;
 parameter REGULATOR_EN = 1'b0;
 endmodule
+
+(* blackbox *)
+module DCS (CLK0, CLK1, CLK2, CLK3, CLKSEL, SELFORCE, CLKOUT);
+input CLK0, CLK1, CLK2, CLK3, SELFORCE;
+input [3:0] CLKSEL;
+output CLKOUT;
+parameter DCS_MODE = "RISING";
+endmodule
+
+
+

yowasp_yosys/share/gowin/cells_xtra.v

@@ -1564,12 +1564,6 @@ parameter IDLE    =  4'd0,
 		  RD_S2   =  4'd12;
 endmodule
 
-module DCS (...);
-input CLK0, CLK1, CLK2, CLK3, SELFORCE;
-input [3:0] CLKSEL;
-output CLKOUT;
-endmodule
-
 module DQCE (...);
 input CLKIN;
 input CE;
@@ -1687,10 +1681,6 @@ endmodule
 module ADC (...);
 endmodule
 
-module BANDGAP (...);
-input BGEN;
-endmodule
-
 module CLKDIV2 (...);
 parameter GSREN = "false"; 
 input HCLKIN, RESETN;

yowasp_yosys/share/include/frontends/ast/ast.h

@@ -17,7 +17,9 @@
  *
  *  ---
  *
- *  This is support code for the Verilog frontend at frontends/verilog
+ *  The AST frontend library is not a frontend on its own but provides an
+ *  abstract syntax tree (AST) abstraction for the open source Verilog frontend
+ *  at frontends/verilog.
  *
  */
 

yowasp_yosys/share/include/kernel/bitpattern.h

@@ -0,0 +1,161 @@
+/*
+ *  yosys -- Yosys Open SYnthesis Suite
+ *
+ *  Copyright (C) 2012  Claire Xenia Wolf <claire@yosyshq.com>
+ *
+ *  Permission to use, copy, modify, and/or distribute this software for any
+ *  purpose with or without fee is hereby granted, provided that the above
+ *  copyright notice and this permission notice appear in all copies.
+ *
+ *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef BITPATTERN_H
+#define BITPATTERN_H
+
+#include "kernel/log.h"
+#include "kernel/rtlil.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+struct BitPatternPool
+{
+	int width;
+	struct bits_t {
+		std::vector<RTLIL::State> bitdata;
+		mutable unsigned int cached_hash;
+		bits_t(int width = 0) : bitdata(width), cached_hash(0) { }
+		RTLIL::State &operator[](int index) {
+			return bitdata[index];
+		}
+		const RTLIL::State &operator[](int index) const {
+			return bitdata[index];
+		}
+		bool operator==(const bits_t &other) const {
+			if (hash() != other.hash())
+				return false;
+			return bitdata == other.bitdata;
+		}
+		unsigned int hash() const {
+			if (!cached_hash)
+				cached_hash = hash_ops<std::vector<RTLIL::State>>::hash(bitdata);
+			return cached_hash;
+		}
+	};
+	pool<bits_t> database;
+
+	BitPatternPool(RTLIL::SigSpec sig)
+	{
+		width = sig.size();
+		if (width > 0) {
+			bits_t pattern(width);
+			for (int i = 0; i < width; i++) {
+				if (sig[i].wire == NULL && sig[i].data <= RTLIL::State::S1)
+					pattern[i] = sig[i].data;
+				else
+					pattern[i] = RTLIL::State::Sa;
+			}
+			database.insert(pattern);
+		}
+	}
+
+	BitPatternPool(int width)
+	{
+		this->width = width;
+		if (width > 0) {
+			bits_t pattern(width);
+			for (int i = 0; i < width; i++)
+				pattern[i] = RTLIL::State::Sa;
+			database.insert(pattern);
+		}
+	}
+
+	bits_t sig2bits(RTLIL::SigSpec sig)
+	{
+		bits_t bits;
+		bits.bitdata = sig.as_const().bits;
+		for (auto &b : bits.bitdata)
+			if (b > RTLIL::State::S1)
+				b = RTLIL::State::Sa;
+		return bits;
+	}
+
+	bool match(bits_t a, bits_t b)
+	{
+		log_assert(int(a.bitdata.size()) == width);
+		log_assert(int(b.bitdata.size()) == width);
+		for (int i = 0; i < width; i++)
+			if (a[i] <= RTLIL::State::S1 && b[i] <= RTLIL::State::S1 && a[i] != b[i])
+				return false;
+		return true;
+	}
+
+	bool has_any(RTLIL::SigSpec sig)
+	{
+		bits_t bits = sig2bits(sig);
+		for (auto &it : database)
+			if (match(it, bits))
+				return true;
+		return false;
+	}
+
+	bool has_all(RTLIL::SigSpec sig)
+	{
+		bits_t bits = sig2bits(sig);
+		for (auto &it : database)
+			if (match(it, bits)) {
+				for (int i = 0; i < width; i++)
+					if (bits[i] > RTLIL::State::S1 && it[i] <= RTLIL::State::S1)
+						goto next_database_entry;
+				return true;
+	next_database_entry:;
+			}
+		return false;
+	}
+
+	bool take(RTLIL::SigSpec sig)
+	{
+		bool status = false;
+		bits_t bits = sig2bits(sig);
+		for (auto it = database.begin(); it != database.end();)
+			if (match(*it, bits)) {
+				for (int i = 0; i < width; i++) {
+					if ((*it)[i] != RTLIL::State::Sa || bits[i] == RTLIL::State::Sa)
+						continue;
+					bits_t new_pattern;
+					new_pattern.bitdata = it->bitdata;
+					new_pattern[i] = bits[i] == RTLIL::State::S1 ? RTLIL::State::S0 : RTLIL::State::S1;
+					database.insert(new_pattern);
+				}
+				it = database.erase(it);
+				status = true;
+				continue;
+			} else
+				++it;
+		return status;
+	}
+
+	bool take_all()
+	{
+		if (database.empty())
+			return false;
+		database.clear();
+		return true;
+	}
+
+	bool empty()
+	{
+		return database.empty();
+	}
+};
+
+YOSYS_NAMESPACE_END
+
+#endif

yowasp_yosys/share/include/kernel/cost.h

@@ -26,7 +26,17 @@ YOSYS_NAMESPACE_BEGIN
 
 struct CellCosts
 {
+
+	private:
+	dict<RTLIL::IdString, int> mod_cost_cache_;
+	Design *design_ = nullptr;
+
+	public:
+	CellCosts(RTLIL::Design *design) : design_(design) { }
+
 	static const dict<RTLIL::IdString, int>& default_gate_cost() {
+		// Default size heuristics for several common PDK standard cells
+		// used by abc and stat
 		static const dict<RTLIL::IdString, int> db = {
 			{ ID($_BUF_),    1 },
 			{ ID($_NOT_),    2 },
@@ -43,12 +53,14 @@ struct CellCosts
 			{ ID($_AOI4_),   7 },
 			{ ID($_OAI4_),   7 },
 			{ ID($_MUX_),    4 },
-			{ ID($_NMUX_),   4 }
+			{ ID($_NMUX_),   4 },
 		};
 		return db;
 	}
 
 	static const dict<RTLIL::IdString, int>& cmos_gate_cost() {
+		// Estimated CMOS transistor counts for several common PDK standard cells
+		// used by stat and optionally by abc
 		static const dict<RTLIL::IdString, int> db = {
 			{ ID($_BUF_),     1 },
 			{ ID($_NOT_),     2 },
@@ -65,50 +77,21 @@ struct CellCosts
 			{ ID($_AOI4_),    8 },
 			{ ID($_OAI4_),    8 },
 			{ ID($_MUX_),    12 },
-			{ ID($_NMUX_),   10 }
+			{ ID($_NMUX_),   10 },
+			{ ID($_DFF_P_),  16 },
+			{ ID($_DFF_N_),  16 },
 		};
 		return db;
 	}
 
-	dict<RTLIL::IdString, int> mod_cost_cache;
-	const dict<RTLIL::IdString, int> *gate_cost = nullptr;
-	Design *design = nullptr;
-
-	int get(RTLIL::IdString type) const
-	{
-		if (gate_cost && gate_cost->count(type))
-			return gate_cost->at(type);
-
-		log_warning("Can't determine cost of %s cell.\n", log_id(type));
-		return 1;
-	}
-
-	int get(RTLIL::Cell *cell)
-	{
-		if (gate_cost && gate_cost->count(cell->type))
-			return gate_cost->at(cell->type);
-
-		if (design && design->module(cell->type) && cell->parameters.empty())
-		{
-			RTLIL::Module *mod = design->module(cell->type);
-
-			if (mod->attributes.count(ID(cost)))
-				return mod->attributes.at(ID(cost)).as_int();
-
-			if (mod_cost_cache.count(mod->name))
-				return mod_cost_cache.at(mod->name);
-
-			int module_cost = 1;
-			for (auto c : mod->cells())
-				module_cost += get(c);
-
-			mod_cost_cache[mod->name] = module_cost;
-			return module_cost;
-		}
-
-		log_warning("Can't determine cost of %s cell (%d parameters).\n", log_id(cell->type), GetSize(cell->parameters));
-		return 1;
-	}
+	// Get the cell cost for a cell based on its parameters.
+	// This cost is an *approximate* upper bound for the number of gates that
+	// the cell will get mapped to with "opt -fast; techmap"
+	// The intended usage is for flattening heuristics and similar situations
+	unsigned int get(RTLIL::Cell *cell);
+	// Sum up the cell costs of all cells in the module
+	// and all its submodules recursively
+	unsigned int get(RTLIL::Module *mod);
 };
 
 YOSYS_NAMESPACE_END

yowasp_yosys/share/include/kernel/hashlib.h

@@ -188,6 +188,7 @@ inline unsigned int mkhash(const T &v) {
 
 inline int hashtable_size(int min_size)
 {
+	// Primes as generated by https://oeis.org/A175953
 	static std::vector<int> zero_and_some_primes = {
 		0, 23, 29, 37, 47, 59, 79, 101, 127, 163, 211, 269, 337, 431, 541, 677,
 		853, 1069, 1361, 1709, 2137, 2677, 3347, 4201, 5261, 6577, 8231, 10289,
@@ -196,7 +197,9 @@ inline int hashtable_size(int min_size)
 		897133, 1121423, 1401791, 1752239, 2190299, 2737937, 3422429, 4278037,
 		5347553, 6684443, 8355563, 10444457, 13055587, 16319519, 20399411,
 		25499291, 31874149, 39842687, 49803361, 62254207, 77817767, 97272239,
-		121590311, 151987889, 189984863, 237481091, 296851369, 371064217
+		121590311, 151987889, 189984863, 237481091, 296851369, 371064217,
+		463830313, 579787991, 724735009, 905918777, 1132398479, 1415498113,
+		1769372713
 	};
 
 	for (auto p : zero_and_some_primes)
@@ -1129,6 +1132,11 @@ public:
 	const_iterator end() const { return const_iterator(*this, offset + size()); }
 };
 
+/**
+ * Union-find data structure with a promotion method
+ * mfp stands for "merge, find, promote"
+ * i-prefixed methods operate on indices in parents
+*/
 template<typename K, typename OPS>
 class mfp
 {
@@ -1142,13 +1150,18 @@ public:
 	{
 	}
 
+	// Finds a given element's index. If it isn't in the data structure,
+	// it is added as its own set
 	int operator()(const K &key) const
 	{
 		int i = database(key);
+		// If the lookup caused the database to grow,
+		// also add a corresponding entry in parents initialized to -1 (no parent)
 		parents.resize(database.size(), -1);
 		return i;
 	}
 
+	// Finds an element at given index
 	const K &operator[](int index) const
 	{
 		return database[index];
@@ -1161,6 +1174,11 @@ public:
 		while (parents[p] != -1)
 			p = parents[p];
 
+		// p is now the representative of i
+		// Now we traverse from i up to the representative again
+		// and make p the parent of all the nodes along the way.
+		// This is a side effect and doesn't affect the return value.
+		// It speeds up future find operations
 		while (k != p) {
 			int next_k = parents[k];
 			parents[k] = p;
@@ -1170,6 +1188,7 @@ public:
 		return p;
 	}
 
+	// Merge sets if the given indices belong to different sets
 	void imerge(int i, int j)
 	{
 		i = ifind(i);

yowasp_yosys/share/include/kernel/sigtools.h

@@ -229,6 +229,13 @@ using sort_by_name_id_guard = typename std::enable_if<std::is_same<T,RTLIL::Cell
 template<typename T>
 class SigSet<T, sort_by_name_id_guard<T>> : public SigSet<T, RTLIL::sort_by_name_id<typename std::remove_pointer<T>::type>> {};
 
+/**
+ * SigMap wraps a union-find "database"
+ * to map SigBits of a module to canonical representative SigBits.
+ * SigBits that are connected share a set in the underlying database.
+ * If a SigBit has a const state (impl: bit.wire is nullptr),
+ * it's promoted to a representative.
+ */
 struct SigMap
 {
 	mfp<SigBit> database;
@@ -249,6 +256,7 @@ struct SigMap
 		database.clear();
 	}
 
+	// Rebuild SigMap for all connections in module
 	void set(RTLIL::Module *module)
 	{
 		int bitcount = 0;
@@ -262,6 +270,7 @@ struct SigMap
 			add(it.first, it.second);
 	}
 
+	// Add connections from "from" to "to", bit-by-bit
 	void add(const RTLIL::SigSpec& from, const RTLIL::SigSpec& to)
 	{
 		log_assert(GetSize(from) == GetSize(to));
@@ -287,6 +296,7 @@ struct SigMap
 		}
 	}
 
+	// Add sig as disconnected from anything
 	void add(const RTLIL::SigBit &bit)
 	{
 		const auto &b = database.find(bit);
@@ -302,6 +312,7 @@ struct SigMap
 
 	inline void add(Wire *wire) { return add(RTLIL::SigSpec(wire)); }
 
+	// Modify bit to its representative
 	void apply(RTLIL::SigBit &bit) const
 	{
 		bit = database.find(bit);
@@ -332,6 +343,7 @@ struct SigMap
 		return sig;
 	}
 
+	// All non-const bits
 	RTLIL::SigSpec allbits() const
 	{
 		RTLIL::SigSpec sig;

yowasp_yosys/share/microchip/LSRAM.txt

@@ -0,0 +1,191 @@
+# ISC License
+# 
+# Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
+# 
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+# 
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+# ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+
+
+
+# LSRAM true dual-port
+ram block $__LSRAM_TDP_ {
+
+	# Cost of a given cell is assumed to be:
+	#   (cost-widthscale) + [widthscale * (used_bits/14)]
+	cost 129;
+
+	# INIT is supported
+	init any;
+
+	# port A and port B are allowed to have different widths, but they MUST have
+	# 	WIDTH values of the same set. 
+	#      Example: Port A has a Data Width of 1. Then Port B's Data Width must be either
+	#      1, 2, 4, 8, or 16 (both values are in the 'WIDTH_1' set).	
+	# 	WIDTH_1 = {1, 2, 4, 8, 16}
+	# 	WIDTH_2 = {5, 10, 20}
+
+	# "byte" specifies how many data bits correspond to one write enable bit.
+	#		"byte" must be larger than width, or width must be a multipler of "byte"
+	#		if "byte" > WIDTH, a single enable wire is inferred
+	#		otherwise, WIDTH/byte number of enable wires are inferred
+	# 		
+	# 		WIDTH = {1, 2, 4, 5, 8, 10} requires 1 enable wire
+	# 		WIDTH = {16, 20} requires 2 enable wire
+
+	option "WIDTH_CONFIG" "REGULAR" {
+
+		# Data-Width| Address bits
+		# 1 		| 14
+		# 2 		| 13
+		# 4 		| 12
+		# 8 		| 11
+		# 16		| 10
+
+		# 14 address bits
+		abits 14;
+
+		widths 1 2 4 8 16 per_port;
+		byte 8;
+	}
+	option "WIDTH_CONFIG" "ALIGN" {
+		
+		# Data-Width| Address bits
+		# 5 		| 12
+		# 10		| 11
+		# 20		| 10
+
+		# Quick "hack" to fix address bit alignment by setting address bits to 12.
+		#   If abits=14, tool will think there are 14 bits for width=5, 13 bits for width=10, 12 bits for width=20
+		#   THe LSRAM_map.v file detects if this option is being used, and adjusts the address port alignments accordingly.
+		abits 12;
+
+		widths 5 10 20 per_port;
+		byte 10;
+	}
+	
+	
+
+	port srsw "A" "B" {
+
+		# read & write width must be same
+		width tied;
+		
+		# clock polarity is rising
+		clock posedge;
+
+		# A/B read-enable
+		rden;
+
+
+		# initial value of read port data (not supported)
+		rdinit none;
+
+		# write modes (<A/B>_WMODE)
+		# 	1. Simple Write: read-data port holds prev value (similar to "NO_CHANGE" for RAMB18E1)
+		# 	2. Feed-through: read-data port takes new write value (similar to "WRITE_FIRST" for RAMB18E1)
+		# 	3. Read-Before-Write: read-data port holds old value while being written (similar to "READ_FIRST" for RAMB18E1)
+
+		portoption "WRITE_MODE" "NO_CHANGE" {
+
+			# Read-write interaction
+			rdwr no_change;
+
+			# Write transparency:
+			#   For write ports, define behaviour when another synchronous read port 
+			#   reads from the same memory cell that said write port is writing to at the same time. 
+			wrtrans all old;
+		}
+		portoption "WRITE_MODE" "WRITE_FIRST" {
+			# bits corresponding to high A/B_WEN are updated
+			rdwr new_only;
+			wrtrans all new;
+		}
+		portoption "WRITE_MODE" "READ_FIRST" {
+			rdwr old;
+
+			wrtrans all old;
+		}
+
+		# generate params to indicate if read or write is used for each port
+		optional_rw;
+	}
+}
+
+# two-port configuration
+ram block $__LSRAM_SDP_ {
+	
+	# since two-port configuration is dedicated for wide-read/write,
+	#	we want to prioritize this configuration over TDP to avoid tool picking multiple TDP RAMs 
+	#	inplace of a single SDP RAM for wide read/write. This means the cost of a single SDP should
+	#	be less than 2 TDP.
+	cost 129;
+	init any;
+
+	option "WIDTH_CONFIG" "REGULAR" {
+
+		# Data-Width| Address bits
+		# 1 		| 14
+		# 2 		| 13
+		# 4 		| 12
+		# 8 		| 11
+		# 16		| 10
+		# 32		| 9
+
+		abits 14;
+
+		widths 1 2 4 8 16 32 per_port;
+
+		# width = 32, byte-write size is 8, ignore other widths
+		byte 8;
+		
+	}
+	option "WIDTH_CONFIG" "ALIGN" {
+		
+		# Data-Width| Address bits
+		# 5 		| 12
+		# 10		| 11
+		# 20		| 10
+		# 40		| 9
+
+		# Same trick as TSP RAM for alignment
+		abits 12;
+		widths 5 10 20 40 per_port;
+		byte 10;
+	}
+
+	port sw "W" {
+
+		# only consider wide write
+		
+		option "WIDTH_CONFIG" "REGULAR" width 32;
+		option "WIDTH_CONFIG" "ALIGN" width 40;
+
+		clock posedge;
+
+		# only simple write supported for two-port mode
+		wrtrans all old;
+		
+		optional;
+	}
+	port sr "R" {
+
+		option "WIDTH_CONFIG" "REGULAR" width 32;
+		option "WIDTH_CONFIG" "ALIGN" width 40;
+
+
+		clock posedge;
+		rden;
+		rdinit none;
+		optional;
+	}
+}