yowasp-yosys 0.40.0.0.post707__py3-none-any.whl → 0.40.0.68.post721.dev0__py3-none-any.whl

yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h

@@ -941,6 +941,55 @@ struct metadata {
 		assert(value_type == DOUBLE);
 		return double_value;
 	}
+
+	// Internal CXXRTL use only.
+	static std::map<std::string, metadata> deserialize(const char *ptr) {
+		std::map<std::string, metadata> result;
+		std::string name;
+		// Grammar:
+		// string   ::= [^\0]+ \0
+		// metadata ::= [uid] .{8} | s <string>
+		// map      ::= ( <string> <metadata> )* \0
+		for (;;) {
+			if (*ptr) {
+				name += *ptr++;
+			} else if (!name.empty()) {
+				ptr++;
+				auto get_u64 = [&]() {
+					uint64_t result = 0;
+					for (size_t count = 0; count < 8; count++)
+						result = (result << 8) | *ptr++;
+					return result;
+				};
+				char type = *ptr++;
+				if (type == 'u') {
+					uint64_t value = get_u64();
+					result.emplace(name, value);
+				} else if (type == 'i') {
+					int64_t value = (int64_t)get_u64();
+					result.emplace(name, value);
+				} else if (type == 'd') {
+					double dvalue;
+					uint64_t uvalue = get_u64();
+					static_assert(sizeof(dvalue) == sizeof(uvalue), "double must be 64 bits in size");
+					memcpy(&dvalue, &uvalue, sizeof(dvalue));
+					result.emplace(name, dvalue);
+				} else if (type == 's') {
+					std::string value;
+					while (*ptr)
+						value += *ptr++;
+					ptr++;
+					result.emplace(name, value);
+				} else {
+					assert(false && "Unknown type specifier");
+					return result;
+				}
+				name.clear();
+			} else {
+				return result;
+			}
+		}
+	}
 };
 
 typedef std::map<std::string, metadata> metadata_map;
@@ -1417,6 +1466,12 @@ struct debug_items {
 			});
 	}
 
+	// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
+	template<class... T>
+	void add(const std::string &base_path, const char *path, const char *serialized_item_attrs, T&&... args) {
+		add(base_path + path, debug_item(std::forward<T>(args)...), metadata::deserialize(serialized_item_attrs));
+	}
+
 	size_t count(const std::string &path) const {
 		if (table.count(path) == 0)
 			return 0;
@@ -1463,6 +1518,11 @@ struct debug_scopes {
 		scope.cell_attrs = std::unique_ptr<debug_attrs>(new debug_attrs { cell_attrs });
 	}
 
+	// This overload exists to reduce excessive stack slot allocation in `CXXRTL_EXTREMELY_COLD void debug_info()`.
+	void add(const std::string &base_path, const char *path, const char *module_name, const char *serialized_module_attrs, const char *serialized_cell_attrs) {
+		add(base_path + path, module_name, metadata::deserialize(serialized_module_attrs), metadata::deserialize(serialized_cell_attrs));
+	}
+
 	size_t contains(const std::string &path) const {
 		return table.count(path);
 	}

yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h

@@ -512,9 +512,10 @@ public:
 	spool &operator=(const spool &) = delete;
 
 	~spool() {
-		if (int fd = writefd.exchange(-1))
+		int fd;
+		if ((fd = writefd.exchange(-1)) != -1)
 			close(fd);
-		if (int fd = readfd.exchange(-1))
+		if ((fd = readfd.exchange(-1)) != -1)
 			close(fd);
 	}
 

yowasp_yosys/share/include/kernel/constids.inc

@@ -222,6 +222,8 @@ X(_TECHMAP_REPLACE_)
 X(techmap_simplemap)
 X(_techmap_special_)
 X(techmap_wrap)
+X(_TECHMAP_PLACEHOLDER_)
+X(techmap_chtype)
 X(T_FALL_MAX)
 X(T_FALL_MIN)
 X(T_FALL_TYP)

yowasp_yosys/share/python3/sby_engine_abc.py

@@ -69,6 +69,14 @@ def run(mode, task, engine_idx, engine):
     if task.opt_aigfolds:
         fold_command += " -s"
 
+    prep_commands = []
+
+    for i, arg in reversed(list(enumerate(engine[1:], 1))):
+        if arg.endswith(';'):
+            prep_commands = engine[1:i + 1]
+            engine[1:] = engine[i + 1:]
+            break
+
     abc_command, custom_options, toggles = abc_getopt(engine[1:], [
         "keep-going",
     ])
@@ -116,6 +124,8 @@ def run(mode, task, engine_idx, engine):
     else:
         task.error(f"Invalid ABC command {abc_command[0]}.")
 
+    abc_command[0:0] = prep_commands
+
     smtbmc_vcd = task.opt_vcd and not task.opt_vcd_sim
     run_aigsmt = smtbmc_vcd or (task.opt_append and task.opt_append_assume)
     smtbmc_append = 0

yowasp_yosys/share/python3/smtio.py

@@ -160,6 +160,7 @@ class SmtIo:
             self.noincr = opts.noincr
             self.info_stmts = opts.info_stmts
             self.nocomments = opts.nocomments
+            self.smt2_options.update(opts.smt2_options)
 
         else:
             self.solver = "yices"
@@ -959,6 +960,8 @@ class SmtIo:
         return int(self.bv2bin(v), 2)
 
     def get_raw_unsat_assumptions(self):
+        if not self.smt2_assumptions:
+            return []
         self.write("(get-unsat-assumptions)")
         exprs = set(self.unparse(part) for part in self.parse(self.read()))
         unsat_assumptions = []
@@ -973,6 +976,10 @@ class SmtIo:
     def get_unsat_assumptions(self, minimize=False):
         if not minimize:
             return self.get_raw_unsat_assumptions()
+        orig_assumptions = self.smt2_assumptions
+
+        self.smt2_assumptions = dict(orig_assumptions)
+
         required_assumptions = {}
 
         while True:
@@ -998,6 +1005,7 @@ class SmtIo:
                     required_assumptions[candidate_key] = candidate_assume
 
             if candidate_assumptions is not None:
+                self.smt2_assumptions = orig_assumptions
                 return list(required_assumptions)
 
     def get(self, expr):
@@ -1146,7 +1154,7 @@ class SmtIo:
 class SmtOpts:
     def __init__(self):
         self.shortopts = "s:S:v"
-        self.longopts = ["unroll", "noincr", "noprogress", "timeout=", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments"]
+        self.longopts = ["unroll", "noincr", "noprogress", "timeout=", "dump-smt2=", "logic=", "dummy=", "info=", "nocomments", "smt2-option="]
         self.solver = "yices"
         self.solver_opts = list()
         self.debug_print = False
@@ -1159,6 +1167,7 @@ class SmtOpts:
         self.logic = None
         self.info_stmts = list()
         self.nocomments = False
+        self.smt2_options = {}
 
     def handle(self, o, a):
         if o == "-s":
@@ -1185,6 +1194,13 @@ class SmtOpts:
             self.info_stmts.append(a)
         elif o == "--nocomments":
             self.nocomments = True
+        elif o == "--smt2-option":
+            args = a.split('=', 1)
+            if len(args) != 2:
+                print("--smt2-option expects an <option>=<value> argument")
+                sys.exit(1)
+            option, value = args
+            self.smt2_options[option] = value
         else:
             return False
         return True
@@ -1208,6 +1224,9 @@ class SmtOpts:
         if solver is "dummy", read solver output from that file
         otherwise: write solver output to that file
 
+    --smt2-option <option>=<value>
+        enable an SMT-LIBv2 option.
+
     -v
         enable debug output
 

yowasp_yosys/share/quicklogic/qlf_k6n10f/bram_types_sim.v

@@ -1,5 +1,5 @@
 // **AUTOGENERATED FILE** **DO NOT EDIT**
-// Generated by ../yosys-src/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py at 2024-04-10 20:48:01.941850+00:00
+// Generated by ../yosys-src/techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py at 2024-05-08 05:20:44.526176+00:00
 `timescale 1ns /10ps
 
 module TDP36K_BRAM_A_X1_B_X1_nonsplit (

yowasp_yosys/smtbmc.py

@@ -199,7 +199,6 @@ def help():
 
     --minimize-assumes
         when using --track-assumes, solve for a minimal set of sufficient assumptions.
-
 """ + so.helpmsg())
 
 def usage():
@@ -670,18 +669,12 @@ if aimfile is not None:
 
 ywfile_hierwitness_cache = None
 
-def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False):
+def ywfile_hierwitness():
     global ywfile_hierwitness_cache
-    if map_steps is None:
-        map_steps = {}
-
-    with open(inywfile, "r") as f:
-        inyw = ReadWitness(f)
-
-        if ywfile_hierwitness_cache is None:
-            ywfile_hierwitness_cache = smt.hierwitness(topmod, allregs=True, blackbox=True)
+    if ywfile_hierwitness_cache is None:
+        ywfile_hierwitness = smt.hierwitness(topmod, allregs=True, blackbox=True)
 
-        inits, seqs, clocks, mems = ywfile_hierwitness_cache
+        inits, seqs, clocks, mems = ywfile_hierwitness
 
         smt_wires = defaultdict(list)
         smt_mems = defaultdict(list)
@@ -692,91 +685,147 @@ def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False):
         for mem in mems:
             smt_mems[mem["path"]].append(mem)
 
-        addr_re = re.compile(r'\\\[[0-9]+\]$')
-        bits_re = re.compile(r'[01?]*$')
+        ywfile_hierwitness_cache = inits, seqs, clocks, mems, smt_wires, smt_mems
 
-        max_t = -1
+    return ywfile_hierwitness_cache
 
-        for t, step in inyw.steps():
-            present_signals, missing = step.present_signals(inyw.sigmap)
-            for sig in present_signals:
-                bits = step[sig]
-                if skip_x:
-                    bits = bits.replace('x', '?')
-                if not bits_re.match(bits):
-                    raise ValueError("unsupported bit value in Yosys witness file")
+def_bits_re = re.compile(r'([01]+)')
 
-                sig_end = sig.offset + len(bits)
-                if sig.path in smt_wires:
-                    for wire in smt_wires[sig.path]:
-                        width, offset = wire["width"], wire["offset"]
+def smt_extract_mask(smt_expr, mask):
+    chunks = []
+    def_bits = ''
 
-                        smt_bool = smt.net_width(topmod, wire["smtpath"]) == 1
+    mask_index_order = mask[::-1]
 
-                        offset = max(offset, 0)
+    for matched in def_bits_re.finditer(mask_index_order):
+        chunks.append(matched.span())
+        def_bits += matched[0]
 
-                        end = width + offset
-                        common_offset = max(sig.offset, offset)
-                        common_end = min(sig_end, end)
-                        if common_end <= common_offset:
-                            continue
+    if not chunks:
+        return
 
-                        smt_expr = smt.witness_net_expr(topmod, f"s{map_steps.get(t, t)}", wire)
+    if len(chunks) == 1:
+        start, end = chunks[0]
+        if start == 0 and end == len(mask_index_order):
+            combined_chunks = smt_expr
+        else:
+            combined_chunks = '((_ extract %d %d) %s)' % (end - 1, start, smt_expr)
+    else:
+        combined_chunks = '(let ((x %s)) (concat %s))' % (smt_expr, ' '.join(
+            '((_ extract %d %d) x)' % (end - 1, start)
+            for start, end in reversed(chunks)
+        ))
 
-                        if not smt_bool:
-                            slice_high = common_end - offset - 1
-                            slice_low = common_offset - offset
-                            smt_expr = "((_ extract %d %d) %s)" % (slice_high, slice_low, smt_expr)
+    return combined_chunks, ''.join(mask_index_order[start:end] for start, end in chunks)[::-1]
 
-                        bit_slice = bits[len(bits) - (common_end - sig.offset):len(bits) - (common_offset - sig.offset)]
+def smt_concat(exprs):
+    if not exprs:
+        return ""
+    if len(exprs) == 1:
+        return exprs[1]
+    return "(concat %s)" % ' '.join(exprs)
 
-                        if bit_slice.count("?") == len(bit_slice):
-                            continue
+def ywfile_signal(sig, step, mask=None):
+    assert sig.width > 0
 
-                        if smt_bool:
-                            assert width == 1
-                            smt_constr = "(= %s %s)" % (smt_expr, "true" if bit_slice == "1" else "false")
-                        else:
-                            if "?" in bit_slice:
-                                mask = bit_slice.replace("0", "1").replace("?", "0")
-                                bit_slice = bit_slice.replace("?", "0")
-                                smt_expr = "(bvand %s #b%s)" % (smt_expr, mask)
+    inits, seqs, clocks, mems, smt_wires, smt_mems = ywfile_hierwitness()
+    sig_end = sig.offset + sig.width
 
-                            smt_constr = "(= %s #b%s)" % (smt_expr, bit_slice)
+    output = []
 
-                        constr_assumes[t].append((inywfile, smt_constr))
+    if sig.path in smt_wires:
+        for wire in smt_wires[sig.path]:
+            width, offset = wire["width"], wire["offset"]
 
-                if sig.memory_path:
-                    if sig.memory_path in smt_mems:
-                        for mem in smt_mems[sig.memory_path]:
-                            width, size, bv = mem["width"], mem["size"], mem["statebv"]
+            smt_bool = smt.net_width(topmod, wire["smtpath"]) == 1
 
-                            smt_expr = smt.net_expr(topmod, f"s{map_steps.get(t, t)}", mem["smtpath"])
+            offset = max(offset, 0)
 
-                            if bv:
-                                word_low = sig.memory_addr * width
-                                word_high = word_low + width - 1
-                                smt_expr = "((_ extract %d %d) %s)" % (word_high, word_low, smt_expr)
-                            else:
-                                addr_width = (size - 1).bit_length()
-                                addr_bits = f"{sig.memory_addr:0{addr_width}b}"
-                                smt_expr = "(select %s #b%s )" % (smt_expr, addr_bits)
+            end = width + offset
+            common_offset = max(sig.offset, offset)
+            common_end = min(sig_end, end)
+            if common_end <= common_offset:
+                continue
 
-                            if len(bits) < width:
-                                slice_high = sig.offset + len(bits) - 1
-                                smt_expr = "((_ extract %d %d) %s)" % (slice_high, sig.offset, smt_expr)
+            smt_expr = smt.witness_net_expr(topmod, f"s{step}", wire)
 
-                            bit_slice = bits
+            if not smt_bool:
+                slice_high = common_end - offset - 1
+                slice_low = common_offset - offset
+                smt_expr = "((_ extract %d %d) %s)" % (slice_high, slice_low, smt_expr)
+            else:
+                smt_expr = "(ite %s #b1 #b0)" % smt_expr
 
-                            if "?" in bit_slice:
-                                mask = bit_slice.replace("0", "1").replace("?", "0")
-                                bit_slice = bit_slice.replace("?", "0")
-                                smt_expr = "(bvand %s #b%s)" % (smt_expr, mask)
+            output.append(((common_offset - sig.offset), (common_end - sig.offset), smt_expr))
 
-                            smt_constr = "(= %s #b%s)" % (smt_expr, bit_slice)
-                            constr_assumes[t].append((inywfile, smt_constr))
-            max_t = t
+    if sig.memory_path:
+        if sig.memory_path in smt_mems:
+            for mem in smt_mems[sig.memory_path]:
+                width, size, bv = mem["width"], mem["size"], mem["statebv"]
+
+                smt_expr = smt.net_expr(topmod, f"s{step}", mem["smtpath"])
+
+                if bv:
+                    word_low = sig.memory_addr * width
+                    word_high = word_low + width - 1
+                    smt_expr = "((_ extract %d %d) %s)" % (word_high, word_low, smt_expr)
+                else:
+                    addr_width = (size - 1).bit_length()
+                    addr_bits = f"{sig.memory_addr:0{addr_width}b}"
+                    smt_expr = "(select %s #b%s )" % (smt_expr, addr_bits)
+
+                if sig.width < width:
+                    slice_high = sig.offset + sig.width - 1
+                    smt_expr = "((_ extract %d %d) %s)" % (slice_high, sig.offset, smt_expr)
 
+                output.append((0, sig.width, smt_expr))
+
+    output.sort()
+
+    output = [chunk for chunk in output if chunk[0] != chunk[1]]
+
+    pos = 0
+
+    for start, end, smt_expr in output:
+        assert start == pos
+        pos = end
+
+    assert pos == sig.width
+
+    if len(output) == 1:
+        return output[0][-1]
+    return smt_concat(smt_expr for start, end, smt_expr in reversed(output))
+
+def ywfile_constraints(inywfile, constr_assumes, map_steps=None, skip_x=False):
+    global ywfile_hierwitness_cache
+    if map_steps is None:
+        map_steps = {}
+
+    with open(inywfile, "r") as f:
+        inyw = ReadWitness(f)
+
+        inits, seqs, clocks, mems, smt_wires, smt_mems = ywfile_hierwitness()
+
+        bits_re = re.compile(r'[01?]*$')
+        max_t = -1
+
+        for t, step in inyw.steps():
+            present_signals, missing = step.present_signals(inyw.sigmap)
+            for sig in present_signals:
+                bits = step[sig]
+                if skip_x:
+                    bits = bits.replace('x', '?')
+                if not bits_re.match(bits):
+                    raise ValueError("unsupported bit value in Yosys witness file")
+
+                smt_expr = ywfile_signal(sig, map_steps.get(t, t))
+
+                smt_expr, bits = smt_extract_mask(smt_expr, bits)
+
+                smt_constr = "(= %s #b%s)" % (smt_expr, bits)
+                constr_assumes[t].append((inywfile, smt_constr))
+
+            max_t = t
         return max_t
 
 if inywfile is not None:
@@ -1367,11 +1416,11 @@ def write_yw_trace(steps, index, allregs=False, filename=None):
 
             exprs.extend(smt.witness_net_expr(topmod, f"s{k}", sig) for sig in sigs)
 
-            all_sigs.append(sigs)
+            all_sigs.append((step_values, sigs))
 
         bvs = iter(smt.get_list(exprs))
 
-        for sigs in all_sigs:
+        for (step_values, sigs) in all_sigs:
             for sig in sigs:
                 value = smt.bv2bin(next(bvs))
                 step_values[sig["sig"]] = value

{yowasp_yosys-0.40.0.0.post707.dist-info → yowasp_yosys-0.40.0.68.post721.dev0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: yowasp-yosys
-Version: 0.40.0.0.post707
+Version: 0.40.0.68.post721.dev0
 Summary: Yosys Open SYnthesis Suite
 Author-email: Catherine <whitequark@whitequark.org>
 License: ISC

{yowasp_yosys-0.40.0.0.post707.dist-info → yowasp_yosys-0.40.0.68.post721.dev0.dist-info}/RECORD

@@ -1,8 +1,8 @@
 yowasp_yosys/__init__.py,sha256=x--xPTzLWZNoX6H0B2E3a1HMZMk3di10gVnWVLJ92xc,1325
 yowasp_yosys/sby.py,sha256=5T0BrIqJ5vobWMd9nOEClXq0rlRxCXNPYycGGS0l7zc,18414
-yowasp_yosys/smtbmc.py,sha256=bGnVDnvEGCRWuNdHfsqwMdCNJ9GJqdeBuxehh8N9M64,73159
+yowasp_yosys/smtbmc.py,sha256=ZYbKxnxP3rGyGa_X6yiH3bevZ2YIUNqzeak4_VT9NWc,73594
 yowasp_yosys/witness.py,sha256=m3iV2Nydm0p4G79VRaaX3lGul-nGnuxeKnx20MCJgi0,17279
-yowasp_yosys/yosys.wasm,sha256=ayR3ZoYGvWnTafWIXzMBfP_KGkO829m-JP5CsAZRumA,21712677
+yowasp_yosys/yosys.wasm,sha256=lN4X0G0S8goHT836Q1fuOiLgeTDTJ-meCqwhlyFpg5I,21916673
 yowasp_yosys/share/abc9_map.v,sha256=uWDqMpBQTeeadH1BlHVwkCy2StKF892xbgBgMKLK5-w,923
 yowasp_yosys/share/abc9_model.v,sha256=IfMyEGOEUBdZyiVule0wMhrVYVYQpmSIcxygbgtHItI,653
 yowasp_yosys/share/abc9_unmap.v,sha256=w107Y3iJjMU6D_6_aYLf2NziXTnAhpa5_CFAwaYO1iU,638
@@ -102,8 +102,8 @@ yowasp_yosys/share/ice40/ff_map.v,sha256=0ikq-i1_UVT6xuFLMj2Zfilwu6wz8oibMdtPegZ
 yowasp_yosys/share/ice40/latches_map.v,sha256=V5NwBaIML68eOlhDaUJUs8W-ggRePjPsDtUn3mnSpao,258
 yowasp_yosys/share/ice40/spram.txt,sha256=dCRV0flfJunvnvKV0Q5Kq5NBrhh_PkZGXvUt675aiIk,153
 yowasp_yosys/share/ice40/spram_map.v,sha256=O8fRkVuH1dgAXEAtYJgh8wTHnZEK75fPAMBI-PgYVqs,475
-yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h,sha256=LS7KRLw0QeYBy4hVN-HXOlffO0haftiyO8H5jX7YRC8,70249
-yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h,sha256=RoCV7UivYQnLU2y5keBtGkSoKuiZ3onK4o7zFLItw3w,29990
+yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h,sha256=DsdKdMvjVtLhCR0tRm8DuzX0IEeX7C9s6Q-OOMjsQa0,72324
+yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h,sha256=3bFAy3nYtaH4MsLI9Kvf88K6BYOkML8plDMxmPtPdss,30008
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h,sha256=6zIxuXG7bXy5UWe7WuA_KQHiwV7VWvcsNecwOPAL_bU,6174
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h,sha256=F2N7FdVUFoOu089dZIBgIT2mmn22QAj0717d26oVPpc,8488
 yowasp_yosys/share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc,sha256=PaxuEg0ZK7anL1qsyjJuf-5nxn4GfMIegCPjyT5e-Sw,4549
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 yowasp_yosys/share/include/kernel/celledges.h,sha256=fF_sHJOpN_qQ1P0x8KKoJE9ulDMusfjkF0dBpTMs19E,2216
 yowasp_yosys/share/include/kernel/celltypes.h,sha256=eUTCXzeOBYZikLkfmvrdZmlrwqn1BEVLjYIlLW3UphU,18323
 yowasp_yosys/share/include/kernel/consteval.h,sha256=dHXfaHnD0v94entOfWlmo5u3QhVF8knnn4ETcHiL4PI,10913
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 yowasp_yosys/share/include/kernel/cost.h,sha256=4f29ZI-4GhsPrI73TNZ89KqtTt7fo48GlWs3U-WA-tQ,3104
 yowasp_yosys/share/include/kernel/ff.h,sha256=Rm9a6qsbXTPADi3TG794tzYXjOvRkewNMy8AXMA5vtE,7574
 yowasp_yosys/share/include/kernel/ffinit.h,sha256=2kcOTgBDxCsCongoGYFPgnFXZugY34WZBDCN2xIHv8M,3473
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 yowasp_yosys/share/python3/sby_cmdline.py,sha256=smwh_vUjRnclYGXMfFD4Bt9C1l3G0oBUPPvCWi_5-Lw,5074
 yowasp_yosys/share/python3/sby_core.py,sha256=gO6QmiGuYVUEIOZL6FpW8jOPqD2S6pIWTF-Svc5JQqE,60212
 yowasp_yosys/share/python3/sby_design.py,sha256=5IbfwvGBkGeMuv7BcCd9eokYv989EHvw3eT3T22xPSw,9351
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 yowasp_yosys/share/python3/sby_engine_aiger.py,sha256=wq4IipN00G3_gj0Kq4UhywV5uB3UhYH-E6Uoqry70Q8,9073
 yowasp_yosys/share/python3/sby_engine_btor.py,sha256=ulUhsJRm7UjMiMwb4Jk6aRQVI_RJN1B6iqQD7MMp8uw,11088
 yowasp_yosys/share/python3/sby_engine_smtbmc.py,sha256=OKwrPTqSgC2ms1rqTMe9Cb53sa_Cy9ImJ-RyBtAs6hs,11979
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 yowasp_yosys/share/python3/sby_mode_prove.py,sha256=igQAoaxEfO6SSXNm8PeIYV1qWLC9os96V1m7FHAJVKo,1941
 yowasp_yosys/share/python3/sby_sim.py,sha256=HWSLhMOv1RrNXVrmgsibBTf3lHUHUNaAhfnBF2Wx9Bc,4403
 yowasp_yosys/share/python3/sby_status.py,sha256=g__ivZ0bHmqrJLG_zx0LcFOe3E5O5yV34HhG9uvZo4Q,10946
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+yowasp_yosys/share/python3/smtio.py,sha256=ewCkiRyTqBRe8yEj-3BAlvwzSUfLA2UMjh_d4kug1n8,48779
 yowasp_yosys/share/python3/ywio.py,sha256=F3V-lAn7GNAlDh8oO3VtLJbQd3LwJZyrq3qjZVW_A_4,12442
 yowasp_yosys/share/quicklogic/common/cells_sim.v,sha256=XjVURrz_kgf2n32Mq9KKUXAbmKJsazqS87PiznC75Ew,366
 yowasp_yosys/share/quicklogic/pp3/abc9_map.v,sha256=wRzXyD70RDkif2ytEgvL2rmPU7mrNmISDB71YgfnHxw,771
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 yowasp_yosys/share/quicklogic/pp3/lut_map.v,sha256=BmijMS4EqVQPP2BPo2zgKStKPPhRLTf5kbcAtGKZEVs,928
 yowasp_yosys/share/quicklogic/qlf_k6n10f/TDP18K_FIFO.v,sha256=k1AVrwpOQ3vpxoWAbchRpmNbncYCYtVfDExz6VcmtBg,10404
 yowasp_yosys/share/quicklogic/qlf_k6n10f/arith_map.v,sha256=Ea7aX3l71nFxP1Az5NHtca-ZPnQmUmUvlWI-tVl4Bkk,2560
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 yowasp_yosys/share/quicklogic/qlf_k6n10f/brams_map.v,sha256=Iqj4w3Vna6W80liLUtDhAQKwciQNZWX3aFr9FDBU5o4,103558
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@@ -294,8 +294,8 @@ yowasp_yosys/share/xilinx/xc5v_dsp_map.v,sha256=I4lg0RQ54fBBba_7NNvUgwS4tQ1yLIsU
 yowasp_yosys/share/xilinx/xc6s_dsp_map.v,sha256=gTxHocB-Dn5G4BplWgri_tLhT6DIO2S0X-yu4iBKYyk,562
 yowasp_yosys/share/xilinx/xc7_dsp_map.v,sha256=zrzreQi7mElrAMtrayxtiO_Bw00S6zsjSjSVcjmJPH0,884
 yowasp_yosys/share/xilinx/xcu_dsp_map.v,sha256=gzCgl1emrHGcigVmU0nP0pW7dlhQ01SaWwXzHHcqt-o,882
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