yowasp-yosys 0.37.0.0.post648__py3-none-any.whl → 0.38.0.0.post669__py3-none-any.whl

yowasp_yosys/__init__.py

@@ -8,7 +8,7 @@ except (ImportError, AttributeError):
 
 
 def run_yosys(argv):
-    return yowasp_runtime.run_wasm(__package__, "yosys.wasm", resources=["share"], 
+    return yowasp_runtime.run_wasm(__package__, "yosys.wasm", resources=["share"],
         argv=["yowasp-yosys", *argv])
 
 
@@ -28,10 +28,6 @@ def _run_yosys_smtbmc_argv():
 def _run_yosys_witness_argv():
     prefix = importlib_resources.files(__package__)
     sys.path[0:0] = [str(prefix / "share" / "python3")]
-    ywio_py = prefix / "ywio.py"
-    with open(ywio_py) as f:
-        globals = {}
-        exec(compile(f.read(), ywio_py, "exec"), globals, globals)
     witness_py = prefix / "witness.py"
     with open(witness_py) as f:
         globals = {"__name__": "__main__"}

yowasp_yosys/share/gowin/brams.txt

@@ -1,13 +1,11 @@
 ram block $__GOWIN_SP_ {
 	abits 14;
 	widths 1 2 4 9 18 36 per_port;
-	byte 9;
 	cost 128;
 	init no_undef;
 	port srsw "A" {
 		clock posedge;
 		clken;
-		wrbe_separate;
 		option "RESET_MODE" "SYNC" {
 			rdsrst zero ungated;
 		}
@@ -30,13 +28,11 @@ ram block $__GOWIN_SP_ {
 ram block $__GOWIN_DP_ {
 	abits 14;
 	widths 1 2 4 9 18 per_port;
-	byte 9;
 	cost 128;
 	init no_undef;
 	port srsw "A" "B" {
 		clock posedge;
 		clken;
-		wrbe_separate;
 		option "RESET_MODE" "SYNC" {
 			rdsrst zero ungated;
 		}
@@ -59,7 +55,6 @@ ram block $__GOWIN_DP_ {
 ram block $__GOWIN_SDP_ {
 	abits 14;
 	widths 1 2 4 9 18 36 per_port;
-	byte 9;
 	cost 128;
 	init no_undef;
 	port sr "R" {
@@ -76,6 +71,5 @@ ram block $__GOWIN_SDP_ {
 	port sw "W" {
 		clock posedge;
 		clken;
-		wrbe_separate;
 	}
 }

yowasp_yosys/share/gowin/brams_map.v

@@ -14,8 +14,7 @@
 `define x8_width(width) (width / 9 * 8 + width % 9)
 `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}
 `define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}
-`define wre(width, wr_en, wr_be) (width < 18 ? wr_en | wr_be[0] : wr_en)
-`define addrbe(width, addr, wr_be) (width < 18 ? addr : {addr[13:4], wr_be})
+`define addrbe_always(width, addr) (width < 18 ? addr :  width == 18 ? {addr[13:4], 4'b0011} : {addr[13:5], 5'b01111})
 
 
 `define INIT(func) \
@@ -90,7 +89,6 @@ parameter INIT = 0;
 parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_A_WIDTH = 36;
-parameter PORT_A_WR_BE_WIDTH = 4;
 parameter PORT_A_OPTION_WRITE_MODE = 0;
 
 input PORT_A_CLK;
@@ -99,15 +97,13 @@ input PORT_A_WR_EN;
 input PORT_A_RD_SRST;
 input PORT_A_RD_ARST;
 input [13:0] PORT_A_ADDR;
-input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
 `DEF_FUNCS
 
 wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
-wire WRE = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);
-wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
+wire [13:0] AD = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
 
 generate
 
@@ -129,9 +125,9 @@ if (PORT_A_WIDTH < 9) begin
 		.BLKSEL(3'b000),
 		.CLK(PORT_A_CLK),
 		.CE(PORT_A_CLK_EN),
-		.WRE(WRE),
+		.WRE(PORT_A_WR_EN),
 		.RESET(RST),
-		.OCE(1'b0),
+		.OCE(1'b1),
 		.AD(AD),
 		.DI(DI),
 		.DO(DO),
@@ -155,9 +151,9 @@ end else begin
 		.BLKSEL(3'b000),
 		.CLK(PORT_A_CLK),
 		.CE(PORT_A_CLK_EN),
-		.WRE(WRE),
+		.WRE(PORT_A_WR_EN),
 		.RESET(RST),
-		.OCE(1'b0),
+		.OCE(1'b1),
 		.AD(AD),
 		.DI(DI),
 		.DO(DO),
@@ -176,11 +172,9 @@ parameter INIT = 0;
 parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_A_WIDTH = 18;
-parameter PORT_A_WR_BE_WIDTH = 2;
 parameter PORT_A_OPTION_WRITE_MODE = 0;
 
 parameter PORT_B_WIDTH = 18;
-parameter PORT_B_WR_BE_WIDTH = 2;
 parameter PORT_B_OPTION_WRITE_MODE = 0;
 
 input PORT_A_CLK;
@@ -189,7 +183,6 @@ input PORT_A_WR_EN;
 input PORT_A_RD_SRST;
 input PORT_A_RD_ARST;
 input [13:0] PORT_A_ADDR;
-input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
 
@@ -199,7 +192,6 @@ input PORT_B_WR_EN;
 input PORT_B_RD_SRST;
 input PORT_B_RD_ARST;
 input [13:0] PORT_B_ADDR;
-input [PORT_A_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
 input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;
 output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
 
@@ -207,10 +199,8 @@ output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
 
 wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
 wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
-wire WREA = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);
-wire WREB = `wre(PORT_B_WIDTH, PORT_B_WR_EN, PORT_B_WR_BE);
-wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
-wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
+wire [13:0] ADA = `addrbe_always(PORT_A_WIDTH, PORT_A_ADDR);
+wire [13:0] ADB = `addrbe_always(PORT_B_WIDTH, PORT_B_ADDR);
 
 generate
 
@@ -224,7 +214,7 @@ if (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin
 	assign PORT_A_RD_DATA = `x8_rd_data(DOA);
 	assign PORT_B_RD_DATA = `x8_rd_data(DOB);
 
-	DP #(
+	DPB #(
 		`INIT(init_slice_x8)
 		.READ_MODE0(1'b0),
 		.READ_MODE1(1'b0),
@@ -232,25 +222,27 @@ if (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin
 		.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
 		.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),
 		.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),
-		.BLK_SEL(3'b000),
+		.BLK_SEL_0(3'b000),
+		.BLK_SEL_1(3'b000),
 		.RESET_MODE(OPTION_RESET_MODE),
 	) _TECHMAP_REPLACE_ (
-		.BLKSEL(3'b000),
+		.BLKSELA(3'b000),
+		.BLKSELB(3'b000),
 
 		.CLKA(PORT_A_CLK),
 		.CEA(PORT_A_CLK_EN),
-		.WREA(WREA),
+		.WREA(PORT_A_WR_EN),
 		.RESETA(RSTA),
-		.OCEA(1'b0),
+		.OCEA(1'b1),
 		.ADA(ADA),
 		.DIA(DIA),
 		.DOA(DOA),
 
 		.CLKB(PORT_B_CLK),
 		.CEB(PORT_B_CLK_EN),
-		.WREB(WREB),
+		.WREB(PORT_B_WR_EN),
 		.RESETB(RSTB),
-		.OCEB(1'b0),
+		.OCEB(1'b1),
 		.ADB(ADB),
 		.DIB(DIB),
 		.DOB(DOB),
@@ -266,7 +258,7 @@ end else begin
 	assign PORT_A_RD_DATA = DOA;
 	assign PORT_B_RD_DATA = DOB;
 
-	DPX9 #(
+	DPX9B #(
 		`INIT(init_slice_x9)
 		.READ_MODE0(1'b0),
 		.READ_MODE1(1'b0),
@@ -274,25 +266,27 @@ end else begin
 		.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
 		.BIT_WIDTH_0(PORT_A_WIDTH),
 		.BIT_WIDTH_1(PORT_B_WIDTH),
-		.BLK_SEL(3'b000),
+		.BLK_SEL_0(3'b000),
+		.BLK_SEL_1(3'b000),
 		.RESET_MODE(OPTION_RESET_MODE),
 	) _TECHMAP_REPLACE_ (
-		.BLKSEL(3'b000),
+		.BLKSELA(3'b000),
+		.BLKSELB(3'b000),
 
 		.CLKA(PORT_A_CLK),
 		.CEA(PORT_A_CLK_EN),
-		.WREA(WREA),
+		.WREA(PORT_A_WR_EN),
 		.RESETA(RSTA),
-		.OCEA(1'b0),
+		.OCEA(1'b1),
 		.ADA(ADA),
 		.DIA(DIA),
 		.DOA(DOA),
 
 		.CLKB(PORT_B_CLK),
 		.CEB(PORT_B_CLK_EN),
-		.WREB(WREB),
+		.WREB(PORT_B_WR_EN),
 		.RESETB(RSTB),
-		.OCEB(1'b0),
+		.OCEB(1'b1),
 		.ADB(ADB),
 		.DIB(DIB),
 		.DOB(DOB),
@@ -311,9 +305,7 @@ parameter INIT = 0;
 parameter OPTION_RESET_MODE = "SYNC";
 
 parameter PORT_R_WIDTH = 18;
-
 parameter PORT_W_WIDTH = 18;
-parameter PORT_W_WR_BE_WIDTH = 2;
 
 input PORT_R_CLK;
 input PORT_R_CLK_EN;
@@ -326,14 +318,13 @@ input PORT_W_CLK;
 input PORT_W_CLK_EN;
 input PORT_W_WR_EN;
 input [13:0] PORT_W_ADDR;
-input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;
 input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
 
 `DEF_FUNCS
 
 wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
-wire WRE = `wre(PORT_W_WIDTH, PORT_W_WR_EN, PORT_W_WR_BE);
-wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE);
+wire [13:0] ADW = `addrbe_always(PORT_W_WIDTH, PORT_W_ADDR);
+wire WRE = PORT_W_CLK_EN & PORT_W_WR_EN;
 
 generate
 
@@ -344,28 +335,28 @@ if (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin
 
 	assign PORT_R_RD_DATA = `x8_rd_data(DO);
 
-	SDP #(
+	SDPB #(
 		`INIT(init_slice_x8)
 		.READ_MODE(1'b0),
 		.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),
 		.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),
-		.BLK_SEL(3'b000),
+		.BLK_SEL_0(3'b000),
+		.BLK_SEL_1(3'b000),
 		.RESET_MODE(OPTION_RESET_MODE),
 	) _TECHMAP_REPLACE_ (
-		.BLKSEL(3'b000),
+		.BLKSELA(3'b000),
+		.BLKSELB(3'b000),
 
 		.CLKA(PORT_W_CLK),
-		.CEA(PORT_W_CLK_EN),
-		.WREA(WRE),
+		.CEA(WRE),
 		.RESETA(1'b0),
 		.ADA(ADW),
 		.DI(DI),
 
 		.CLKB(PORT_R_CLK),
 		.CEB(PORT_R_CLK_EN),
-		.WREB(1'b0),
 		.RESETB(RST),
-		.OCE(1'b0),
+		.OCE(1'b1),
 		.ADB(PORT_R_ADDR),
 		.DO(DO),
 	);
@@ -377,28 +368,28 @@ end else begin
 
 	assign PORT_R_RD_DATA = DO;
 
-	SDPX9 #(
+	SDPX9B #(
 		`INIT(init_slice_x9)
 		.READ_MODE(1'b0),
 		.BIT_WIDTH_0(PORT_W_WIDTH),
 		.BIT_WIDTH_1(PORT_R_WIDTH),
-		.BLK_SEL(3'b000),
+		.BLK_SEL_0(3'b000),
+		.BLK_SEL_1(3'b000),
 		.RESET_MODE(OPTION_RESET_MODE),
 	) _TECHMAP_REPLACE_ (
-		.BLKSEL(3'b000),
+		.BLKSELA(3'b000),
+		.BLKSELB(3'b000),
 
 		.CLKA(PORT_W_CLK),
-		.CEA(PORT_W_CLK_EN),
-		.WREA(WRE),
+		.CEA(WRE),
 		.RESETA(1'b0),
 		.ADA(ADW),
 		.DI(DI),
 
 		.CLKB(PORT_R_CLK),
 		.CEB(PORT_R_CLK_EN),
-		.WREB(1'b0),
 		.RESETB(RST),
-		.OCE(1'b0),
+		.OCE(1'b1),
 		.ADB(PORT_R_ADDR),
 		.DO(DO),
 	);