xmos-ai-tools 1.1.2.dev216__py3-none-macosx_11_0_arm64.whl → 1.1.2.dev236__py3-none-macosx_11_0_arm64.whl

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/kernel_util.h

@@ -28,21 +28,26 @@ limitations under the License.
 namespace tflite {
 namespace micro {
 
-TfLiteRegistration_V1 RegisterOp(
+TFLMRegistration RegisterOp(
     void* (*init)(TfLiteContext* context, const char* buffer, size_t length),
     TfLiteStatus (*prepare)(TfLiteContext* context, TfLiteNode* node),
     TfLiteStatus (*invoke)(TfLiteContext* context, TfLiteNode* node),
-    void (*free)(TfLiteContext* context, void* buffer) = nullptr);
+    void (*free)(TfLiteContext* context, void* buffer) = nullptr,
+    void (*reset)(TfLiteContext* context, void* buffer) = nullptr);
+
+TFLMInferenceRegistration RegisterOp(
+    TfLiteStatus (*invoke)(TfLiteContext* context, TfLiteNode* node),
+    void (*reset)(TfLiteContext* context, void* buffer) = nullptr);
 
 // Prints out n bytes in a int8_t buffer as hex
 void PrintNBytes(const int8_t* tensor_data, int n_bytes,
                  const char* prefix = nullptr);
 
-// Prints out the the n bytes in a TfLiteEvalTensor as hex
+// Prints out the n bytes in a TfLiteEvalTensor as hex
 void PrintNBytes(const TfLiteEvalTensor* tensor, int n_bytes,
                  const char* prefix = nullptr);
 
-// Prints out the the n bytes in a TfLiteTensor as hex
+// Prints out n bytes in a TfLiteTensor as hex
 void PrintNBytes(const TfLiteTensor* tensor, int n_bytes,
                  const char* prefix = nullptr);
 

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/micro_ops.h

@@ -15,6 +15,8 @@ limitations under the License.
 #ifndef TENSORFLOW_LITE_MICRO_KERNELS_MICRO_OPS_H_
 #define TENSORFLOW_LITE_MICRO_KERNELS_MICRO_OPS_H_
 
+#include "signal/micro/kernels/irfft.h"
+#include "signal/micro/kernels/rfft.h"
 #include "tensorflow/lite/c/common.h"
 
 // Forward declaration of all micro op kernel registration methods. These
@@ -31,109 +33,126 @@ namespace tflite {
 // (https://abseil.io/tips/130). Any new ops (or cleanup of existing ops should
 // have their Register function declarations in the tflite namespace.
 
-TfLiteRegistration_V1 Register_ABS();
-TfLiteRegistration_V1 Register_ADD();
-TfLiteRegistration_V1 Register_ADD_N();
-TfLiteRegistration_V1 Register_ARG_MAX();
-TfLiteRegistration_V1 Register_ARG_MIN();
-TfLiteRegistration_V1 Register_ASSIGN_VARIABLE();
-TfLiteRegistration_V1 Register_AVERAGE_POOL_2D();
-TfLiteRegistration_V1 Register_BATCH_TO_SPACE_ND();
-TfLiteRegistration_V1 Register_BROADCAST_ARGS();
-TfLiteRegistration_V1 Register_BROADCAST_TO();
-TfLiteRegistration_V1 Register_CALL_ONCE();
-TfLiteRegistration_V1 Register_CAST();
-TfLiteRegistration_V1 Register_CEIL();
+TFLMRegistration Register_ABS();
+TFLMRegistration Register_ADD();
+TFLMRegistration Register_ADD_N();
+TFLMRegistration Register_ARG_MAX();
+TFLMRegistration Register_ARG_MIN();
+TFLMRegistration Register_ASSIGN_VARIABLE();
+TFLMRegistration Register_AVERAGE_POOL_2D();
+TFLMRegistration Register_BATCH_MATMUL();
+TFLMRegistration Register_BATCH_TO_SPACE_ND();
+TFLMRegistration Register_BROADCAST_ARGS();
+TFLMRegistration Register_BROADCAST_TO();
+TFLMRegistration Register_CALL_ONCE();
+TFLMRegistration Register_CAST();
+TFLMRegistration Register_CEIL();
 // TODO(b/160234179): Change custom OPs to also return by value.
-TfLiteRegistration_V1* Register_CIRCULAR_BUFFER();
-TfLiteRegistration_V1 Register_CONCATENATION();
-TfLiteRegistration_V1 Register_CONV_2D();
-TfLiteRegistration_V1 Register_COS();
-TfLiteRegistration_V1 Register_CUMSUM();
-TfLiteRegistration_V1 Register_DEPTH_TO_SPACE();
-TfLiteRegistration_V1 Register_DEPTHWISE_CONV_2D();
-TfLiteRegistration_V1 Register_DEQUANTIZE();
-TfLiteRegistration_V1 Register_DIV();
-TfLiteRegistration_V1 Register_ELU();
-TfLiteRegistration_V1 Register_EQUAL();
-TfLiteRegistration_V1* Register_ETHOSU();
-TfLiteRegistration_V1 Register_EXP();
-TfLiteRegistration_V1 Register_EXPAND_DIMS();
-TfLiteRegistration_V1 Register_FILL();
-TfLiteRegistration_V1 Register_FLOOR();
-TfLiteRegistration_V1 Register_FLOOR_DIV();
-TfLiteRegistration_V1 Register_FLOOR_MOD();
-TfLiteRegistration_V1 Register_FULLY_CONNECTED();
-TfLiteRegistration_V1 Register_GATHER();
-TfLiteRegistration_V1 Register_GATHER_ND();
-TfLiteRegistration_V1 Register_GREATER();
-TfLiteRegistration_V1 Register_GREATER_EQUAL();
-TfLiteRegistration_V1 Register_HARD_SWISH();
-TfLiteRegistration_V1 Register_IF();
-TfLiteRegistration_V1 Register_L2_NORMALIZATION();
-TfLiteRegistration_V1 Register_L2_POOL_2D();
-TfLiteRegistration_V1 Register_LEAKY_RELU();
-TfLiteRegistration_V1 Register_LESS();
-TfLiteRegistration_V1 Register_LESS_EQUAL();
-TfLiteRegistration_V1 Register_LOG();
-TfLiteRegistration_V1 Register_LOG_SOFTMAX();
-TfLiteRegistration_V1 Register_LOGICAL_AND();
-TfLiteRegistration_V1 Register_LOGICAL_NOT();
-TfLiteRegistration_V1 Register_LOGICAL_OR();
-TfLiteRegistration_V1 Register_LOGISTIC();
-TfLiteRegistration_V1 Register_MAX_POOL_2D();
-TfLiteRegistration_V1 Register_MAXIMUM();
-TfLiteRegistration_V1 Register_MEAN();
-TfLiteRegistration_V1 Register_MINIMUM();
-TfLiteRegistration_V1 Register_MIRROR_PAD();
-TfLiteRegistration_V1 Register_MUL();
-TfLiteRegistration_V1 Register_NEG();
-TfLiteRegistration_V1 Register_NOT_EQUAL();
-TfLiteRegistration_V1 Register_PACK();
-TfLiteRegistration_V1 Register_PAD();
-TfLiteRegistration_V1 Register_PADV2();
-TfLiteRegistration_V1 Register_PRELU();
-TfLiteRegistration_V1 Register_QUANTIZE();
-TfLiteRegistration_V1 Register_READ_VARIABLE();
-TfLiteRegistration_V1 Register_REDUCE_MAX();
-TfLiteRegistration_V1 Register_RELU();
-TfLiteRegistration_V1 Register_RELU6();
-TfLiteRegistration_V1 Register_RESIZE_BILINEAR();
-TfLiteRegistration_V1 Register_RESIZE_NEAREST_NEIGHBOR();
-TfLiteRegistration_V1 Register_RSQRT();
-TfLiteRegistration_V1 Register_SELECT_V2();
-TfLiteRegistration_V1 Register_SHAPE();
-TfLiteRegistration_V1 Register_SIN();
-TfLiteRegistration_V1 Register_SLICE();
-TfLiteRegistration_V1 Register_SOFTMAX();
-TfLiteRegistration_V1 Register_SPACE_TO_BATCH_ND();
-TfLiteRegistration_V1 Register_SPACE_TO_DEPTH();
-TfLiteRegistration_V1 Register_SPLIT();
-TfLiteRegistration_V1 Register_SPLIT_V();
-TfLiteRegistration_V1 Register_SQRT();
-TfLiteRegistration_V1 Register_SQUARE();
-TfLiteRegistration_V1 Register_SQUARED_DIFFERENCE();
-TfLiteRegistration_V1 Register_SQUEEZE();
-TfLiteRegistration_V1 Register_STRIDED_SLICE();
-TfLiteRegistration_V1 Register_SUB();
-TfLiteRegistration_V1 Register_SUM();
-TfLiteRegistration_V1 Register_SVDF();
-TfLiteRegistration_V1 Register_TANH();
-TfLiteRegistration_V1 Register_TRANSPOSE();
-TfLiteRegistration_V1 Register_TRANSPOSE_CONV();
+TFLMRegistration* Register_CIRCULAR_BUFFER();
+TFLMRegistration Register_CONCATENATION();
+TFLMRegistration Register_CONV_2D();
+TFLMRegistration Register_COS();
+TFLMRegistration Register_CUMSUM();
+TFLMRegistration Register_DEPTH_TO_SPACE();
+TFLMRegistration Register_DEPTHWISE_CONV_2D();
+TFLMRegistration Register_DEQUANTIZE();
+TFLMRegistration Register_DIV();
+TFLMRegistration Register_ELU();
+TFLMRegistration Register_EMBEDDING_LOOKUP();
+TFLMRegistration Register_EQUAL();
+TFLMRegistration* Register_ETHOSU();
+TFLMRegistration Register_EXP();
+TFLMRegistration Register_EXPAND_DIMS();
+TFLMRegistration Register_FILL();
+TFLMRegistration Register_FLOOR();
+TFLMRegistration Register_FLOOR_DIV();
+TFLMRegistration Register_FLOOR_MOD();
+TFLMRegistration Register_FULLY_CONNECTED();
+TFLMRegistration Register_GATHER();
+TFLMRegistration Register_GATHER_ND();
+TFLMRegistration Register_GREATER();
+TFLMRegistration Register_GREATER_EQUAL();
+TFLMRegistration Register_HARD_SWISH();
+TFLMRegistration Register_IF();
+TFLMRegistration Register_L2_NORMALIZATION();
+TFLMRegistration Register_L2_POOL_2D();
+TFLMRegistration Register_LEAKY_RELU();
+TFLMRegistration Register_LESS();
+TFLMRegistration Register_LESS_EQUAL();
+TFLMRegistration Register_LOG();
+TFLMRegistration Register_LOG_SOFTMAX();
+TFLMRegistration Register_LOGICAL_AND();
+TFLMRegistration Register_LOGICAL_NOT();
+TFLMRegistration Register_LOGICAL_OR();
+TFLMRegistration Register_LOGISTIC();
+TFLMRegistration Register_MAX_POOL_2D();
+TFLMRegistration Register_MAXIMUM();
+TFLMRegistration Register_MEAN();
+TFLMRegistration Register_MINIMUM();
+TFLMRegistration Register_MIRROR_PAD();
+TFLMRegistration Register_MUL();
+TFLMRegistration Register_NEG();
+TFLMRegistration Register_NOT_EQUAL();
+TFLMRegistration Register_PACK();
+TFLMRegistration Register_PAD();
+TFLMRegistration Register_PADV2();
+TFLMRegistration Register_PRELU();
+TFLMRegistration Register_QUANTIZE();
+TFLMRegistration Register_READ_VARIABLE();
+TFLMRegistration Register_REDUCE_MAX();
+TFLMRegistration Register_RELU();
+TFLMRegistration Register_RELU6();
+TFLMRegistration Register_RESHAPE();
+TFLMRegistration Register_RESIZE_BILINEAR();
+TFLMRegistration Register_RESIZE_NEAREST_NEIGHBOR();
+TFLMRegistration Register_ROUND();
+TFLMRegistration Register_RSQRT();
+TFLMRegistration Register_SELECT_V2();
+TFLMRegistration Register_SHAPE();
+TFLMRegistration Register_SIN();
+TFLMRegistration Register_SLICE();
+TFLMRegistration Register_SOFTMAX();
+TFLMRegistration Register_SPACE_TO_BATCH_ND();
+TFLMRegistration Register_SPACE_TO_DEPTH();
+TFLMRegistration Register_SPLIT();
+TFLMRegistration Register_SPLIT_V();
+TFLMRegistration Register_SQRT();
+TFLMRegistration Register_SQUARE();
+TFLMRegistration Register_SQUARED_DIFFERENCE();
+TFLMRegistration Register_SQUEEZE();
+TFLMRegistration Register_STRIDED_SLICE();
+TFLMRegistration Register_SUB();
+TFLMRegistration Register_SUM();
+TFLMRegistration Register_SVDF();
+TFLMRegistration Register_TANH();
+TFLMRegistration Register_TRANSPOSE();
+TFLMRegistration Register_TRANSPOSE_CONV();
 // TODO(b/230666079): resolve conflict with xtensa implementation
-TfLiteRegistration_V1 Register_UNIDIRECTIONAL_SEQUENCE_LSTM();
-TfLiteRegistration_V1 Register_UNPACK();
-TfLiteRegistration_V1 Register_VAR_HANDLE();
-TfLiteRegistration_V1 Register_WHILE();
-TfLiteRegistration_V1 Register_ZEROS_LIKE();
+TFLMRegistration Register_UNIDIRECTIONAL_SEQUENCE_LSTM();
+TFLMRegistration Register_UNPACK();
+TFLMRegistration Register_VAR_HANDLE();
+TFLMRegistration Register_WHILE();
+TFLMRegistration Register_ZEROS_LIKE();
+
+// TODO(b/295174388): Add the rest of inference only registration functions.
+TFLMInferenceRegistration RegisterInference_FULLY_CONNECTED();
+
+// TODO(b/160234179): Change custom OPs to also return by value.
+namespace tflm_signal {
+TFLMRegistration* Register_DELAY();
+TFLMRegistration* Register_FFT_AUTO_SCALE();
+TFLMRegistration* Register_FILTER_BANK();
+TFLMRegistration* Register_FILTER_BANK_LOG();
+TFLMRegistration* Register_FILTER_BANK_SPECTRAL_SUBTRACTION();
+TFLMRegistration* Register_FILTER_BANK_SQUARE_ROOT();
+TFLMRegistration* Register_ENERGY();
+TFLMRegistration* Register_FRAMER();
+TFLMRegistration* Register_OVERLAP_ADD();
+TFLMRegistration* Register_PCAN();
+TFLMRegistration* Register_STACKER();
+TFLMRegistration* Register_WINDOW();
+}  // namespace tflm_signal
 
-namespace ops {
-namespace micro {
-TfLiteRegistration_V1 Register_RESHAPE();
-TfLiteRegistration_V1 Register_ROUND();
-}  // namespace micro
-}  // namespace ops
 }  // namespace tflite
 
 #endif  // TENSORFLOW_LITE_MICRO_KERNELS_MICRO_OPS_H_

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/mul.h

@@ -19,7 +19,7 @@ limitations under the License.
 #include <cstdint>
 
 #include "tensorflow/lite/c/builtin_op_data.h"
-#include "tensorflow/lite/c/common.h"
+#include "tensorflow/lite/micro/micro_common.h"
 
 namespace tflite {
 
@@ -61,13 +61,13 @@ void EvalMulFloatReference(TfLiteContext* context, TfLiteNode* node,
                            TfLiteEvalTensor* output);
 
 // Generic must define registration function.
-TfLiteRegistration_V1 Register_MUL();
+TFLMRegistration Register_MUL();
 
 #if defined(CMSIS_NN)
-TfLiteRegistration_V1 Register_MUL_INT8();
+TFLMRegistration Register_MUL_INT8();
 #else
 // Fallback registration
-inline TfLiteRegistration_V1 Register_MUL_INT8() { return Register_MUL(); }
+inline TFLMRegistration Register_MUL_INT8() { return Register_MUL(); }
 #endif
 }  // namespace tflite
 

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/pooling.h

@@ -113,27 +113,27 @@ void MaxPoolingEvalQuantized(TfLiteContext* context, TfLiteNode* node,
 }
 
 #if defined(CMSIS_NN) || defined(XTENSA)
-TfLiteRegistration_V1 Register_AVERAGE_POOL_2D_INT8();
+TFLMRegistration Register_AVERAGE_POOL_2D_INT8();
 
-TfLiteRegistration_V1 Register_MAX_POOL_2D_INT8();
+TFLMRegistration Register_MAX_POOL_2D_INT8();
 
-TfLiteRegistration_V1 Register_AVERAGE_POOL_2D_INT16();
+TFLMRegistration Register_AVERAGE_POOL_2D_INT16();
 
-TfLiteRegistration_V1 Register_MAX_POOL_2D_INT16();
+TFLMRegistration Register_MAX_POOL_2D_INT16();
 #else
-inline TfLiteRegistration_V1 Register_AVERAGE_POOL_2D_INT8() {
+inline TFLMRegistration Register_AVERAGE_POOL_2D_INT8() {
   return tflite::Register_AVERAGE_POOL_2D();
 }
 
-inline TfLiteRegistration_V1 Register_MAX_POOL_2D_INT8() {
+inline TFLMRegistration Register_MAX_POOL_2D_INT8() {
   return tflite::Register_MAX_POOL_2D();
 }
 
-inline TfLiteRegistration_V1 Register_AVERAGE_POOL_2D_INT16() {
+inline TFLMRegistration Register_AVERAGE_POOL_2D_INT16() {
   return tflite::Register_AVERAGE_POOL_2D();
 }
 
-inline TfLiteRegistration_V1 Register_MAX_POOL_2D_INT16() {
+inline TFLMRegistration Register_MAX_POOL_2D_INT16() {
   return tflite::Register_MAX_POOL_2D();
 }
 #endif

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/reduce.h

@@ -19,8 +19,8 @@ limitations under the License.
 #include <cstdint>
 
 #include "tensorflow/lite/c/builtin_op_data.h"
-#include "tensorflow/lite/c/common.h"
 #include "tensorflow/lite/kernels/internal/types.h"
+#include "tensorflow/lite/micro/micro_common.h"
 
 namespace tflite {
 
@@ -56,9 +56,9 @@ TfLiteStatus EvalSumHelper(TfLiteContext* context, TfLiteNode* node,
 void ReduceResolveAxis(const int* axis_data, int axis_count,
                        MeanParams* op_params);
 
-TfLiteRegistration_V1 Register_MEAN();
-TfLiteRegistration_V1 Register_REDUCE_MAX();
-TfLiteRegistration_V1 Register_SUM();
+TFLMRegistration Register_MEAN();
+TFLMRegistration Register_REDUCE_MAX();
+TFLMRegistration Register_SUM();
 
 }  // namespace tflite
 

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/reshape.h

@@ -0,0 +1,26 @@
+/* Copyright 2023 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#include "tensorflow/lite/c/builtin_op_data.h"
+#include "tensorflow/lite/c/common.h"
+
+namespace tflite {
+
+constexpr int kReshapeInputTensor = 0;
+constexpr int kReshapeOutputTensor = 0;
+
+TfLiteStatus PrepareReshapeReference(TfLiteContext* context, TfLiteNode* node);
+
+}  // namespace tflite

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/softmax.h

@@ -16,8 +16,8 @@ limitations under the License.
 #define TENSORFLOW_LITE_MICRO_KERNELS_SOFTMAX_H_
 
 #include "tensorflow/lite/c/builtin_op_data.h"
-#include "tensorflow/lite/c/common.h"
 #include "tensorflow/lite/kernels/internal/types.h"
+#include "tensorflow/lite/micro/micro_common.h"
 
 namespace tflite {
 
@@ -32,38 +32,34 @@ TfLiteStatus CalculateSoftmaxParams(TfLiteContext* context,
 
 TfLiteStatus SoftmaxPrepare(TfLiteContext* context, TfLiteNode* node);
 
-// This is the most generic TfLiteRegistration_V1. The actual supported types
+// This is the most generic TFLMRegistration. The actual supported types
 // may still be target dependent. The only requirement is that every
 // implementation (reference or optimized) must define this function.
-TfLiteRegistration_V1 Register_SOFTMAX();
+TFLMRegistration Register_SOFTMAX();
 
 #if defined(XTENSA) || defined(CMSIS_NN)
-// Returns a TfLiteRegistration_V1 struct for kernel variant that only supports
+// Returns a TFLMRegistration struct for kernel variant that only supports
 // int8 input and int16 output.
-TfLiteRegistration_V1 Register_SOFTMAX_INT8_INT16();
+TFLMRegistration Register_SOFTMAX_INT8_INT16();
 #else
-inline TfLiteRegistration_V1 Register_SOFTMAX_INT8_INT16() {
+inline TFLMRegistration Register_SOFTMAX_INT8_INT16() {
   return Register_SOFTMAX();
 }
 #endif
 
 #if defined(CMSIS_NN)
-// Returns a TfLiteRegistration_V1 struct for kernel variant that only supports
+// Returns a TFLMRegistration struct for kernel variant that only supports
 // int8 input/output and uses the latency optimized implementations.
-TfLiteRegistration_V1 Register_SOFTMAX_INT8();
+TFLMRegistration Register_SOFTMAX_INT8();
 
-// Returns a TfLiteRegistration_V1 struct for kernel variant that only supports
+// Returns a TFLMRegistration struct for kernel variant that only supports
 // int16 input/output and uses the latency optimized implementations.
-TfLiteRegistration_V1 Register_SOFTMAX_INT16();
+TFLMRegistration Register_SOFTMAX_INT16();
 
 #else
-inline TfLiteRegistration_V1 Register_SOFTMAX_INT8() {
-  return Register_SOFTMAX();
-}
+inline TFLMRegistration Register_SOFTMAX_INT8() { return Register_SOFTMAX(); }
 
-inline TfLiteRegistration_V1 Register_SOFTMAX_INT16() {
-  return Register_SOFTMAX();
-}
+inline TFLMRegistration Register_SOFTMAX_INT16() { return Register_SOFTMAX(); }
 #endif
 
 }  // namespace tflite

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/strided_slice.h

@@ -0,0 +1,40 @@
+/* Copyright 2023 The TensorFlow Authors. All Rights Reserved.
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
+==============================================================================*/
+
+#ifndef TENSORFLOW_LITE_MICRO_KERNELS_STRIDED_SLICE_H_
+#define TENSORFLOW_LITE_MICRO_KERNELS_STRIDED_SLICE_H_
+
+#include <cstdint>
+
+#include "tensorflow/lite/c/builtin_op_data.h"
+#include "tensorflow/lite/c/common.h"
+#include "tensorflow/lite/micro/micro_common.h"
+
+namespace tflite {
+
+constexpr int kStridedSliceInputTensor = 0;
+constexpr int kStridedSliceBeginTensor = 1;
+constexpr int kStridedSliceEndTensor = 2;
+constexpr int kStridedSliceStridesTensor = 3;
+constexpr int kStridedSliceOutputTensor = 0;
+
+void* StridedSliceInit(TfLiteContext* context, const char* buffer,
+                       size_t length);
+
+TfLiteStatus StridedSlicePrepare(TfLiteContext* context, TfLiteNode* node);
+
+}  // namespace tflite
+
+#endif  // TENSORFLOW_LITE_MICRO_KERNELS_STRIDED_SLICE_H_

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/svdf.h

@@ -1,4 +1,4 @@
-/* Copyright 2022 The TensorFlow Authors. All Rights Reserved.
+/* Copyright 2023 The TensorFlow Authors. All Rights Reserved.
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
@@ -16,7 +16,7 @@ limitations under the License.
 #define TENSORFLOW_LITE_MICRO_KERNELS_SVDF_H_
 
 #include "tensorflow/lite/c/builtin_op_data.h"
-#include "tensorflow/lite/c/common.h"
+#include "tensorflow/lite/micro/micro_common.h"
 
 namespace tflite {
 
@@ -77,13 +77,14 @@ void EvalFloatSvdfReference(
 
 TfLiteStatus PrepareSvdf(TfLiteContext* context, TfLiteNode* node);
 
-// This is the most generic TfLiteRegistration_V1. The actual supported types
+// This is the most generic TFLMRegistration. The actual supported types
 // may still be target dependent. The only requirement is that every
 // implementation (reference or optimized) must define this function.
-TfLiteRegistration_V1 Register_SVDF();
+TFLMRegistration Register_SVDF();
 
-#if defined(HEXAGON) || defined(CMSIS_NN)
-TfLiteRegistration_V1 Register_SVDF_INT8();
+#if defined(HEXAGON) || defined(CMSIS_NN) || defined(XTENSA)
+
+TFLMRegistration Register_SVDF_INT8();
 
 #else
 // Note that while this block gets used for both reference and optimized kernels
@@ -91,7 +92,7 @@ TfLiteRegistration_V1 Register_SVDF_INT8();
 // define fallback implementation that allow reference kernels to still be used
 // from applications that call a more specific kernel variant.
 
-inline TfLiteRegistration_V1 Register_SVDF_INT8() { return Register_SVDF(); }
+inline TFLMRegistration Register_SVDF_INT8() { return Register_SVDF(); }
 
 #endif
 }  // namespace tflite

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/unidirectional_sequence_lstm.h

@@ -24,20 +24,20 @@ limitations under the License.
 
 namespace tflite {
 
-// This is the most generic TfLiteRegistration_V1. The actual supported types
+// This is the most generic TFLMRegistration. The actual supported types
 // may still be target dependent. The only requirement is that every
 // implementation (reference or optimized) must define this function.
 // TODO(b/230666079): resolve conflict with xtensa implementation
-TfLiteRegistration_V1 Register_UNIDIRECTIONAL_SEQUENCE_LSTM();
+TFLMRegistration Register_UNIDIRECTIONAL_SEQUENCE_LSTM();
 
 #if defined(CMSIS_NN)
-// Returns a TfLiteRegistration_V1 struct for kernel variant that only supports
+// Returns a TFLMRegistration struct for kernel variant that only supports
 // int8 activations and int8 weights and uses the latency optimized
 // implementations.
-TfLiteRegistration_V1 Register_UNIDIRECTIONAL_SEQUENCE_LSTM_INT8();
+TFLMRegistration Register_UNIDIRECTIONAL_SEQUENCE_LSTM_INT8();
 
 #else
-inline TfLiteRegistration_V1 Register_UNIDIRECTIONAL_SEQUENCE_LSTM_INT8() {
+inline TFLMRegistration Register_UNIDIRECTIONAL_SEQUENCE_LSTM_INT8() {
   return Register_UNIDIRECTIONAL_SEQUENCE_LSTM();
 }
 #endif

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa.h

@@ -22,13 +22,13 @@ limitations under the License.
 #include "tensorflow/lite/micro/kernels/xtensa/hifimini/fixedpoint_utils.h"
 #endif  // defined(HIFMINI)
 
-#if defined(HIFI4) || defined(HIFI5)
+#if defined(HIFI3) || defined(HIFI4) || defined(HIFI5)
 #include "include/nnlib/xa_nnlib_api.h"
 #include "include/nnlib/xa_nnlib_standards.h"
 
 #define ALIGNED_SIZE(x, bytes) (((x) + (bytes - 1)) & (~(bytes - 1)))
 #define ALIGN_PTR(x, bytes) ((((unsigned)(x)) + (bytes - 1)) & (~(bytes - 1)))
-#endif  // defined(HIFI4) || defined(HIFI5)
+#endif  // defined(HIFI3) || defined(HIFI4) || defined(HIFI5)
 
 #if defined(VISION_P6)
 #include "utils.h"

xmos_ai_tools/runtime/include/tensorflow/lite/micro/kernels/xtensa/xtensa_conv.h

@@ -25,9 +25,9 @@ namespace tflite {
 struct XtensaConvOpData {
   OpDataConv reference_op_data;
 
-#if defined(HIFI4) || defined(HIFI5)
+#if defined(HIFI3) || defined(HIFI4) || defined(HIFI5)
   int scratch_tensor_index;
-#endif  // defined(HIFI4) || defined(HIFI5)
+#endif  // defined(HIFI3) || defined(HIFI4) || defined(HIFI5)
 
 #if defined(VISION_P6)
   int8_t* reorder_coefficient_bias;  // buffers used to keep reordered coeff and
@@ -36,30 +36,32 @@ struct XtensaConvOpData {
   int8_t* per_channel_output_shift_int8;
   uint8_t* p_context;  // persistent lib context for this instance saved here
   uint32_t context_size;
+  bool is_per_channel_quantized;
 #endif  // VISION_P6
 };
 
-#if defined(HIFI4) || defined(HIFI5)
+#if defined(HIFI3) || defined(HIFI4) || defined(HIFI5)
 TfLiteStatus ConvPrepareHifi(TfLiteContext* context, TfLiteNode* node);
 
-TfLiteStatus ConvEvalHifi(TfLiteContext* context, TfLiteNode* node,
-                          const TfLiteConvParams& params,
-                          const XtensaConvOpData& data,
-                          const TfLiteEvalTensor* input,
-                          const TfLiteEvalTensor* filter,
-                          const TfLiteEvalTensor* bias,
-                          TfLiteEvalTensor* output);
-#endif  // defined(HIFI4) || defined(HIFI5)
-
-#if defined(HIFI4)
-TfLiteStatus ConvEvalHifi16(TfLiteContext* context, TfLiteNode* node,
-                            const TfLiteConvParams& params,
-                            const XtensaConvOpData& data,
-                            const TfLiteEvalTensor* input,
-                            const TfLiteEvalTensor* filter,
-                            const TfLiteEvalTensor* bias,
-                            TfLiteEvalTensor* output);
-#endif  // defined(HIFI4)
+TfLiteStatus ConvEvalHifiInt8(TfLiteContext* context, TfLiteNode* node,
+                              const TfLiteConvParams& params,
+                              const XtensaConvOpData& data,
+                              const TfLiteEvalTensor* input,
+                              const TfLiteEvalTensor* filter,
+                              const TfLiteEvalTensor* bias,
+                              TfLiteEvalTensor* output);
+
+#if defined(HIFI3) || defined(HIFI4)
+TfLiteStatus ConvEvalHifiInt16(TfLiteContext* context, TfLiteNode* node,
+                               const TfLiteConvParams& params,
+                               const XtensaConvOpData& data,
+                               const TfLiteEvalTensor* input,
+                               const TfLiteEvalTensor* filter,
+                               const TfLiteEvalTensor* bias,
+                               TfLiteEvalTensor* output);
+#endif  // defined(HIFI3) || defined(HIFI4)
+
+#endif  // defined(HIFI3) || defined(HIFI4) || defined(HIFI5)
 
 #if defined(VISION_P6)
 
@@ -79,6 +81,9 @@ TfLiteStatus ConvReferenceEvalInt8(TfLiteContext* context, TfLiteNode* node);
 
 TfLiteStatus ConvReferenceEvalInt16(TfLiteContext* context, TfLiteNode* node);
 
+void* ConvInitXtensa(TfLiteContext* context, const char* buffer, size_t length);
+TfLiteStatus ConvPrepareXtensa(TfLiteContext* context, TfLiteNode* node);
+
 }  // namespace tflite
 
 #endif  // TENSORFLOW_LITE_MICRO_KERNELS_XTENSA_XTENSA_CONV_H_