tdl-xoa-driver 1.7.1__py3-none-any.whl → 1.7.4__py3-none-any.whl

{tdl_xoa_driver-1.7.1.dist-info → tdl_xoa_driver-1.7.4.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: tdl-xoa-driver
-Version: 1.7.1
+Version: 1.7.4
 Summary: TDL XOA Python API is a Python library providing user-friendly communication interfaces to Teledyne LeCroy Xena Ethernet traffic generation test equipment. It provides a rich collection of APIs that can be used to either write test scripts or develop applications.
 Home-page: https://github.com/xenanetworks/tdl-xoa-driver
 Author: Leonard Yu, Zoltan Hanisch

{tdl_xoa_driver-1.7.1.dist-info → tdl_xoa_driver-1.7.4.dist-info}/RECORD

@@ -1,8 +1,8 @@
-tdl_xoa_driver-1.7.1.dist-info/licenses/LICENSE,sha256=KcCGoRYa8BS0KGUIHDIAeebClL6sX1uRWVrtESwpjOo,11351
-xoa_driver/__init__.py,sha256=qcnNgRe9QjMSe2PGgCiDKUZqf7e3cIfmgfFZpaF-IRQ,47
+tdl_xoa_driver-1.7.4.dist-info/licenses/LICENSE,sha256=KcCGoRYa8BS0KGUIHDIAeebClL6sX1uRWVrtESwpjOo,11351
+xoa_driver/__init__.py,sha256=T92DeWJjBmo2W0qwytgZFQvHTcwyltXiZHX-jy2Bmts,47
 xoa_driver/enums.py,sha256=bKYWqYkFfUyargNxvJi9_1cvrBy6EUIKkUvsl34frn8,8611
 xoa_driver/exceptions.py,sha256=baNpophPmeNujMTSfL9TsYHa3Gju2-ozNOg78n8tqN8,1957
-xoa_driver/hlfuncs.py,sha256=XxMAXe3NDOLr3PMSbTqJdmX7FKeqh4UhDW1g7s5Wpd4,385
+xoa_driver/hlfuncs.py,sha256=HbGw7HGyPGY_xsxTZujtozcV9cu0QIjEH3LKkJwokww,407
 xoa_driver/lli.py,sha256=PyT7DT9KxIM8PMw1JMu80J_KIifMPlCg9gd47J7SIjs,434
 xoa_driver/misc.py,sha256=JBFOiKU1z7DB99HXEDv-tiFM5PvNqNkcT7AxJXZ4lPk,1968
 xoa_driver/modules.py,sha256=sj7MeLNPqgPFtZU40WdrOQ7tV_WEFXCQfJ3FGnsE-BQ,10287
@@ -15,9 +15,10 @@ xoa_driver/functions/anlt_ll_debug.py,sha256=bKcAjMRslG733ASswIOkNwaUgnayzzKII0m
 xoa_driver/functions/async_wrapper.py,sha256=DivkplV3ULnFAuHbMmIcLTuYnlulKbZs0P5MZnC5-Kk,4009
 xoa_driver/functions/exceptions.py,sha256=JlQSHNmiSS_mOQygqituLQF5fFVg38LG4Ktz7qWHxf0,2667
 xoa_driver/functions/headers.py,sha256=Rf_em8LqCZOz0oxiqvtAFwx71_CtD9_I0p-vEZWtc6E,33886
-xoa_driver/functions/layer1_adv.py,sha256=Mbolxw4z4DCXpChZCEtTVjybXV0AHabRo9Cabjzv77A,11422
+xoa_driver/functions/layer1_adv.py,sha256=r7WgSn0qfsHefPZW2YmXym5POEyTUEV_qSeD97QXDFQ,12650
 xoa_driver/functions/mgmt.py,sha256=rPnlLxeaRIl8_LhJEvRfSn5npxZeqtrIiG_8Fx22a0k,19997
 xoa_driver/functions/tools.py,sha256=Wj00KfsuyFsp8HiEoHof28JCNLBYRKZ7FU48pyO2nyk,9916
+xoa_driver/functions/xcvr.py,sha256=I9T67OUUw6UrWbMeKzRtGtD7I39CftdlpqScgj1EO-E,8218
 xoa_driver/functions/cli/__init__.py,sha256=1qCG8oiucQ51v8tS6mAvu9MpBDQ4dqDhzx-EvdhDTQQ,458
 xoa_driver/functions/cli/_cli_manager.py,sha256=MKU2wS0Gxd514zvyWsm4qiYg-WLPA6vrHZy2QFcqpsU,22166
 xoa_driver/functions/cli/_config_block.py,sha256=KaNiAq4ht6Hfoo7iE2h03SAXhE3WX5efyHJcE74dYto,12245
@@ -49,7 +50,7 @@ xoa_driver/internals/commands/ped_commands.py,sha256=b2g_GHtUlYoiHsAslLBRguAEje7
 xoa_driver/internals/commands/pef_commands.py,sha256=phPVir8lEZxHBC2Dxj0NC1fNT04RPKN2LOAzSnqPJ9Y,83072
 xoa_driver/internals/commands/pf_commands.py,sha256=OZOksRT54YnerXVwU4SnVqT918cAqAwrNHnwgPgC1IU,14705
 xoa_driver/internals/commands/pl1_commands.py,sha256=1XtkDNT9ag8jVUwLQdQsk9ZTfwp2Td4Egvj1PU0kyI0,78643
-xoa_driver/internals/commands/pl1ad_commands.py,sha256=nIfDnHvaIboqCFZyfGfX3gG7kjMPRzHgrb00_fVf7Xg,22451
+xoa_driver/internals/commands/pl1ad_commands.py,sha256=j55mSP3RGvMzCQ3mFOGZHXOLJpXUHpJbDmSFzkaREmQ,22711
 xoa_driver/internals/commands/pl_commands.py,sha256=PGhIN4mK1wDM2JZBXCpTvGgnBLyLiHCYca-BTOc0liw,6497
 xoa_driver/internals/commands/pm_commands.py,sha256=GFB67ayuPevseNzrNIWt43X7unw0dp-TIVS-vS6ICB0,9666
 xoa_driver/internals/commands/pp_commands.py,sha256=M5kbbSJzv-RCC-oJ7P0T5fgP8TqQ5WoKBbl5kRSdq9c,83758
@@ -149,7 +150,7 @@ xoa_driver/internals/hli/ports/port_l23/family_odin.py,sha256=XMwRYHVsEwDQnFlqme
 xoa_driver/internals/hli/ports/port_l23/family_thor.py,sha256=AmvOB_7csbvr-KIKXPIRuzfMXHBbSbdnmmiU79k-tBs,1600
 xoa_driver/internals/hli/ports/port_l23/layer1_edun.py,sha256=JjC56MUwie5qq1DtPZdepBrpA7sCCBgNw4NdzOZcVes,3134
 xoa_driver/internals/hli/ports/port_l23/layer1_freya.py,sha256=cySM8AoivcXNMs7aUmGNVW17JIup5kIpH2EaAIYzubY,3343
-xoa_driver/internals/hli/ports/port_l23/layer1_freya_adv.py,sha256=tRj2aRjNQngG52D5NVV-K60Hr6yk1mn-jrwjQFFIP5U,1583
+xoa_driver/internals/hli/ports/port_l23/layer1_freya_adv.py,sha256=aXcF0mro92LNMiXjTXBoy2I5oUXckBvaEk5Y4cKwihI,1572
 xoa_driver/internals/hli/ports/port_l23/layer1_loki.py,sha256=NvvwpDIRfizv5sDjTsuwyZGrvkL-nvsu8c5YXpBl0Yk,2229
 xoa_driver/internals/hli/ports/port_l23/layer1_thor.py,sha256=_D6VgDzMfCIHK6yNRebHUjpn6KiI3MllAVxh3CRKzBU,2220
 xoa_driver/internals/hli/ports/port_l23/bases/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
@@ -190,7 +191,7 @@ xoa_driver/internals/hli/ports/port_l23/sec/__init__.py,sha256=47DEQpj8HBSa-_TIm
 xoa_driver/internals/hli/ports/port_l23/sec/macsec.py,sha256=HZNO5t-7WnQ2sUqLCFMXy4h80TOYJmx-9GF3MDrQoOg,3184
 xoa_driver/internals/hli/ports/port_l23/tcvr/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 xoa_driver/internals/hli/ports/port_l23/tcvr/cmis.py,sha256=gqCRk6JFbU4waol2zEaaORWvQE3IIrT-ASHm-DFUl-U,5713
-xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py,sha256=MzX2p109NyFKz4lhEyT6MAOQZ7uDCeJpM6Sx2rPcm84,4459
+xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py,sha256=U9R2_MzsPrMAqv0587L9S_HpyIXtbUTWhtRm2ZdmLIo,4313
 xoa_driver/internals/hli/ports/port_l23/trafficgen/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 xoa_driver/internals/hli/ports/port_l23/trafficgen/capture.py,sha256=mH_yPZW_3lTX9n1NTCMQlIixd5BWcb5VRfCrtpzY8I8,1955
 xoa_driver/internals/hli/ports/port_l23/trafficgen/runt.py,sha256=VuxgV2piV57hUlDKcO2sucYwhwpsVO3nwiE1qvexo6g,849
@@ -236,7 +237,7 @@ xoa_driver/internals/utils/managers/abc.py,sha256=M3XgI2FVQLUXixS5SKnZTm0MweHY6D
 xoa_driver/internals/utils/managers/exceptions.py,sha256=fqLSin-OQCIKuhpzvK6RZThF3FJ8FsHers4EmqM9gSs,628
 xoa_driver/internals/utils/managers/modules_manager.py,sha256=sCEhqUu7Waot16rucJ5nI9FyHuFEeU_sBx1JjZdhDJg,3236
 xoa_driver/internals/utils/managers/ports_manager.py,sha256=cmXGWMVbHB27E7e0t-K9mUDessdU_t_v-6WUtpqbIho,3554
-tdl_xoa_driver-1.7.1.dist-info/METADATA,sha256=2NvijpVYnk2Sowh5uevaUP599vbDgNPZDWPcnC6pPm0,4171
-tdl_xoa_driver-1.7.1.dist-info/WHEEL,sha256=wUyA8OaulRlbfwMtmQsvNngGrxQHAvkKcvRmdizlJi0,92
-tdl_xoa_driver-1.7.1.dist-info/top_level.txt,sha256=sBbN3hwpa4s2VxsUBoWJ5jIqqDr50vgcEb-V8kL7pvE,11
-tdl_xoa_driver-1.7.1.dist-info/RECORD,,
+tdl_xoa_driver-1.7.4.dist-info/METADATA,sha256=c-i_qWZ5tnP-sokYsmKos2Hsqh38-NNAatMM1rpQ4Do,4171
+tdl_xoa_driver-1.7.4.dist-info/WHEEL,sha256=wUyA8OaulRlbfwMtmQsvNngGrxQHAvkKcvRmdizlJi0,92
+tdl_xoa_driver-1.7.4.dist-info/top_level.txt,sha256=sBbN3hwpa4s2VxsUBoWJ5jIqqDr50vgcEb-V8kL7pvE,11
+tdl_xoa_driver-1.7.4.dist-info/RECORD,,

xoa_driver/__init__.py

@@ -1,2 +1,2 @@
-__version__ = "1.7.1"
+__version__ = "1.7.4"
 __short_version__ = "1.7"

xoa_driver/functions/layer1_adv.py

@@ -18,6 +18,9 @@ if TYPE_CHECKING:
     FreyaEdunPort = Union[Z800FreyaPort, Z1600EdunPort]
 
 from ..utils import apply
+from ..enums import (
+    OnOff,
+)
 
 
 
@@ -95,7 +98,7 @@ async def get_rx_freq_all(port: "Z800FreyaPort") -> Tuple[int, int, int]:
     return (resp1.frequency_hz, resp2.frequency_hz, resp3.frequency_hz)
 
 
-async def get_cdr_lol_since_last(port: "Z800FreyaPort", serdes_indices: List[int]) -> List[Tuple[bool, bool]]:
+async def get_cdr_lol(port: "Z800FreyaPort", serdes_indices: List[int]) -> List[Tuple[bool, bool]]:
     """
     Get the current and latched CDR LOL status of the specified Serdes.
 
@@ -109,7 +112,7 @@ async def get_cdr_lol_since_last(port: "Z800FreyaPort", serdes_indices: List[int
     results = []
     cmds = []
     for serdes_id in serdes_indices:
-        cmds.append(port.layer1_adv.serdes[serdes_id].rx_cdr_lol_since_last.get())
+        cmds.append(port.layer1_adv.serdes[serdes_id].rx_cdr_lol.get())
     resps = await apply(*cmds)
     for resp in resps:
         curr = True if resp.current_lol.value == 1 else False
@@ -153,7 +156,7 @@ async def get_hi_ber(port: "Z800FreyaPort") -> Tuple[bool, bool]:
     return (curr, latched)
 
 
-async def get_hi_ser(port: "Z800FreyaPort") -> Tuple[bool, bool]:
+async def get_hi_ser(port: "Z800FreyaPort") -> Tuple[bool, bool, bool]:
     """
     Get the current and latched HI-SER status of the specified port.
 
@@ -161,13 +164,14 @@ async def get_hi_ser(port: "Z800FreyaPort") -> Tuple[bool, bool]:
 
     :param port: The port instance.
     :type port: :class:`~xoa_driver.ports.Z800FreyaPort`
-    :return: A tuple containing current and latched HI-SER status.
-    :rtype: Tuple[bool, bool]
+    :return: A tuple containing alarm state, current and latched HI-SER status.
+    :rtype: Tuple[bool, bool, bool]
     """
     resp = await port.layer1_adv.pcs.hi_ser.status.get()
+    alarm_state = True if resp.alarm_state == OnOff.ON else False
     curr = True if resp.current_hiser.value == 1 else False
     latched = True if resp.latched_hiser.value == 1 else False
-    return (curr, latched)
+    return (alarm_state, curr, latched)
 
 
 async def get_deg_ser(port: "Z800FreyaPort") -> Tuple[bool, bool]:
@@ -318,13 +322,48 @@ async def get_total_loa_since_last(port: "Z800FreyaPort") -> int:
     return resp.loa_count
 
 
+async def set_cw_err(port: "Z800FreyaPort") -> None:
+    """
+    Inject a 64b/66b codeword error (CW Err) from the port immediately when called.
+
+    :param port: The port instance.
+    :type port: :class:`~xoa_driver.ports.Z800FreyaPort`
+    """
+    await port.layer1_adv.pcs.err_cw.tx_err_cw.set()
+
+
+async def set_itb(port: "Z800FreyaPort") -> None:
+    """
+    Inject an invalid 256b/257b transcode block (ITB) from the port immediately when called.
+
+    :param port: The port instance.
+    :type port: :class:`~xoa_driver.ports.Z800FreyaPort`
+    """
+    await port.layer1_adv.pcs.itb.tx_itb.set()
+
+
+async def set_hi_ser_alarm(port: "Z800FreyaPort", on: bool) -> None:
+    """
+    Set the HI-SER alarm on or off on the port.
+
+    :param port: The port instance.
+    :type port: :class:`~xoa_driver.ports.Z800FreyaPort`
+    :param on: Set to `True` to enable the HI-SER alarm, or `False` to disable the HI-SER alarm.
+    """
+    if on:
+        await port.layer1_adv.pcs.hi_ser.alarm.set_on()
+    else:
+        await port.layer1_adv.pcs.hi_ser.alarm.set_off()
+
+
+
 __all__ = (
     "get_tx_freq_curr",
     "get_rx_freq_curr",
     "get_rx_freq_min",
     "get_rx_freq_max",
     "get_rx_freq_all",
-    "get_cdr_lol_since_last",
+    "get_cdr_lol",
     "get_rx_lane_skew",
     "get_hi_ber",
     "get_hi_ser",
@@ -337,4 +376,7 @@ __all__ = (
     "get_local_fault_since_last",
     "get_remote_fault_since_last",
     "get_total_loa_since_last",
+    "set_cw_err",
+    "set_itb",
+    "set_hi_ser_alarm",
 )

xoa_driver/functions/xcvr.py

@@ -0,0 +1,196 @@
+"""
+Transceiver R/W functions
+"""
+
+from __future__ import annotations
+import asyncio
+from typing import (
+    TYPE_CHECKING,
+    Any,
+    Union,
+    List,
+    Tuple,
+)
+if TYPE_CHECKING:
+    from xoa_driver.ports import Z800FreyaPort, Z1600EdunPort, Z100LokiPort, Z10OdinPort, Z400ThorPort
+
+from ..misc import Hex
+
+
+
+async def get_xcvr_rw_seq_bank(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", bank: int, page: int, register: int, length: int) -> str:
+    """Read a number of bytes from transceiver register interface via I2C.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param bank: The bank address, e.g. 10 or 0xA
+    :type bank: int
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param length: The number of bytes to read
+    :type length: int
+    :return: The read bytes as a string, e.g. 'DEADBEEF'
+    :rtype: str
+    """
+
+    resp = await port.transceiver.access_rw_seq_bank(bank_address=bank, page_address=page, register_address=register, byte_count=length).get()
+    return resp.value
+
+async def set_xcvr_rw_seq_bank(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", bank: int, page: int, register: int, value: str) -> None:
+    """Write a number of bytes to transceiver register interface via I2C.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param bank: The bank address, e.g. 10 or 0xA
+    :type bank: int
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param value: The bytes to write as a string, e.g. 'DEADBEEF'
+    :type value: str
+    """
+    await port.transceiver.access_rw_seq_bank(bank_address=bank, page_address=page, register_address=register, byte_count=len(value)//2).set(value=Hex(value))
+
+
+async def get_xcvr_rw_seq(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", page: int, register: int, length: int) -> str:
+    """Read a number of bytes from transceiver register interface via I2C.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param length: The number of bytes to read
+    :type length: int
+    :return: The read bytes as a string, e.g. 'DEADBEEF'
+    :rtype: str
+    """
+
+    resp = await port.transceiver.access_rw_seq(page_address=page, register_address=register, byte_count=length).get()
+    return resp.value
+
+async def set_xcvr_rw_seq(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", page: int, register: int, value: str) -> None:
+    """Write a number of bytes to transceiver register interface via I2C.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param value: The bytes to write as a string, e.g. 'DEADBEEF'
+    :type value: str
+    """
+    await port.transceiver.access_rw_seq(page_address=page, register_address=register, byte_count=len(value)//2).set(value=Hex(value))
+
+
+async def get_xcvr_rw(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", page: int, register: int) -> str:
+    """Read 4 bytes from transceiver register interface.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :return: The read bytes as a string, e.g. 'DEADBEEF'
+    :rtype: str
+    """
+
+    resp = await port.transceiver.access_rw(page_address=page, register_address=register).get()
+    return resp.value
+
+async def set_xcvr_rw(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", page: int, register: int, value: str) -> None:
+    """Write 4 bytes to transceiver register interface.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param value: The bytes to write as a string, e.g. 'DEADBEEF'
+    :type value: str
+    """
+    await port.transceiver.access_rw(page_address=page, register_address=register).set(value=Hex(value))
+
+async def get_xcvr_mii(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", register: int) -> str:
+    """Read 2 bytes from transceiver register interface.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :return: The read 2 bytes as a string, e.g. 'DEAF'
+    :rtype: str
+    """
+
+    resp = await port.transceiver.access_mii(register_address=register).get()
+    return resp.value
+
+async def set_xcvr_mii(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort",register: int, value: str) -> None:
+    """Write 2 bytes to transceiver register interface.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param value: The 2 bytes to write as a string, e.g. 'DEAF'
+    :type value: str
+    """
+    await port.transceiver.access_mii(register_address=register).set(value=Hex(value))
+
+async def get_i2c_freq_khz(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort") -> int:
+    """Read access speed on a transceiver I2C access in the unit of KHz. Default to 100. 
+    
+    When the transceiver is plugged out and in again, the speed will be reset to the default value 100. The speed has a minimum and a maximum, which can be obtained from P_CAPABILITIES. 
+    
+    The I2C speed configuration will not be included in the port configuration file (.xpc). 
+    When you load a port configuration to a port, the transceiver I2C access speed will be reset to default 100.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :return: The current I2C access speed in KHz
+    :rtype: int
+    """
+
+    resp = await port.transceiver.i2c_config.get()
+    return resp.frequency
+
+async def set_i2c_freq_khz(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", frequency: int) -> None:
+    """Set access speed on a transceiver I2C access in the unit of KHz.
+    
+    When the transceiver is plugged out and in again, the speed will be reset to the default value 100. The speed has a minimum and a maximum, which can be obtained from P_CAPABILITIES. 
+    
+    The I2C speed configuration will not be included in the port configuration file (.xpc). 
+    When you load a port configuration to a port, the transceiver I2C access speed will be reset to default 100.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param frequency: The desired I2C access speed in KHz
+    :type frequency: int
+    """
+
+    await port.transceiver.i2c_config.set(frequency=frequency)
+
+
+
+
+__all__ = (
+    "get_xcvr_rw_seq_bank",
+    "set_xcvr_rw_seq_bank",
+    "get_xcvr_rw_seq",
+    "set_xcvr_rw_seq",
+    "get_xcvr_rw",
+    "set_xcvr_rw",
+    "get_xcvr_mii",
+    "set_xcvr_mii",
+    "get_i2c_freq_khz",
+    "set_i2c_freq_khz",
+)

xoa_driver/hlfuncs.py

@@ -11,6 +11,7 @@ from xoa_driver.functions import (
     cmis,
     layer1_adv,
     async_wrapper,
+    xcvr,
 )
 
 __all__ = (
@@ -23,4 +24,5 @@ __all__ = (
     "cmis",
     "layer1_adv",
     "async_wrapper",
+    "xcvr",
 )

xoa_driver/internals/commands/pl1ad_commands.py

@@ -35,7 +35,7 @@ class PL1AD_RX_FREQ_CURR:
 
     """
 
-    code: typing.ClassVar[int] = 1303
+    code: typing.ClassVar[int] = 553
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -65,7 +65,7 @@ class PL1AD_RX_FREQ_MIN:
 
     """
 
-    code: typing.ClassVar[int] = 1305
+    code: typing.ClassVar[int] = 554
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -94,7 +94,7 @@ class PL1AD_RX_FREQ_MAX:
 
     """
 
-    code: typing.ClassVar[int] = 1304
+    code: typing.ClassVar[int] = 555
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -123,7 +123,7 @@ class PL1AD_RX_LOL:
 
     """
 
-    code: typing.ClassVar[int] = 1312
+    code: typing.ClassVar[int] = 556
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -157,7 +157,7 @@ class PL1AD_RX_SKEW:
 
     """
 
-    code: typing.ClassVar[int] = 1315
+    code: typing.ClassVar[int] = 557
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -187,7 +187,7 @@ class PL1AD_RX_HIBER:
     Returns the current and the latched High BER status of the port.
     """
 
-    code: typing.ClassVar[int] = 1306
+    code: typing.ClassVar[int] = 558
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -222,7 +222,7 @@ class PL1AD_RX_HISER:
 
     """
 
-    code: typing.ClassVar[int] = 1307
+    code: typing.ClassVar[int] = 559
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -258,7 +258,7 @@ class PL1AD_RX_HISER_ALARM:
 
     """
 
-    code: typing.ClassVar[int] = 1308
+    code: typing.ClassVar[int] = 560
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -291,6 +291,13 @@ class PL1AD_RX_HISER_ALARM:
         """
 
         return Token(self._connection, build_set_request(self, module=self._module, port=self._port, alarm_state=alarm_state))
+    
+
+    set_off = functools.partialmethod(set, OnOff.OFF)
+    """Set the High SER Alarm state of the port to `OFF`, disabling the alarm."""
+    
+    set_on = functools.partialmethod(set, OnOff.ON)
+    """Set the High SER Alarm state of the port to `ON`, enabling the alarm."""
 
 
 @register_command
@@ -303,7 +310,7 @@ class PL1AD_RX_DEG_SER:
 
     """
 
-    code: typing.ClassVar[int] = 1300
+    code: typing.ClassVar[int] = 561
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -351,7 +358,7 @@ class PL1AD_RX_DEG_SER_THRESH:
 
     """
 
-    code: typing.ClassVar[int] = 1301
+    code: typing.ClassVar[int] = 562
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -412,7 +419,7 @@ class PL1AD_RX_ERR_CW_CNT:
 
     """
 
-    code: typing.ClassVar[int] = 1302
+    code: typing.ClassVar[int] = 563
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -444,7 +451,7 @@ class PL1AD_RX_ITB_CNT:
 
     """
 
-    code: typing.ClassVar[int] = 1309
+    code: typing.ClassVar[int] = 564
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -477,7 +484,7 @@ class PL1AD_RX_LOSYNC_CNT:
 
     """
 
-    code: typing.ClassVar[int] = 1313
+    code: typing.ClassVar[int] = 565
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -511,7 +518,7 @@ class PL1AD_RX_LF_CNT:
 
     """
 
-    code: typing.ClassVar[int] = 1310
+    code: typing.ClassVar[int] = 566
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -544,7 +551,7 @@ class PL1AD_RX_RF_CNT:
 
     """
 
-    code: typing.ClassVar[int] = 1314
+    code: typing.ClassVar[int] = 567
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -576,7 +583,7 @@ class PL1AD_RX_LOA_CNT:
     Use ``PP_RXCLEAR`` to reset the counter.
     """
 
-    code: typing.ClassVar[int] = 1311
+    code: typing.ClassVar[int] = 568
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -606,7 +613,7 @@ class PL1AD_TX_FREQ_CURR:
     Return the current port Tx frequency in Hz.
     """
 
-    code: typing.ClassVar[int] = 1317
+    code: typing.ClassVar[int] = 570
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -636,7 +643,7 @@ class PL1AD_TX_ERR_CW:
 
     """
 
-    code: typing.ClassVar[int] = 1316
+    code: typing.ClassVar[int] = 571
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'
@@ -661,7 +668,7 @@ class PL1AD_TX_ITB:
 
     """
 
-    code: typing.ClassVar[int] = 1318
+    code: typing.ClassVar[int] = 572
     pushed: typing.ClassVar[bool] = False
 
     _connection: 'interfaces.IConnection'

xoa_driver/internals/hli/ports/port_l23/layer1_freya_adv.py

@@ -19,7 +19,7 @@ class SerdesAdv:
 
     def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_idx: int) -> None:
 
-        self.rx_cdr_lol_since_last = PL1AD_RX_LOL(conn, module_id, port_id, serdes_idx)
+        self.rx_cdr_lol = PL1AD_RX_LOL(conn, module_id, port_id, serdes_idx)
         """Returns the current and the latched CDR Loss of Lock (LOL) status of the specified Serdes.
 
         :type: PL1AD_RX_LOL

xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py

@@ -45,7 +45,7 @@ class Transceiver:
         """
 
     def access_rw(self, page_address: int, register_address: int) -> "PX_RW":
-        """Access to register interface by the transceiver.
+        """R/W access (4 bytes) to register interface by the transceiver.
 
         :param page_address: page address
         :type page_address: int
@@ -64,7 +64,7 @@ class Transceiver:
         )
 
     def access_mii(self, register_address: int) -> "PX_MII":
-        """Access to the register interface supported by the media-independent interface (MII) transceiver.
+        """R/W access (2 bytes) to the register interface supported by MII transceiver.
 
         :param register_address: register address
         :type register_address: int
@@ -79,7 +79,7 @@ class Transceiver:
         )
 
     def access_rw_seq(self, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ":
-        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+        """Sequential R/W a number of bytes to the register interface.
 
         :param page_address: page address (0-255)
         :type page_address: int
@@ -100,7 +100,7 @@ class Transceiver:
         )
     
     def access_rw_seq_bank(self, bank_address: int, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ_BANK":
-        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+        """Sequential R/W a number of bytes to the register interface.
 
         :param bank_address: bank address (0-255)
         :type bank_address: int