tdl-xoa-driver 1.7.1__py3-none-any.whl → 1.7.2__py3-none-any.whl

{tdl_xoa_driver-1.7.1.dist-info → tdl_xoa_driver-1.7.2.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: tdl-xoa-driver
-Version: 1.7.1
+Version: 1.7.2
 Summary: TDL XOA Python API is a Python library providing user-friendly communication interfaces to Teledyne LeCroy Xena Ethernet traffic generation test equipment. It provides a rich collection of APIs that can be used to either write test scripts or develop applications.
 Home-page: https://github.com/xenanetworks/tdl-xoa-driver
 Author: Leonard Yu, Zoltan Hanisch

{tdl_xoa_driver-1.7.1.dist-info → tdl_xoa_driver-1.7.2.dist-info}/RECORD

@@ -1,8 +1,8 @@
-tdl_xoa_driver-1.7.1.dist-info/licenses/LICENSE,sha256=KcCGoRYa8BS0KGUIHDIAeebClL6sX1uRWVrtESwpjOo,11351
-xoa_driver/__init__.py,sha256=qcnNgRe9QjMSe2PGgCiDKUZqf7e3cIfmgfFZpaF-IRQ,47
+tdl_xoa_driver-1.7.2.dist-info/licenses/LICENSE,sha256=KcCGoRYa8BS0KGUIHDIAeebClL6sX1uRWVrtESwpjOo,11351
+xoa_driver/__init__.py,sha256=my0_cIbrINVq23cNQpfIfw8trjhpryw9x_IRDbJlEzY,47
 xoa_driver/enums.py,sha256=bKYWqYkFfUyargNxvJi9_1cvrBy6EUIKkUvsl34frn8,8611
 xoa_driver/exceptions.py,sha256=baNpophPmeNujMTSfL9TsYHa3Gju2-ozNOg78n8tqN8,1957
-xoa_driver/hlfuncs.py,sha256=XxMAXe3NDOLr3PMSbTqJdmX7FKeqh4UhDW1g7s5Wpd4,385
+xoa_driver/hlfuncs.py,sha256=HbGw7HGyPGY_xsxTZujtozcV9cu0QIjEH3LKkJwokww,407
 xoa_driver/lli.py,sha256=PyT7DT9KxIM8PMw1JMu80J_KIifMPlCg9gd47J7SIjs,434
 xoa_driver/misc.py,sha256=JBFOiKU1z7DB99HXEDv-tiFM5PvNqNkcT7AxJXZ4lPk,1968
 xoa_driver/modules.py,sha256=sj7MeLNPqgPFtZU40WdrOQ7tV_WEFXCQfJ3FGnsE-BQ,10287
@@ -18,6 +18,7 @@ xoa_driver/functions/headers.py,sha256=Rf_em8LqCZOz0oxiqvtAFwx71_CtD9_I0p-vEZWtc
 xoa_driver/functions/layer1_adv.py,sha256=Mbolxw4z4DCXpChZCEtTVjybXV0AHabRo9Cabjzv77A,11422
 xoa_driver/functions/mgmt.py,sha256=rPnlLxeaRIl8_LhJEvRfSn5npxZeqtrIiG_8Fx22a0k,19997
 xoa_driver/functions/tools.py,sha256=Wj00KfsuyFsp8HiEoHof28JCNLBYRKZ7FU48pyO2nyk,9916
+xoa_driver/functions/xcvr.py,sha256=I9T67OUUw6UrWbMeKzRtGtD7I39CftdlpqScgj1EO-E,8218
 xoa_driver/functions/cli/__init__.py,sha256=1qCG8oiucQ51v8tS6mAvu9MpBDQ4dqDhzx-EvdhDTQQ,458
 xoa_driver/functions/cli/_cli_manager.py,sha256=MKU2wS0Gxd514zvyWsm4qiYg-WLPA6vrHZy2QFcqpsU,22166
 xoa_driver/functions/cli/_config_block.py,sha256=KaNiAq4ht6Hfoo7iE2h03SAXhE3WX5efyHJcE74dYto,12245
@@ -190,7 +191,7 @@ xoa_driver/internals/hli/ports/port_l23/sec/__init__.py,sha256=47DEQpj8HBSa-_TIm
 xoa_driver/internals/hli/ports/port_l23/sec/macsec.py,sha256=HZNO5t-7WnQ2sUqLCFMXy4h80TOYJmx-9GF3MDrQoOg,3184
 xoa_driver/internals/hli/ports/port_l23/tcvr/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 xoa_driver/internals/hli/ports/port_l23/tcvr/cmis.py,sha256=gqCRk6JFbU4waol2zEaaORWvQE3IIrT-ASHm-DFUl-U,5713
-xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py,sha256=MzX2p109NyFKz4lhEyT6MAOQZ7uDCeJpM6Sx2rPcm84,4459
+xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py,sha256=U9R2_MzsPrMAqv0587L9S_HpyIXtbUTWhtRm2ZdmLIo,4313
 xoa_driver/internals/hli/ports/port_l23/trafficgen/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 xoa_driver/internals/hli/ports/port_l23/trafficgen/capture.py,sha256=mH_yPZW_3lTX9n1NTCMQlIixd5BWcb5VRfCrtpzY8I8,1955
 xoa_driver/internals/hli/ports/port_l23/trafficgen/runt.py,sha256=VuxgV2piV57hUlDKcO2sucYwhwpsVO3nwiE1qvexo6g,849
@@ -236,7 +237,7 @@ xoa_driver/internals/utils/managers/abc.py,sha256=M3XgI2FVQLUXixS5SKnZTm0MweHY6D
 xoa_driver/internals/utils/managers/exceptions.py,sha256=fqLSin-OQCIKuhpzvK6RZThF3FJ8FsHers4EmqM9gSs,628
 xoa_driver/internals/utils/managers/modules_manager.py,sha256=sCEhqUu7Waot16rucJ5nI9FyHuFEeU_sBx1JjZdhDJg,3236
 xoa_driver/internals/utils/managers/ports_manager.py,sha256=cmXGWMVbHB27E7e0t-K9mUDessdU_t_v-6WUtpqbIho,3554
-tdl_xoa_driver-1.7.1.dist-info/METADATA,sha256=2NvijpVYnk2Sowh5uevaUP599vbDgNPZDWPcnC6pPm0,4171
-tdl_xoa_driver-1.7.1.dist-info/WHEEL,sha256=wUyA8OaulRlbfwMtmQsvNngGrxQHAvkKcvRmdizlJi0,92
-tdl_xoa_driver-1.7.1.dist-info/top_level.txt,sha256=sBbN3hwpa4s2VxsUBoWJ5jIqqDr50vgcEb-V8kL7pvE,11
-tdl_xoa_driver-1.7.1.dist-info/RECORD,,
+tdl_xoa_driver-1.7.2.dist-info/METADATA,sha256=3pLZYkLPhQp54_Lr4NHmMNsgvBF-SS9i4IOiHIsYyKc,4171
+tdl_xoa_driver-1.7.2.dist-info/WHEEL,sha256=wUyA8OaulRlbfwMtmQsvNngGrxQHAvkKcvRmdizlJi0,92
+tdl_xoa_driver-1.7.2.dist-info/top_level.txt,sha256=sBbN3hwpa4s2VxsUBoWJ5jIqqDr50vgcEb-V8kL7pvE,11
+tdl_xoa_driver-1.7.2.dist-info/RECORD,,

xoa_driver/__init__.py

@@ -1,2 +1,2 @@
-__version__ = "1.7.1"
+__version__ = "1.7.2"
 __short_version__ = "1.7"

xoa_driver/functions/xcvr.py

@@ -0,0 +1,196 @@
+"""
+Transceiver R/W functions
+"""
+
+from __future__ import annotations
+import asyncio
+from typing import (
+    TYPE_CHECKING,
+    Any,
+    Union,
+    List,
+    Tuple,
+)
+if TYPE_CHECKING:
+    from xoa_driver.ports import Z800FreyaPort, Z1600EdunPort, Z100LokiPort, Z10OdinPort, Z400ThorPort
+
+from ..misc import Hex
+
+
+
+async def get_xcvr_rw_seq_bank(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", bank: int, page: int, register: int, length: int) -> str:
+    """Read a number of bytes from transceiver register interface via I2C.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param bank: The bank address, e.g. 10 or 0xA
+    :type bank: int
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param length: The number of bytes to read
+    :type length: int
+    :return: The read bytes as a string, e.g. 'DEADBEEF'
+    :rtype: str
+    """
+
+    resp = await port.transceiver.access_rw_seq_bank(bank_address=bank, page_address=page, register_address=register, byte_count=length).get()
+    return resp.value
+
+async def set_xcvr_rw_seq_bank(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", bank: int, page: int, register: int, value: str) -> None:
+    """Write a number of bytes to transceiver register interface via I2C.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param bank: The bank address, e.g. 10 or 0xA
+    :type bank: int
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param value: The bytes to write as a string, e.g. 'DEADBEEF'
+    :type value: str
+    """
+    await port.transceiver.access_rw_seq_bank(bank_address=bank, page_address=page, register_address=register, byte_count=len(value)//2).set(value=Hex(value))
+
+
+async def get_xcvr_rw_seq(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", page: int, register: int, length: int) -> str:
+    """Read a number of bytes from transceiver register interface via I2C.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param length: The number of bytes to read
+    :type length: int
+    :return: The read bytes as a string, e.g. 'DEADBEEF'
+    :rtype: str
+    """
+
+    resp = await port.transceiver.access_rw_seq(page_address=page, register_address=register, byte_count=length).get()
+    return resp.value
+
+async def set_xcvr_rw_seq(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", page: int, register: int, value: str) -> None:
+    """Write a number of bytes to transceiver register interface via I2C.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param value: The bytes to write as a string, e.g. 'DEADBEEF'
+    :type value: str
+    """
+    await port.transceiver.access_rw_seq(page_address=page, register_address=register, byte_count=len(value)//2).set(value=Hex(value))
+
+
+async def get_xcvr_rw(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", page: int, register: int) -> str:
+    """Read 4 bytes from transceiver register interface.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :return: The read bytes as a string, e.g. 'DEADBEEF'
+    :rtype: str
+    """
+
+    resp = await port.transceiver.access_rw(page_address=page, register_address=register).get()
+    return resp.value
+
+async def set_xcvr_rw(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", page: int, register: int, value: str) -> None:
+    """Write 4 bytes to transceiver register interface.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param value: The bytes to write as a string, e.g. 'DEADBEEF'
+    :type value: str
+    """
+    await port.transceiver.access_rw(page_address=page, register_address=register).set(value=Hex(value))
+
+async def get_xcvr_mii(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", register: int) -> str:
+    """Read 2 bytes from transceiver register interface.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :return: The read 2 bytes as a string, e.g. 'DEAF'
+    :rtype: str
+    """
+
+    resp = await port.transceiver.access_mii(register_address=register).get()
+    return resp.value
+
+async def set_xcvr_mii(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort",register: int, value: str) -> None:
+    """Write 2 bytes to transceiver register interface.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param page: The page address, e.g. 10 or 0xA
+    :type page: int
+    :param register: The register address, e.g. 10 or 0xA
+    :type register: int
+    :param value: The 2 bytes to write as a string, e.g. 'DEAF'
+    :type value: str
+    """
+    await port.transceiver.access_mii(register_address=register).set(value=Hex(value))
+
+async def get_i2c_freq_khz(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort") -> int:
+    """Read access speed on a transceiver I2C access in the unit of KHz. Default to 100. 
+    
+    When the transceiver is plugged out and in again, the speed will be reset to the default value 100. The speed has a minimum and a maximum, which can be obtained from P_CAPABILITIES. 
+    
+    The I2C speed configuration will not be included in the port configuration file (.xpc). 
+    When you load a port configuration to a port, the transceiver I2C access speed will be reset to default 100.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :return: The current I2C access speed in KHz
+    :rtype: int
+    """
+
+    resp = await port.transceiver.i2c_config.get()
+    return resp.frequency
+
+async def set_i2c_freq_khz(port: "Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort", frequency: int) -> None:
+    """Set access speed on a transceiver I2C access in the unit of KHz.
+    
+    When the transceiver is plugged out and in again, the speed will be reset to the default value 100. The speed has a minimum and a maximum, which can be obtained from P_CAPABILITIES. 
+    
+    The I2C speed configuration will not be included in the port configuration file (.xpc). 
+    When you load a port configuration to a port, the transceiver I2C access speed will be reset to default 100.
+
+    :param port: The port object
+    :type port: Z1600EdunPort | Z800FreyaPort | Z400ThorPort | Z100LokiPort | Z10OdinPort
+    :param frequency: The desired I2C access speed in KHz
+    :type frequency: int
+    """
+
+    await port.transceiver.i2c_config.set(frequency=frequency)
+
+
+
+
+__all__ = (
+    "get_xcvr_rw_seq_bank",
+    "set_xcvr_rw_seq_bank",
+    "get_xcvr_rw_seq",
+    "set_xcvr_rw_seq",
+    "get_xcvr_rw",
+    "set_xcvr_rw",
+    "get_xcvr_mii",
+    "set_xcvr_mii",
+    "get_i2c_freq_khz",
+    "set_i2c_freq_khz",
+)

xoa_driver/hlfuncs.py

@@ -11,6 +11,7 @@ from xoa_driver.functions import (
     cmis,
     layer1_adv,
     async_wrapper,
+    xcvr,
 )
 
 __all__ = (
@@ -23,4 +24,5 @@ __all__ = (
     "cmis",
     "layer1_adv",
     "async_wrapper",
+    "xcvr",
 )

xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py

@@ -45,7 +45,7 @@ class Transceiver:
         """
 
     def access_rw(self, page_address: int, register_address: int) -> "PX_RW":
-        """Access to register interface by the transceiver.
+        """R/W access (4 bytes) to register interface by the transceiver.
 
         :param page_address: page address
         :type page_address: int
@@ -64,7 +64,7 @@ class Transceiver:
         )
 
     def access_mii(self, register_address: int) -> "PX_MII":
-        """Access to the register interface supported by the media-independent interface (MII) transceiver.
+        """R/W access (2 bytes) to the register interface supported by MII transceiver.
 
         :param register_address: register address
         :type register_address: int
@@ -79,7 +79,7 @@ class Transceiver:
         )
 
     def access_rw_seq(self, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ":
-        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+        """Sequential R/W a number of bytes to the register interface.
 
         :param page_address: page address (0-255)
         :type page_address: int
@@ -100,7 +100,7 @@ class Transceiver:
         )
     
     def access_rw_seq_bank(self, bank_address: int, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ_BANK":
-        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+        """Sequential R/W a number of bytes to the register interface.
 
         :param bank_address: bank address (0-255)
         :type bank_address: int