tdl-xoa-driver 1.6.3__py3-none-any.whl → 1.7.2__py3-none-any.whl

xoa_driver/internals/hli/ports/port_l23/family_freya.py

@@ -14,6 +14,7 @@ if TYPE_CHECKING:
 
 from .bases.port_l23_genuine import BasePortL23Genuine
 from .layer1_freya import Layer1
+from .layer1_freya_adv import Layer1Adv
 
 
 class FamilyFreya(BasePortL23Genuine):
@@ -30,6 +31,10 @@ class FamilyFreya(BasePortL23Genuine):
 
         self.layer1 = Layer1(self._conn, self)
         """Layer 1"""
+
+        self.layer1_adv = Layer1Adv(self._conn, self)
+        """Layer 1 Advanced"""
+
         return self
 
     on_dynamic_change = functools.partialmethod(utils.on_event, P_DYNAMIC)

xoa_driver/internals/hli/ports/port_l23/family_odin.py

@@ -64,7 +64,7 @@ class POdin1G3S6PE(POdin1G3S6P):
     ...
 
 
-class POdin1G3S2PT(FamilyOdin):
+class POdin1G3S2PT(POdin1G3S6P):
     """L23 port on Odin-1G-3S-2P-T module.
     """
     ...

xoa_driver/internals/hli/ports/port_l23/layer1_adv/freq.py

@@ -0,0 +1,38 @@
+from typing import TYPE_CHECKING
+from xoa_driver.internals.commands import (
+    PL1AD_RX_FREQ_CURR,
+    PL1AD_RX_FREQ_MAX,
+    PL1AD_RX_FREQ_MIN,
+    PL1AD_TX_FREQ_CURR,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+
+
+class FrequencyAdv:
+    """Frequency Management"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.rx_curr = PL1AD_RX_FREQ_CURR(conn, module_id, port_id)
+        """Returns the current receive frequency.
+        
+        :type: PL1AD_RX_FREQ_CURR
+        """
+
+        self.rx_max = PL1AD_RX_FREQ_MAX(conn, module_id, port_id)
+        """Returns the maximum receive frequency.
+        
+        :type: PL1AD_RX_FREQ_MAX
+        """
+
+        self.rx_min = PL1AD_RX_FREQ_MIN(conn, module_id, port_id)
+        """Returns the minimum receive frequency.
+
+        :type: PL1AD_RX_FREQ_MIN
+        """
+
+        self.tx_curr = PL1AD_TX_FREQ_CURR(conn, module_id, port_id)
+        """Returns the current transmit frequency.
+
+        :type: PL1AD_TX_FREQ_CURR
+        """

xoa_driver/internals/hli/ports/port_l23/layer1_adv/pcs_fec.py

@@ -0,0 +1,214 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+    Union,
+    Self,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+    from xoa_driver.internals.hli.ports.port_l23.family_freya import FamilyFreya
+
+from xoa_driver.internals.commands import (
+    PL1AD_RX_HIBER,
+    PL1AD_RX_HISER,
+    PL1AD_RX_HISER_ALARM,
+    PL1AD_RX_ITB_CNT,
+    PL1AD_TX_ITB,
+    PL1AD_RX_DEG_SER,
+    PL1AD_RX_DEG_SER_THRESH,
+    PL1AD_RX_ERR_CW_CNT,
+    PL1AD_TX_ERR_CW,
+    PL1AD_RX_SKEW,
+    PL1AD_RX_LOA_CNT,
+    PL1AD_RX_LOSYNC_CNT,
+)
+
+
+class PcsLaneAdv:
+    """PCS Lane Advanced Statistics"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, lane_idx: int) -> None:
+
+        self.rx_skew = PL1AD_RX_SKEW(conn, module_id, port_id, lane_idx)
+        """Returns the current Rx relative skew of the PCS lane measured in bits.
+
+        :type: PL1AD_RX_SKEW
+        """
+
+        # self.tx_skew = PL1AD_TX_SKEW(conn, module_id, port_id, lane_idx)
+        # """Returns the current Tx relative skew of the PCS lane measured in bits.
+
+        # :type: PL1AD_TX_SKEW
+        # """
+
+
+        # self.rx_loa_since_last = PL1AD_RX_LOA_CNT(conn, module_id, port_id, lane_idx)
+        # """Returns the number of cumulated Loss of Alignment conditions on the PCS lane since last query
+
+        # :type: PL1AD_RX_LOA_CNT
+        # """
+
+        # self.tx_loa = PL1AD_TX_LOA(conn, module_id, port_id, lane_idx)
+        # """Sends a Loss of Alignment from the Tx lane immediately when called.
+        
+        # :type: PL1AD_TX_LOA
+        # """
+
+
+
+class HighBer:
+    """High Bit Error Rate (BER) Alarm"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.status = PL1AD_RX_HIBER(conn, module_id, port_id)
+        """Returns the current and the latched High BER status of the port.
+        
+        :type: PL1AD_RX_HIBER
+        """
+
+
+class HighSer:
+    """High Symbol Error Rate (SER) Alarm"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.status = PL1AD_RX_HISER(conn, module_id, port_id)
+        """Returns the current and the latched High SER status of the port.
+        
+        :type: PL1AD_RX_HISER
+        """
+
+        self.alarm = PL1AD_RX_HISER_ALARM(conn, module_id, port_id)
+        """High SER Alarm management.
+
+        :type: PL1AD_RX_HISER_ALARM
+        """
+
+        # self.tx_hi_ser = PL1AD_TX_HISER(conn, module_id, port_id)
+        # """Sends a High SER condition from the Tx port immediately when called.
+        
+        # :type: PL1AD_TX_HISER
+        # """
+
+        # self.state = PL1AD_RX_HISER_CTRL(conn, module_id, port_id)
+        # """Enable or disable High SER detection.
+        
+        # :type: PL1AD_RX_HISER_CTRL
+        # """
+
+class InvalidTranscodeBlock:
+    """Invalid Transcode Block (ITB) Management"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.rx_itb_since_last = PL1AD_RX_ITB_CNT(conn, module_id, port_id)
+        """Returns the number of cumulated Invalid 256b/257b Transcode Blocks since last query.
+        
+        :type: PL1AD_RX_ITB_CNT
+        """
+
+        self.tx_itb = PL1AD_TX_ITB(conn, module_id, port_id)
+        """Sends an Invalid 256b/257b Transcode Block from the Tx port immediately when called.
+        
+        :type: PL1AD_TX_ITB
+        """
+        
+
+
+class DegradedSer:
+    """Degraded Symbol Error Rate (SER) Management"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.threshold = PL1AD_RX_DEG_SER_THRESH(conn, module_id, port_id)
+        """Configures the thresholds for the Degraded SER Alarm.
+        
+        :type: PL1AD_RX_DEG_SER_THRESH
+        """
+
+        self.status = PL1AD_RX_DEG_SER(conn, module_id, port_id)
+        """The current and latched Degraded SER status of the port.
+        
+        :type: PL1AD_RX_DEG_SER
+        """
+
+        # self.state = PL1AD_RX_DEG_SER_STATE(conn, module_id, port_id)
+        # """Enable or disable Degraded SER detection.
+        
+        # :type: PL1AD_RX_DEG_SER_STATE
+        # """
+
+
+class ErrorCodeword:
+    """Erroneous Codeword (CW) Management"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.rx_err_cw_since_last = PL1AD_RX_ERR_CW_CNT(conn, module_id, port_id)
+        """Returns the number of cumulative erroneous 64b/66b codewords since last query.
+        
+        :type: PL1AD_RX_ERR_CW_CNT
+        """
+
+        self.tx_err_cw = PL1AD_TX_ERR_CW(conn, module_id, port_id)
+        """Sends an error 64b/66b codeword from the Tx port immediately when called.
+        
+        :type: PL1AD_TX_ERR_CW
+        """
+
+
+class PcsLayerAdv:
+    """Adv. Layer-1 - PCS layer configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", port: "FamilyFreya") -> None:
+        self._conn = conn
+        self.__port = port
+        module_id, port_id = port.kind
+
+        self.lane: Tuple["PcsLaneAdv", ...] = tuple(
+            PcsLaneAdv(self._conn, module_id, port_id, lane_idx=idx)
+            for idx in range(self.__port.info.capabilities.lane_count)
+        )  # TODO: need to fix, currently port.info.capabilities must be none because lanes are created before awaiting the port
+        """PCS Lane
+        
+        :type: Tuple[PcsLaneAdv, ...]
+        """
+
+        self.deg_ser = DegradedSer(conn, module_id, port_id)
+        """Degraded Symbol Error Rate (SER) Management
+
+        :type: DegradedSer
+        """
+
+        self.err_cw = ErrorCodeword(conn, module_id, port_id)
+        """Erroneous Codeword (CW) Management
+
+        :type: ErrorCodeword
+        """
+
+        self.hi_ber = HighBer(conn, module_id, port_id)
+        """High Bit Error Rate (BER)
+
+        :type: HighBer
+        """
+
+        self.hi_ser = HighSer(conn, module_id, port_id)
+        """High Symbol Error Rate (SER)
+
+        :type: HighSer
+        """
+
+        self.itb = InvalidTranscodeBlock(conn, module_id, port_id)
+        """Invalid Transcode Block (ITB) Management
+
+        :type: InvalidTranscodeBlock
+        """
+
+        self.rx_total_loa_since_last = PL1AD_RX_LOA_CNT(conn, module_id, port_id) # TODO: Suggestion for R106 GA: The name of the XMP command is preferred to be changed to PL1AD_RX_LOA_TOTAL_CNT 
+        """Returns the number of cumulated Loss of Alignment conditions since last query of the port.
+
+        :type: PL1AD_RX_LOA_CNT
+        """
+
+        self.rx_link_sync_loss_since_last = PL1AD_RX_LOSYNC_CNT(conn, module_id, port_id)
+        """Returns the number of cumulated Loss of Sync conditions since last query.
+
+        :type: PL1AD_RX_LOSYNC_CNT
+        """
+

xoa_driver/internals/hli/ports/port_l23/layer1_adv/rs_fault.py

@@ -0,0 +1,24 @@
+from typing import TYPE_CHECKING
+from xoa_driver.internals.commands import (
+    PL1AD_RX_LF_CNT,
+    PL1AD_RX_RF_CNT,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+
+
+class RsFault:
+    """RS Fault Management"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.rx_local_fault_since_last = PL1AD_RX_LF_CNT(conn, module_id, port_id)
+        """Returns the number of cumulated Local Fault conditions since last query.
+        
+        :type: PL1AD_RX_LF_CNT
+        """
+
+        self.rx_remote_fault_since_last = PL1AD_RX_RF_CNT(conn, module_id, port_id)
+        """Returns the number of cumulated Remote Fault conditions since last query.
+        
+        :type: PL1AD_RX_RF_CNT
+        """

xoa_driver/internals/hli/ports/port_l23/layer1_freya.py

@@ -72,10 +72,15 @@ class FreyaPcsLayer(PcsLayer):
 class Layer1:
     def __init__(self, conn: "itf.IConnection", port: "FamilyFreya") -> None:
         module_id, port_id = port.kind
+
         self.serdes: Tuple[SerDesFreya, ...] = tuple(
                 SerDesFreya(conn, module_id, port_id, serdes_xindex=idx)
                 for idx in range(port.info.capabilities.serdes_count)
                 )
+        """SerDes Lane
+        
+        :type: Tuple[SerDesFreya, ...]
+        """
         
         self.impairment = Impair(conn, module_id, port_id)
         """Impairment functions

xoa_driver/internals/hli/ports/port_l23/layer1_freya_adv.py

@@ -0,0 +1,61 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+    from xoa_driver.internals.hli.ports.port_l23.family_freya import FamilyFreya
+    
+from xoa_driver.internals.commands import (
+    PL1AD_RX_LOL,
+)
+
+from .layer1_adv.freq import FrequencyAdv
+from .layer1_adv.pcs_fec import PcsLayerAdv
+from .layer1_adv.rs_fault import *
+
+class SerdesAdv:
+    """Serdes Advanced Statistics"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_idx: int) -> None:
+
+        self.rx_cdr_lol_since_last = PL1AD_RX_LOL(conn, module_id, port_id, serdes_idx)
+        """Returns the current and the latched CDR Loss of Lock (LOL) status of the specified Serdes.
+
+        :type: PL1AD_RX_LOL
+        """
+
+
+class Layer1Adv:
+    def __init__(self, conn: "itf.IConnection", port: "FamilyFreya") -> None:
+        module_id, port_id = port.kind
+
+        self.serdes: Tuple["SerdesAdv", ...] = tuple(
+            SerdesAdv(conn, module_id, port_id, serdes_idx=idx)
+            for idx in range(port.info.capabilities.serdes_count)
+        ) 
+        """SerDes Lane
+        
+        :type: Tuple[SerdesAdv, ...]
+        """
+
+        self.freq = FrequencyAdv(conn, module_id, port_id)
+        """Frequency Management
+
+        :type: FrequencyAdv
+        """
+
+        self.rs_fault = RsFault(conn, module_id, port_id)
+        """RS Fault Management
+
+        :type: RsFault
+        """
+
+        self.pcs = PcsLayerAdv(conn, port)
+        """PCS configuration and status
+        """
+
+        
+
+
+        

xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py

@@ -45,7 +45,7 @@ class Transceiver:
         """
 
     def access_rw(self, page_address: int, register_address: int) -> "PX_RW":
-        """Access to register interface by the transceiver.
+        """R/W access (4 bytes) to register interface by the transceiver.
 
         :param page_address: page address
         :type page_address: int
@@ -64,7 +64,7 @@ class Transceiver:
         )
 
     def access_mii(self, register_address: int) -> "PX_MII":
-        """Access to the register interface supported by the media-independent interface (MII) transceiver.
+        """R/W access (2 bytes) to the register interface supported by MII transceiver.
 
         :param register_address: register address
         :type register_address: int
@@ -79,7 +79,7 @@ class Transceiver:
         )
 
     def access_rw_seq(self, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ":
-        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+        """Sequential R/W a number of bytes to the register interface.
 
         :param page_address: page address (0-255)
         :type page_address: int
@@ -100,7 +100,7 @@ class Transceiver:
         )
     
     def access_rw_seq_bank(self, bank_address: int, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ_BANK":
-        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+        """Sequential R/W a number of bytes to the register interface.
 
         :param bank_address: bank address (0-255)
         :type bank_address: int