tdl-xoa-driver 1.5.1__py3-none-any.whl → 1.6.1__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.1.dist-info}/METADATA +1 -1
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.1.dist-info}/RECORD +87 -88
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.1.dist-info}/licenses/LICENSE +1 -1
- xoa_driver/__init__.py +2 -2
- xoa_driver/enums.py +10 -10
- xoa_driver/functions/anlt.py +60 -78
- xoa_driver/functions/cli/testbed_config.py +1 -1
- xoa_driver/functions/cmis/_replies.py +4 -4
- xoa_driver/functions/mgmt.py +206 -250
- xoa_driver/functions/tools.py +11 -6
- xoa_driver/internals/commands/c_commands.py +59 -0
- xoa_driver/internals/commands/enums.py +101 -90
- xoa_driver/internals/commands/m4_commands.py +25 -0
- xoa_driver/internals/commands/m4e_commands.py +6 -0
- xoa_driver/internals/commands/m_commands.py +51 -1
- xoa_driver/internals/commands/p4_commands.py +63 -1
- xoa_driver/internals/commands/p4e_commands.py +9 -0
- xoa_driver/internals/commands/p4g_commands.py +139 -0
- xoa_driver/internals/commands/p_commands.py +455 -61
- xoa_driver/internals/commands/pc_commands.py +9 -0
- xoa_driver/internals/commands/pd_commands.py +11 -0
- xoa_driver/internals/commands/pe_commands.py +27 -0
- xoa_driver/internals/commands/pec_commands.py +9 -0
- xoa_driver/internals/commands/ped_commands.py +23 -0
- xoa_driver/internals/commands/pef_commands.py +43 -0
- xoa_driver/internals/commands/pf_commands.py +11 -0
- xoa_driver/internals/commands/pl1_commands.py +315 -48
- xoa_driver/internals/commands/pl_commands.py +8 -0
- xoa_driver/internals/commands/pm_commands.py +11 -0
- xoa_driver/internals/commands/pp_commands.py +84 -27
- xoa_driver/internals/commands/pr_commands.py +25 -0
- xoa_driver/internals/commands/ps_commands.py +47 -1
- xoa_driver/internals/commands/pt_commands.py +15 -0
- xoa_driver/internals/commands/px_commands.py +180 -136
- xoa_driver/internals/commands/subtypes.py +4 -3
- xoa_driver/internals/core/transporter/protocol/payload/base_struct.py +1 -1
- xoa_driver/internals/hli/indices/macsecscs/base_macsecsc.py +41 -3
- xoa_driver/internals/hli/modules/modules_l23/family_combi.py +0 -64
- xoa_driver/internals/hli/modules/modules_l23/family_edun.py +0 -2
- xoa_driver/internals/hli/modules/modules_l23/{family_g.py → family_loki.py} +29 -1
- xoa_driver/internals/hli/modules/modules_l23/family_odin.py +412 -0
- xoa_driver/internals/hli/modules/modules_l23/{family_l.py → family_thor.py} +44 -0
- xoa_driver/internals/hli/ports/port_l23/chimera/port_chimera.py +3 -3
- xoa_driver/internals/hli/ports/port_l23/family_edun.py +8 -43
- xoa_driver/internals/hli/ports/port_l23/{family_l1.py → family_freya.py} +9 -44
- xoa_driver/internals/hli/ports/port_l23/{family_g.py → family_loki.py} +32 -31
- xoa_driver/internals/hli/ports/port_l23/family_odin.py +225 -0
- xoa_driver/internals/hli/ports/port_l23/family_thor.py +67 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/anlt.py +512 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/brr.py +26 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/eye_diagram.py +71 -0
- xoa_driver/internals/hli/ports/port_l23/{pcs_pma_ijkl_chimera.py → layer1/impair.py} +7 -7
- xoa_driver/internals/hli/ports/port_l23/layer1/laser_power.py +28 -0
- xoa_driver/internals/hli/ports/port_l23/{family_e.py → layer1/lower_power.py} +1 -51
- xoa_driver/internals/hli/ports/port_l23/{freya_l1.py → layer1/medium.py} +38 -358
- xoa_driver/internals/hli/ports/port_l23/layer1/pcs_fec.py +219 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/pma.py +43 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/prbs.py +39 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/preamble.py +25 -0
- xoa_driver/internals/hli/ports/port_l23/{fault_jkl.py → layer1/rs_fault.py} +2 -2
- xoa_driver/internals/hli/ports/port_l23/layer1/siv.py +69 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_edun.py +103 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_freya.py +103 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_loki.py +74 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_thor.py +70 -0
- xoa_driver/internals/hli/ports/port_l23/sec/__init__.py +0 -0
- xoa_driver/internals/hli/ports/port_l23/sec/macsec.py +108 -0
- xoa_driver/internals/hli/ports/port_l23/tcvr/__init__.py +0 -0
- xoa_driver/internals/hli/ports/port_l23/{bases/port_transceiver.py → tcvr/cmis.py} +4 -118
- xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py +124 -0
- xoa_driver/internals/hli/ports/port_l23/trafficgen/__init__.py +0 -0
- xoa_driver/internals/hli/ports/port_l23/trafficgen/runt.py +32 -0
- xoa_driver/internals/hli/ports/port_l23/{bases/port_reception_statistics.py → trafficgen/rx_stats.py} +0 -21
- xoa_driver/internals/hli/ports/port_l23/{bases/port_l23.py → trafficgen/tgen.py} +31 -213
- xoa_driver/internals/hli/ports/port_l23/{bases/port_transmission_statistics.py → trafficgen/tx_stats.py} +2 -22
- xoa_driver/internals/hli/testers/l23_tester.py +1 -3
- xoa_driver/internals/utils/indices/_interfaces.py +18 -6
- xoa_driver/internals/utils/indices/index_manager.py +8 -2
- xoa_driver/internals/utils/managers/ports_manager.py +5 -2
- xoa_driver/misc.py +6 -6
- xoa_driver/modules.py +31 -47
- xoa_driver/ports.py +10 -29
- xoa_driver/internals/hli/modules/modules_l23/family_d.py +0 -75
- xoa_driver/internals/hli/modules/modules_l23/family_e.py +0 -85
- xoa_driver/internals/hli/modules/modules_l23/family_f.py +0 -145
- xoa_driver/internals/hli/modules/modules_l23/family_h.py +0 -40
- xoa_driver/internals/hli/modules/modules_l23/family_i.py +0 -25
- xoa_driver/internals/hli/modules/modules_l23/family_j.py +0 -25
- xoa_driver/internals/hli/modules/modules_l23/family_k.py +0 -39
- xoa_driver/internals/hli/modules/modules_l23/family_m.py +0 -25
- xoa_driver/internals/hli/modules/modules_l23/family_n.py +0 -40
- xoa_driver/internals/hli/ports/port_l23/bases/port_l23_genuine.py +0 -229
- xoa_driver/internals/hli/ports/port_l23/edun_l1.py +0 -181
- xoa_driver/internals/hli/ports/port_l23/family_combi.py +0 -37
- xoa_driver/internals/hli/ports/port_l23/family_d.py +0 -51
- xoa_driver/internals/hli/ports/port_l23/family_f.py +0 -151
- xoa_driver/internals/hli/ports/port_l23/family_h.py +0 -67
- xoa_driver/internals/hli/ports/port_l23/family_i.py +0 -84
- xoa_driver/internals/hli/ports/port_l23/family_j.py +0 -68
- xoa_driver/internals/hli/ports/port_l23/family_k.py +0 -73
- xoa_driver/internals/hli/ports/port_l23/family_l.py +0 -82
- xoa_driver/internals/hli/ports/port_l23/family_m.py +0 -29
- xoa_driver/internals/hli/ports/port_l23/pcs_pma_ghijkl.py +0 -369
- xoa_driver/internals/hli/ports/port_l23/pcs_pma_l.py +0 -78
- xoa_driver/internals/hli/ports/port_l23/port_l23ve.py +0 -101
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.1.dist-info}/WHEEL +0 -0
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.1.dist-info}/top_level.txt +0 -0
- /xoa_driver/internals/hli/modules/modules_l23/{family_l1.py → family_freya.py} +0 -0
- /xoa_driver/internals/hli/ports/port_l23/{bases → layer1}/__init__.py +0 -0
- /xoa_driver/internals/hli/ports/port_l23/{bases/port_capture.py → trafficgen/capture.py} +0 -0
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@@ -62,7 +62,7 @@ from xoa_driver.internals.state_storage import ports_state
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from xoa_driver.internals.hli.indices.length_term import LengthTermIdx
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from xoa_driver.internals.hli.indices.match_term import MatchTermIdx
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from .
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from .capture import PortCapture
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LengthTermIndices = idx_mgr.IndexManager[LengthTermIdx]
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MatchTermIndices = idx_mgr.IndexManager[MatchTermIdx]
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@@ -138,7 +138,7 @@ class TxConfiguration:
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"""
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class
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class TxRate:
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"""L23 port TX rate"""
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def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
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"""
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class MacControl:
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"""MAC control configuration
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"""
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def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
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self.address = P_MACADDRESS(conn, module_id, port_id)
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"""MAC address configuration. This attribute allows the user to configure the MAC address for the port.
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:type: P_MACADDRESS
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"""
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self.autotrain = P_AUTOTRAIN(conn, module_id, port_id)
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"""Interval between MAC auto training packets. This attribute allows the user to configure the interval at which MAC auto training packets are sent. Auto training packets are used to optimize the performance of the MAC layer and to ensure proper communication between devices.
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:type: P_AUTOTRAIN
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"""
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class Multicast:
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"""L23 port multicast configuration"""
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"""
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"""L23 port networking configuration"""
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class NetConfig:
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"""L23 port network interface configuration"""
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"""L23 port MAC address.
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"""L23 port MAC address and control.
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:type: P_IPV6ADDRESS
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"""L23 port IPv4
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"""L23 port IPv4 configuration.
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"""L23 port IPv6 configuration.
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class BasePortL23(base_port.BasePort[ports_state.PortL23LocalState]):
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"""L23 port layout which is relevant to all L23 ports."""
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"""L23 port capabilities ext.
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:type: Mix
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|
457
|
-
"""
|
|
458
|
-
|
|
459
|
-
self.latency_config = LatencyConfiguration(conn, module_id, port_id)
|
|
460
|
-
"""L23 port latency configuration.
|
|
461
|
-
|
|
462
|
-
self.latency_config = LatencyConfiguration(conn, module_id, port_id)
|
|
463
|
-
:type:
|
|
464
|
-
"""
|
|
465
|
-
|
|
466
|
-
self.rate = Rate(conn, module_id, port_id)
|
|
467
|
-
"""L23 port rate.
|
|
468
|
-
|
|
469
|
-
:type: Rate
|
|
470
|
-
"""
|
|
471
|
-
|
|
472
|
-
self.tx_config = TxConfiguration(conn, module_id, port_id)
|
|
473
|
-
"""L23 port TX configuration.
|
|
474
|
-
|
|
475
|
-
:type: TxConfiguration
|
|
476
|
-
"""
|
|
477
|
-
|
|
478
|
-
self.tx_single_pkt = TxSinglePacket(conn, module_id, port_id)
|
|
479
|
-
"""L23 port single-packet TX configuration.
|
|
480
|
-
|
|
481
|
-
:type: TxSinglePacket
|
|
482
|
-
"""
|
|
483
|
-
|
|
484
|
-
self.multicast = Multicast(conn, module_id, port_id)
|
|
485
|
-
"""L23 port multicast configuration.
|
|
486
|
-
|
|
487
|
-
:type: Multicast
|
|
488
|
-
"""
|
|
489
|
-
|
|
490
|
-
self.net_config = NetworkConfiguration(conn, module_id, port_id)
|
|
491
|
-
"""L23 port network configuration.
|
|
492
|
-
|
|
493
|
-
:type: NetworkConfiguration
|
|
494
|
-
"""
|
|
495
|
-
|
|
496
|
-
self.local_states = ports_state.PortL23LocalState()
|
|
497
|
-
"""L23 port local states.
|
|
498
|
-
|
|
499
|
-
:type: PortL23LocalState
|
|
500
|
-
"""
|
|
501
|
-
|
|
502
|
-
self.length_terms: LengthTermIndices = idx_mgr.IndexManager(
|
|
503
|
-
conn,
|
|
504
|
-
LengthTermIdx,
|
|
505
|
-
module_id,
|
|
506
|
-
port_id
|
|
507
|
-
)
|
|
508
|
-
"""L23 port's length term index manager.
|
|
509
|
-
|
|
510
|
-
:type: LengthTermIndices
|
|
511
|
-
"""
|
|
512
|
-
|
|
513
|
-
self.match_terms: MatchTermIndices = idx_mgr.IndexManager(
|
|
514
|
-
conn,
|
|
515
|
-
MatchTermIdx,
|
|
516
|
-
module_id,
|
|
517
|
-
port_id
|
|
518
|
-
)
|
|
519
|
-
"""L23 port's match term index manager.
|
|
520
|
-
|
|
521
|
-
:type: MatchTermIndices
|
|
522
|
-
"""
|
|
523
|
-
|
|
524
|
-
self.used_tpld_ids = P_USED_TPLDID(conn, module_id, port_id)
|
|
525
|
-
"""TG port's used TPLD IDs.
|
|
526
|
-
|
|
527
|
-
:type: P_USED_TPLDID
|
|
528
|
-
"""
|
|
529
|
-
|
|
530
|
-
on_speed_change = functools.partialmethod(utils.on_event, P_SPEED)
|
|
531
|
-
"""Register a callback to the event that the port's speed changes."""
|
|
532
|
-
|
|
533
|
-
on_traffic_change = functools.partialmethod(utils.on_event, P_TRAFFIC)
|
|
534
|
-
"""Register a callback to the event that the port's traffic status changes."""
|
|
@@ -14,13 +14,11 @@ from xoa_driver.internals.commands import (
|
|
|
14
14
|
PT_TOTALEXT,
|
|
15
15
|
PT_NOTPLDEXT,
|
|
16
16
|
PT_STREAMEXT,
|
|
17
|
-
P_MACSEC_TX_STATS,
|
|
18
|
-
P_MACSEC_TX_CLEAR,
|
|
19
17
|
)
|
|
20
18
|
|
|
21
19
|
# region All Ports
|
|
22
20
|
|
|
23
|
-
class
|
|
21
|
+
class PortTxStats:
|
|
24
22
|
"""L23 port TX statistics"""
|
|
25
23
|
|
|
26
24
|
def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
|
|
@@ -101,31 +99,13 @@ class PortTransmissionStatistics:
|
|
|
101
99
|
|
|
102
100
|
# region Genuine Ports
|
|
103
101
|
|
|
104
|
-
class MACSecTxStats:
|
|
105
|
-
"""MACSec TX SC Statistics"""
|
|
106
|
-
def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
|
|
107
|
-
|
|
108
|
-
self.total = P_MACSEC_TX_STATS(conn, module_id, port_id)
|
|
109
|
-
"""Port's total MACsec TX statistics
|
|
110
|
-
|
|
111
|
-
:type: P_MACSEC_TX_STATS
|
|
112
|
-
"""
|
|
113
102
|
|
|
114
|
-
self.clear = P_MACSEC_TX_CLEAR(conn, module_id, port_id)
|
|
115
|
-
"""Clear Port's MACsec TX statistics
|
|
116
103
|
|
|
117
|
-
|
|
118
|
-
"""
|
|
119
|
-
|
|
120
|
-
|
|
121
|
-
class GenuinePortTransmissionStatistics(PortTransmissionStatistics):
|
|
104
|
+
class GenuinePortTransmissionStatistics(PortTxStats):
|
|
122
105
|
"""L23 port RX statistics."""
|
|
123
106
|
|
|
124
107
|
def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
|
|
125
108
|
super().__init__(conn, module_id, port_id)
|
|
126
109
|
|
|
127
|
-
self.macsec = MACSecTxStats(conn, module_id, port_id)
|
|
128
|
-
"""L23 port's MACsec TX statistics.
|
|
129
|
-
"""
|
|
130
110
|
|
|
131
111
|
# endregion
|
|
@@ -57,9 +57,7 @@ def get_module_type(revision: str) -> Type:
|
|
|
57
57
|
|
|
58
58
|
class L23Tester(BaseTester["testers_state.GenuineTesterLocalState"]):
|
|
59
59
|
"""
|
|
60
|
-
|
|
61
|
-
It is essentially an extended :class:`BaseTester`.
|
|
62
|
-
|
|
60
|
+
Create an instanace to connect to a Xena chassis.
|
|
63
61
|
|
|
64
62
|
:param host: tester's address/hostname
|
|
65
63
|
:type host: str
|
|
@@ -1,18 +1,19 @@
|
|
|
1
1
|
from typing import (
|
|
2
2
|
Protocol,
|
|
3
3
|
List,
|
|
4
|
-
|
|
4
|
+
TypeVar,
|
|
5
|
+
Self,
|
|
5
6
|
TYPE_CHECKING,
|
|
6
7
|
)
|
|
7
8
|
|
|
8
9
|
if TYPE_CHECKING:
|
|
9
10
|
from xoa_driver.internals.core import interfaces as itf
|
|
10
|
-
from .. import kind
|
|
11
|
-
from . import observer
|
|
11
|
+
from .. import kind as kind_module
|
|
12
|
+
from . import observer as idx_obs
|
|
12
13
|
|
|
13
14
|
|
|
14
15
|
class IIndexType(Protocol):
|
|
15
|
-
def __init__(self, conn: "itf.IConnection", kind: "
|
|
16
|
+
def __init__(self, conn: "itf.IConnection", kind: "kind_module.IndicesKind", observer: "idx_obs.IndicesObserver") -> None: ... # noqa: E704
|
|
16
17
|
|
|
17
18
|
async def delete(self) -> None: ... # noqa: E704
|
|
18
19
|
|
|
@@ -20,7 +21,18 @@ class IIndexType(Protocol):
|
|
|
20
21
|
def idx(self) -> int: ... # noqa: E704
|
|
21
22
|
|
|
22
23
|
@classmethod
|
|
23
|
-
async def _fetch(
|
|
24
|
+
async def _fetch(
|
|
25
|
+
cls,
|
|
26
|
+
conn: "itf.IConnection",
|
|
27
|
+
module_id: int,
|
|
28
|
+
port_id: int) -> List[int]: ... # noqa: E704
|
|
24
29
|
|
|
25
30
|
@classmethod
|
|
26
|
-
async def _new(
|
|
31
|
+
async def _new(
|
|
32
|
+
cls,
|
|
33
|
+
conn: "itf.IConnection",
|
|
34
|
+
kind: "kind_module.IndicesKind",
|
|
35
|
+
observer: "idx_obs.IndicesObserver"
|
|
36
|
+
) -> Self: ... # noqa: E704
|
|
37
|
+
|
|
38
|
+
IT = TypeVar("IT", bound=IIndexType)
|
|
@@ -60,7 +60,13 @@ class IndexManager(Generic[IT]):
|
|
|
60
60
|
return self._indices[key]
|
|
61
61
|
|
|
62
62
|
def obtain_multiple(self, *keys: int):
|
|
63
|
-
"""Obtain multiple
|
|
63
|
+
"""Obtain multiple index objects
|
|
64
|
+
|
|
65
|
+
:param keys: Indices of the desired index objects
|
|
66
|
+
:type keys: int
|
|
67
|
+
:return: Tuple of index objects corresponding to the provided keys
|
|
68
|
+
:rtype: tuple[IT, ...]
|
|
69
|
+
"""
|
|
64
70
|
return tuple(self._indices[k] for k in keys)
|
|
65
71
|
|
|
66
72
|
def __detect_empty_idx_slot(self) -> int:
|
|
@@ -74,7 +80,7 @@ class IndexManager(Generic[IT]):
|
|
|
74
80
|
]
|
|
75
81
|
return min(empties) if empties else len(existing_indices)
|
|
76
82
|
|
|
77
|
-
def __remove_from_slot(self, index_inst:
|
|
83
|
+
def __remove_from_slot(self, index_inst: IT) -> None:
|
|
78
84
|
# throws ValueError if element is not exists in list of indices
|
|
79
85
|
self._indices.remove(index_inst)
|
|
80
86
|
|
|
@@ -111,6 +111,9 @@ class PortsCombiManager(PortBaseManager[PT]):
|
|
|
111
111
|
for port_id in range(self._ports_count)
|
|
112
112
|
)
|
|
113
113
|
ports = await asyncio.gather(*coros)
|
|
114
|
-
self._items =
|
|
115
|
-
|
|
114
|
+
self._items = cast(
|
|
115
|
+
OrderedDict[int, PT],
|
|
116
|
+
OrderedDict(
|
|
117
|
+
(port.kind.port_id, port) for port in ports
|
|
118
|
+
)
|
|
116
119
|
)
|
xoa_driver/misc.py
CHANGED
|
@@ -5,9 +5,9 @@
|
|
|
5
5
|
from .internals.core.token import Token
|
|
6
6
|
from .internals.core.transporter.protocol.payload.types import Hex
|
|
7
7
|
from .internals.commands.subtypes import (
|
|
8
|
-
|
|
9
|
-
|
|
10
|
-
|
|
8
|
+
ArpEntry,
|
|
9
|
+
NdpEntry,
|
|
10
|
+
DhcpEntry,
|
|
11
11
|
GroupAddressElem,
|
|
12
12
|
VlanTag,
|
|
13
13
|
QueueStatsElem,
|
|
@@ -31,9 +31,9 @@ from xoa_driver.internals.hli.indices.macsecscs.genuine_macsecsc import GenuineM
|
|
|
31
31
|
__all__ = (
|
|
32
32
|
"Token",
|
|
33
33
|
"Hex",
|
|
34
|
-
"
|
|
35
|
-
"
|
|
36
|
-
"
|
|
34
|
+
"ArpEntry",
|
|
35
|
+
"NdpEntry",
|
|
36
|
+
"DhcpEntry",
|
|
37
37
|
"GroupAddressElem",
|
|
38
38
|
"VlanTag",
|
|
39
39
|
"QueueStatsElem",
|
xoa_driver/modules.py
CHANGED
|
@@ -1,21 +1,26 @@
|
|
|
1
1
|
#: All available test module types.
|
|
2
2
|
"""Xena test module types."""
|
|
3
|
-
|
|
3
|
+
from typing import Union
|
|
4
4
|
from .internals.hli.modules.modules_l23.module_l23_base import ModuleL23
|
|
5
|
-
from .internals.hli.modules.
|
|
5
|
+
from .internals.hli.modules.module_l23ve import ModuleL23VE
|
|
6
|
+
from .internals.hli.modules.module_chimera import (
|
|
7
|
+
ModuleChimera,
|
|
8
|
+
MChi100G5S2P,
|
|
9
|
+
MChi100G5S2P_b,
|
|
10
|
+
MChi40G2S2P,
|
|
11
|
+
)
|
|
12
|
+
from .internals.hli.modules.module_l47 import ModuleL47
|
|
13
|
+
from .internals.hli.modules.module_l47ve import ModuleL47VE
|
|
14
|
+
from .internals.hli.modules.modules_l23.family_odin import (
|
|
6
15
|
MOdin1G3S2PT,
|
|
7
16
|
MOdin1G3S6P,
|
|
8
17
|
MOdin1G3S6P_b,
|
|
9
18
|
MOdin1G3S6PE,
|
|
10
|
-
)
|
|
11
|
-
from .internals.hli.modules.modules_l23.family_e import (
|
|
12
19
|
MOdin5G4S6PCU,
|
|
13
20
|
MOdin10G3S2PCU,
|
|
14
21
|
MOdin10G3S6PCU,
|
|
15
22
|
MOdin10G5S6PCU,
|
|
16
23
|
MOdin10G5S6PCU_b,
|
|
17
|
-
)
|
|
18
|
-
from .internals.hli.modules.modules_l23.family_f import (
|
|
19
24
|
MOdin10G1S2P,
|
|
20
25
|
MOdin10G1S2P_b,
|
|
21
26
|
MOdin10G1S2P_c,
|
|
@@ -25,31 +30,32 @@ from .internals.hli.modules.modules_l23.family_f import (
|
|
|
25
30
|
MOdin10G1S6P_b,
|
|
26
31
|
MOdin10G1S12P,
|
|
27
32
|
MOdin10G6S6P_a,
|
|
33
|
+
MOdin100G3S1P,
|
|
34
|
+
MOdin1G3S6PT1RJ45,
|
|
35
|
+
MOdin10G4S2PCombi,
|
|
36
|
+
MOdin10G4S2PCombi_b,
|
|
37
|
+
MOdin40G2S2P,
|
|
38
|
+
MOdin40G2S2PB,
|
|
28
39
|
)
|
|
29
|
-
from .internals.hli.modules.modules_l23.
|
|
40
|
+
from .internals.hli.modules.modules_l23.family_loki import (
|
|
30
41
|
MLoki100G3S1P,
|
|
31
42
|
MLoki100G3S1P_b,
|
|
32
43
|
MLoki100G3S1PSE,
|
|
33
44
|
MLoki100G3S1PB,
|
|
34
45
|
MLoki100G3S1PB_b,
|
|
35
46
|
MLoki100G5S4P_a,
|
|
36
|
-
)
|
|
37
|
-
from .internals.hli.modules.modules_l23.family_h import (
|
|
38
47
|
MLoki100G5S1P,
|
|
39
|
-
|
|
48
|
+
MLoki100G5S2P,
|
|
40
49
|
)
|
|
41
|
-
from .internals.hli.modules.modules_l23.
|
|
42
|
-
|
|
43
|
-
from .internals.hli.modules.modules_l23.family_k import (
|
|
50
|
+
from .internals.hli.modules.modules_l23.family_thor import (
|
|
51
|
+
MThor100G5S4P,
|
|
44
52
|
MThor400G7S1P,
|
|
45
53
|
MThor400G7S1PLE,
|
|
46
|
-
)
|
|
47
|
-
from .internals.hli.modules.modules_l23.family_l import (
|
|
48
54
|
MThor400G7S1P_b,
|
|
49
55
|
MThor400G7S1P_c,
|
|
50
56
|
MThor400G7S1P_d,
|
|
51
57
|
)
|
|
52
|
-
from .internals.hli.modules.modules_l23.
|
|
58
|
+
from .internals.hli.modules.modules_l23.family_freya import (
|
|
53
59
|
MFreya800G1S1P_a,
|
|
54
60
|
MFreya800G1S1P_b,
|
|
55
61
|
MFreya800G1S1POSFP_a,
|
|
@@ -99,33 +105,11 @@ from .internals.hli.modules.modules_l23.family_l1 import (
|
|
|
99
105
|
MFreya800G4S1POSFP_e_g2,
|
|
100
106
|
MFreya800G4S1POSFP_f_g2,
|
|
101
107
|
)
|
|
102
|
-
from .internals.hli.modules.modules_l23.family_m import MOdin1G3S6PT1RJ45
|
|
103
|
-
from .internals.hli.modules.modules_l23.family_n import (
|
|
104
|
-
MOdin40G2S2P,
|
|
105
|
-
MOdin40G2S2PB,
|
|
106
|
-
)
|
|
107
|
-
from .internals.hli.modules.modules_l23.family_combi import (
|
|
108
|
-
MOdin10G4S2PCombi,
|
|
109
|
-
MOdin10G4S2PCombi_b,
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110
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)
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111
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-
from .internals.hli.modules.module_l23ve import ModuleL23VE
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112
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-
from .internals.hli.modules.module_chimera import (
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113
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ModuleChimera,
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114
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MChi100G5S2P,
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115
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MChi100G5S2P_b,
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116
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MChi40G2S2P,
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117
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)
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118
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from .internals.hli.modules.module_l47 import ModuleL47
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119
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from .internals.hli.modules.module_l47ve import ModuleL47VE
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120
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-
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121
108
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from .internals.hli.modules.modules_l23.family_edun import (
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122
109
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MEdun800G3S1PSMPX_a,
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123
110
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MEdun1600G4S1POSFP_a
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124
111
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)
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125
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-
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126
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-
import typing
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127
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-
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128
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-
Z10OdinModule = typing.Union[
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112
|
+
Z10OdinModule = Union[
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129
113
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MOdin1G3S2PT,
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130
114
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MOdin1G3S6P,
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131
115
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MOdin1G3S6P_b,
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@@ -152,7 +136,7 @@ Z10OdinModule = typing.Union[
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152
136
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MOdin100G3S1P,
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153
137
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]
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154
138
|
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155
|
-
Z100LokiModule =
|
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139
|
+
Z100LokiModule = Union[
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156
140
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MLoki100G3S1P,
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157
141
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MLoki100G3S1P_b,
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158
142
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MLoki100G3S1PSE,
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|
@@ -163,7 +147,7 @@ Z100LokiModule = typing.Union[
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163
147
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MLoki100G5S4P_a,
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164
148
|
]
|
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165
149
|
|
|
166
|
-
Z400ThorModule =
|
|
150
|
+
Z400ThorModule = Union[
|
|
167
151
|
MThor100G5S4P,
|
|
168
152
|
MThor400G7S1P,
|
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169
153
|
MThor400G7S1PLE,
|
|
@@ -172,7 +156,7 @@ Z400ThorModule = typing.Union[
|
|
|
172
156
|
MThor400G7S1P_d,
|
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173
157
|
]
|
|
174
158
|
|
|
175
|
-
Z800FreyaModule =
|
|
159
|
+
Z800FreyaModule = Union[
|
|
176
160
|
MFreya800G1S1P_a,
|
|
177
161
|
MFreya800G1S1P_b,
|
|
178
162
|
MFreya800G1S1POSFP_a,
|
|
@@ -223,25 +207,25 @@ Z800FreyaModule = typing.Union[
|
|
|
223
207
|
MFreya800G4S1POSFP_f_g2,
|
|
224
208
|
]
|
|
225
209
|
|
|
226
|
-
Z1600EdunModule =
|
|
210
|
+
Z1600EdunModule = Union[
|
|
227
211
|
MEdun800G3S1PSMPX_a,
|
|
228
212
|
MEdun1600G4S1POSFP_a
|
|
229
213
|
]
|
|
230
214
|
|
|
231
|
-
E100ChimeraModule =
|
|
215
|
+
E100ChimeraModule = Union[
|
|
232
216
|
ModuleChimera,
|
|
233
217
|
MChi100G5S2P,
|
|
234
218
|
MChi100G5S2P_b,
|
|
235
219
|
MChi40G2S2P,
|
|
236
220
|
]
|
|
237
221
|
|
|
238
|
-
LegacyModule =
|
|
222
|
+
LegacyModule = Union[
|
|
239
223
|
ModuleL23VE,
|
|
240
224
|
ModuleL47,
|
|
241
225
|
ModuleL47VE,
|
|
242
226
|
]
|
|
243
227
|
|
|
244
|
-
GenericL23Module =
|
|
228
|
+
GenericL23Module = Union[
|
|
245
229
|
"MOdin1G3S2PT",
|
|
246
230
|
"MOdin1G3S6P",
|
|
247
231
|
"MOdin1G3S6P_b",
|
|
@@ -336,7 +320,7 @@ GenericL23Module = typing.Union[
|
|
|
336
320
|
"MEdun1600G4S1POSFP_a",
|
|
337
321
|
]
|
|
338
322
|
|
|
339
|
-
GenericAnyModule =
|
|
323
|
+
GenericAnyModule = Union[
|
|
340
324
|
GenericL23Module,
|
|
341
325
|
|
|
342
326
|
"ModuleL23VE",
|