tdl-xoa-driver 1.5.1__py3-none-any.whl → 1.6.0__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.0.dist-info}/METADATA +1 -1
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.0.dist-info}/RECORD +89 -88
- xoa_driver/__init__.py +2 -2
- xoa_driver/enums.py +10 -10
- xoa_driver/functions/anlt.py +60 -78
- xoa_driver/functions/cli/testbed_config.py +1 -1
- xoa_driver/functions/cmis/_replies.py +4 -4
- xoa_driver/functions/mgmt.py +206 -250
- xoa_driver/functions/tools.py +11 -6
- xoa_driver/internals/commands/c_commands.py +59 -0
- xoa_driver/internals/commands/enums.py +101 -90
- xoa_driver/internals/commands/m4_commands.py +25 -0
- xoa_driver/internals/commands/m4e_commands.py +6 -0
- xoa_driver/internals/commands/m_commands.py +51 -1
- xoa_driver/internals/commands/p4_commands.py +63 -1
- xoa_driver/internals/commands/p4e_commands.py +9 -0
- xoa_driver/internals/commands/p4g_commands.py +139 -0
- xoa_driver/internals/commands/p_commands.py +455 -61
- xoa_driver/internals/commands/pc_commands.py +9 -0
- xoa_driver/internals/commands/pd_commands.py +11 -0
- xoa_driver/internals/commands/pe_commands.py +27 -0
- xoa_driver/internals/commands/pec_commands.py +9 -0
- xoa_driver/internals/commands/ped_commands.py +23 -0
- xoa_driver/internals/commands/pef_commands.py +43 -0
- xoa_driver/internals/commands/pf_commands.py +11 -0
- xoa_driver/internals/commands/pl1_commands.py +315 -48
- xoa_driver/internals/commands/pl_commands.py +8 -0
- xoa_driver/internals/commands/pm_commands.py +11 -0
- xoa_driver/internals/commands/pp_commands.py +84 -27
- xoa_driver/internals/commands/pr_commands.py +25 -0
- xoa_driver/internals/commands/ps_commands.py +47 -1
- xoa_driver/internals/commands/pt_commands.py +15 -0
- xoa_driver/internals/commands/px_commands.py +180 -136
- xoa_driver/internals/commands/subtypes.py +4 -3
- xoa_driver/internals/core/transporter/protocol/payload/base_struct.py +1 -1
- xoa_driver/internals/hli/indices/macsecscs/base_macsecsc.py +41 -3
- xoa_driver/internals/hli/modules/modules_l23/family_combi.py +0 -64
- xoa_driver/internals/hli/modules/modules_l23/family_edun.py +0 -2
- xoa_driver/internals/hli/modules/modules_l23/{family_g.py → family_loki.py} +29 -1
- xoa_driver/internals/hli/modules/modules_l23/family_odin.py +412 -0
- xoa_driver/internals/hli/modules/modules_l23/{family_l.py → family_thor.py} +44 -0
- xoa_driver/internals/hli/ports/port_l23/chimera/port_chimera.py +3 -3
- xoa_driver/internals/hli/ports/port_l23/family_edun.py +9 -44
- xoa_driver/internals/hli/ports/port_l23/{family_l1.py → family_freya.py} +10 -45
- xoa_driver/internals/hli/ports/port_l23/{family_g.py → family_loki.py} +33 -32
- xoa_driver/internals/hli/ports/port_l23/family_odin.py +225 -0
- xoa_driver/internals/hli/ports/port_l23/family_thor.py +67 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/anlt.py +512 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/brr.py +26 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/eye_diagram.py +71 -0
- xoa_driver/internals/hli/ports/port_l23/{pcs_pma_ijkl_chimera.py → layer1/impair.py} +7 -7
- xoa_driver/internals/hli/ports/port_l23/layer1/laser_power.py +28 -0
- xoa_driver/internals/hli/ports/port_l23/{family_e.py → layer1/lower_power.py} +1 -51
- xoa_driver/internals/hli/ports/port_l23/{freya_l1.py → layer1/medium.py} +38 -358
- xoa_driver/internals/hli/ports/port_l23/layer1/pcs_fec.py +219 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/pma.py +43 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/prbs.py +39 -0
- xoa_driver/internals/hli/ports/port_l23/layer1/preamble.py +25 -0
- xoa_driver/internals/hli/ports/port_l23/{fault_jkl.py → layer1/rs_fault.py} +2 -2
- xoa_driver/internals/hli/ports/port_l23/layer1/siv.py +69 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_edun.py +103 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_freya.py +103 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_loki.py +74 -0
- xoa_driver/internals/hli/ports/port_l23/layer1_thor.py +70 -0
- xoa_driver/internals/hli/ports/port_l23/port_l23ve.py +4 -4
- xoa_driver/internals/hli/ports/port_l23/sec/__init__.py +0 -0
- xoa_driver/internals/hli/ports/port_l23/sec/macsec.py +108 -0
- xoa_driver/internals/hli/ports/port_l23/tcvr/__init__.py +0 -0
- xoa_driver/internals/hli/ports/port_l23/{bases/port_transceiver.py → tcvr/cmis.py} +4 -118
- xoa_driver/internals/hli/ports/port_l23/tcvr/transceiver.py +124 -0
- xoa_driver/internals/hli/ports/port_l23/trafficgen/__init__.py +0 -0
- xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_l23.py +1 -1
- xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_l23_genuine.py +5 -45
- xoa_driver/internals/hli/ports/port_l23/{bases/port_reception_statistics.py → trafficgen/port_rx_stats.py} +0 -21
- xoa_driver/internals/hli/ports/port_l23/{bases/port_transmission_statistics.py → trafficgen/port_tx_stats.py} +2 -22
- xoa_driver/internals/hli/ports/port_l23/trafficgen/runt.py +32 -0
- xoa_driver/internals/hli/testers/l23_tester.py +1 -3
- xoa_driver/internals/utils/indices/_interfaces.py +18 -6
- xoa_driver/internals/utils/indices/index_manager.py +8 -2
- xoa_driver/internals/utils/managers/ports_manager.py +5 -2
- xoa_driver/misc.py +6 -6
- xoa_driver/modules.py +31 -47
- xoa_driver/ports.py +10 -29
- xoa_driver/internals/hli/modules/modules_l23/family_d.py +0 -75
- xoa_driver/internals/hli/modules/modules_l23/family_e.py +0 -85
- xoa_driver/internals/hli/modules/modules_l23/family_f.py +0 -145
- xoa_driver/internals/hli/modules/modules_l23/family_h.py +0 -40
- xoa_driver/internals/hli/modules/modules_l23/family_i.py +0 -25
- xoa_driver/internals/hli/modules/modules_l23/family_j.py +0 -25
- xoa_driver/internals/hli/modules/modules_l23/family_k.py +0 -39
- xoa_driver/internals/hli/modules/modules_l23/family_m.py +0 -25
- xoa_driver/internals/hli/modules/modules_l23/family_n.py +0 -40
- xoa_driver/internals/hli/ports/port_l23/edun_l1.py +0 -181
- xoa_driver/internals/hli/ports/port_l23/family_combi.py +0 -37
- xoa_driver/internals/hli/ports/port_l23/family_d.py +0 -51
- xoa_driver/internals/hli/ports/port_l23/family_f.py +0 -151
- xoa_driver/internals/hli/ports/port_l23/family_h.py +0 -67
- xoa_driver/internals/hli/ports/port_l23/family_i.py +0 -84
- xoa_driver/internals/hli/ports/port_l23/family_j.py +0 -68
- xoa_driver/internals/hli/ports/port_l23/family_k.py +0 -73
- xoa_driver/internals/hli/ports/port_l23/family_l.py +0 -82
- xoa_driver/internals/hli/ports/port_l23/family_m.py +0 -29
- xoa_driver/internals/hli/ports/port_l23/pcs_pma_ghijkl.py +0 -369
- xoa_driver/internals/hli/ports/port_l23/pcs_pma_l.py +0 -78
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.0.dist-info}/WHEEL +0 -0
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.0.dist-info}/licenses/LICENSE +0 -0
- {tdl_xoa_driver-1.5.1.dist-info → tdl_xoa_driver-1.6.0.dist-info}/top_level.txt +0 -0
- /xoa_driver/internals/hli/modules/modules_l23/{family_l1.py → family_freya.py} +0 -0
- /xoa_driver/internals/hli/ports/port_l23/{bases → layer1}/__init__.py +0 -0
- /xoa_driver/internals/hli/ports/port_l23/{bases → trafficgen}/port_capture.py +0 -0
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"""Port Advanced Layer 1 Commands"""
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from __future__ import annotations
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from dataclasses import dataclass
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import typing
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OnOff,
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FreyaLinkTrainingMode,
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FreyaAutonegMode,
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AutoNegTecAbility,
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AutoNegFECAbility,
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AutoNegPauseAbility,
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AutoNegMode,
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AutoNegStatus,
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AutoNegTechAbilityHCDStatus,
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FECMode,
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PauseMode,
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FreyaOutOfSyncPreset,
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Layer1Control,
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FreyaPCSVariant,
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AutoNegTecAbilityHCD,
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@dataclass
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class PL1_AUTONEGINFO:
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"""
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Get
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Get advanced auto-negotiation statistics. Statistics are split into a number of pages.
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code: typing.ClassVar[int] = 385
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def get(self) -> Token[GetDataAttr]:
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"""Get the lower and the upper bound of transmit equalizer (native value) of the serdes, and how the serdes responds to an increment/decrement request when either bound is reached.
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:return: lower and upper bound of transmit equalizer (native value) and response mode
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:rtype: PL1_LT_PHYTXEQ_RANGE.GetDataAttr
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"""
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"""Set the lower and the upper bound of transmit equalizer (native value) of the serdes, and how the serdes responds to an increment/decrement request when either bound is reached.
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"""Set the lower and the upper bound of transmit equalizer (native value) of the serdes, and how the serdes responds to an increment/decrement request when either bound is reached.
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:param response: byte, the response when either of the bounds is triggered. Default is AUTO.
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"""a set of 16 bit signed 2-complement sample values. With present hardware, the range of each sample is -64..63. In CLI scripting, each sample value is represented as two bytes, msb first."""
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+
:type response: FreyaPresetResponse
|
|
890
|
+
:param pre3: The pre3 tap value, negative, scaled by 1E3.
|
|
891
|
+
:type pre3: int
|
|
892
|
+
:param pre2: The pre2 tap value, positive, scaled by 1E3.
|
|
893
|
+
:type pre2: int
|
|
894
|
+
:param pre: The pre tap value, negative, scaled by 1E3.
|
|
895
|
+
:type pre: int
|
|
896
|
+
:param main: The main tap value, positive, scaled by 1E3.
|
|
897
|
+
:type main: int
|
|
898
|
+
:param post: The post tap value, negative, scaled by 1E3.
|
|
899
|
+
:type post: int
|
|
900
|
+
"""
|
|
826
901
|
return Token(
|
|
827
902
|
self._connection,
|
|
828
903
|
build_set_request(self, module=self._module, port=self._port, indices=[self._serdes_xindex, self._preset_xindex], response=response, pre3=pre3, pre2=pre2, pre=pre, main=main, post=post))
|
|
@@ -838,14 +913,15 @@ class PL1_PHYTXEQ_LEVEL:
|
|
|
838
913
|
|
|
839
914
|
- **Regular Freya**: Original fixed format [pre3, pre2, pre, main, post]
|
|
840
915
|
- **Loki-4P and H-Freya/Edun**: Variable number in N*pre, main, M*post layout
|
|
841
|
-
|
|
916
|
+
|
|
917
|
+
``[pre_n, pre_n-1, ..., pre_1, main, post_1, post_2, ..., post_m]``
|
|
842
918
|
|
|
843
|
-
|
|
919
|
+
Query port capabilities for ``numtxeqtaps`` and ``numtxeqpretaps`` to determine
|
|
844
920
|
the number of taps and layout.
|
|
845
921
|
|
|
846
922
|
.. note::
|
|
847
923
|
|
|
848
|
-
PL1_PHYTXEQ
|
|
924
|
+
``PL1_PHYTXEQ``, ``PL1_PHYTXEQ_LEVEL``, and ``PL1_PHYTXEQ_COEFF`` facilitate the configuration and retrieval of TX tap values, each offering a unique perspective. Modifications made with any of these parameters will result in updates to the read results across all of them.
|
|
849
925
|
|
|
850
926
|
"""
|
|
851
927
|
|
|
@@ -911,7 +987,8 @@ class PL1_PHYTXEQ_COEFF:
|
|
|
911
987
|
|
|
912
988
|
- **Regular Freya**: Original fixed format [pre3, pre2, pre, main, post]
|
|
913
989
|
- **Loki-4P and H-Freya/Edun**: Variable number in N*pre, main, M*post layout
|
|
914
|
-
|
|
990
|
+
|
|
991
|
+
``[pre_n, pre_n-1, ..., pre_1, main, post_1, post_2, ..., post_m]``
|
|
915
992
|
|
|
916
993
|
Use P_CAPABILITIES to query ``numtxeqtaps`` and ``numtxeqpretaps`` to determine
|
|
917
994
|
the number of taps and layout.
|
|
@@ -922,12 +999,12 @@ class PL1_PHYTXEQ_COEFF:
|
|
|
922
999
|
|
|
923
1000
|
The following rules apply:
|
|
924
1001
|
|
|
925
|
-
* 0.5 approx.
|
|
926
|
-
* -0.4 approx
|
|
927
|
-
* -0.4 approx
|
|
928
|
-
* 0
|
|
929
|
-
* -0.25 approx
|
|
930
|
-
* The sum of the absolute value of each coefficients must be
|
|
1002
|
+
* 0.5 approx. <= main <= 1
|
|
1003
|
+
* -0.4 approx <= post <= 0
|
|
1004
|
+
* -0.4 approx <= pre <= 0
|
|
1005
|
+
* 0 <= pre2 <= 0.25 approx.
|
|
1006
|
+
* -0.25 approx <= pre3 <= 0
|
|
1007
|
+
* The sum of the absolute value of each coefficients must be <= 1.
|
|
931
1008
|
* A sum of 1 corresponds to a TX output voltage swing of 1000 mVpp approximately.
|
|
932
1009
|
|
|
933
1010
|
"""
|
|
@@ -1000,25 +1077,70 @@ class PL1_AUTONEG_STATUS:
|
|
|
1000
1077
|
|
|
1001
1078
|
class GetDataAttr(ResponseBodyStruct):
|
|
1002
1079
|
mode: AutoNegMode = field(XmpInt())
|
|
1003
|
-
"""Autoneg mode
|
|
1080
|
+
"""Autoneg mode
|
|
1081
|
+
|
|
1082
|
+
:type mode: AutoNegMode
|
|
1083
|
+
"""
|
|
1004
1084
|
autoneg_state: AutoNegStatus = field(XmpInt())
|
|
1005
|
-
"""Autoneg
|
|
1085
|
+
"""Autoneg status
|
|
1086
|
+
|
|
1087
|
+
:type autoneg_state: AutoNegStatus
|
|
1088
|
+
"""
|
|
1089
|
+
|
|
1006
1090
|
received_tech_abilities: Hex = field(XmpHex(size=8))
|
|
1007
|
-
"""Received technology abilities from the remote port
|
|
1091
|
+
"""Received technology abilities bitmask from the remote port
|
|
1092
|
+
|
|
1093
|
+
To parse the bitmask, refer to the :class:`AutoNegTecAbility` enum IntFlag.
|
|
1094
|
+
|
|
1095
|
+
:type received_tech_abilities: Hex, 16 characters long.
|
|
1096
|
+
"""
|
|
1097
|
+
|
|
1008
1098
|
received_fec_abilities: Hex = field(XmpHex(size=1))
|
|
1009
|
-
"""Received FEC capabilities from the remote port
|
|
1099
|
+
"""Received FEC capabilities bitmask from the remote port
|
|
1100
|
+
|
|
1101
|
+
To parse the bitmask, refer to the :class:`AutoNegFECAbility` enum IntFlag.
|
|
1102
|
+
|
|
1103
|
+
:type received_fec_abilities: Hex, 2 characters long.
|
|
1104
|
+
"""
|
|
1105
|
+
|
|
1010
1106
|
received_pause_mode: Hex = field(XmpHex(size=1))
|
|
1011
|
-
"""Received pause capabilities from the remote port
|
|
1012
|
-
|
|
1013
|
-
|
|
1014
|
-
|
|
1015
|
-
|
|
1107
|
+
"""Received pause capabilities bitmask from the remote port
|
|
1108
|
+
|
|
1109
|
+
To parse the bitmask, refer to the :class:`AutoNegPauseAbility` enum IntFlag.
|
|
1110
|
+
|
|
1111
|
+
:type received_pause_mode: Hex, 2 characters long.
|
|
1112
|
+
"""
|
|
1113
|
+
|
|
1114
|
+
tech_ability_hcd_status: AutoNegTechAbilityHCDStatus = field(XmpInt())
|
|
1115
|
+
"""HCD technology ability negotiation status
|
|
1116
|
+
|
|
1117
|
+
:type tech_ability_hcd_status: AutoNegTechAbilityHCDStatus
|
|
1118
|
+
"""
|
|
1119
|
+
|
|
1120
|
+
tech_ability_hcd_value: AutoNegTecAbilityHCD = field(XmpInt())
|
|
1121
|
+
"""HCD technology ability negotiation result
|
|
1122
|
+
|
|
1123
|
+
:type tech_ability_hcd_value: AutoNegTecAbilityHCD
|
|
1124
|
+
"""
|
|
1125
|
+
|
|
1016
1126
|
fec_mode_result: FECMode = field(XmpInt())
|
|
1017
|
-
"""FEC mode negotiation result
|
|
1127
|
+
"""FEC mode negotiation result
|
|
1128
|
+
|
|
1129
|
+
:type fec_mode_result: FECMode
|
|
1130
|
+
"""
|
|
1131
|
+
|
|
1018
1132
|
pause_mode_result: PauseMode = field(XmpInt())
|
|
1019
|
-
"""Pause mode negotiation result
|
|
1133
|
+
"""Pause mode negotiation result
|
|
1134
|
+
|
|
1135
|
+
:type pause_mode_result: PauseMode
|
|
1136
|
+
"""
|
|
1020
1137
|
|
|
1021
1138
|
def get(self) -> Token[GetDataAttr]:
|
|
1139
|
+
"""Get the autonegotiation status.
|
|
1140
|
+
|
|
1141
|
+
:return: The autonegotiation status
|
|
1142
|
+
:rtype: PL1_AUTONEG_STATUS.GetDataAttr
|
|
1143
|
+
"""
|
|
1022
1144
|
|
|
1023
1145
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1024
1146
|
|
|
@@ -1038,16 +1160,30 @@ class PL1_AUTONEG_ABILITIES:
|
|
|
1038
1160
|
|
|
1039
1161
|
class GetDataAttr(ResponseBodyStruct):
|
|
1040
1162
|
tech_abilities_supported: Hex = field(XmpHex(size=8))
|
|
1041
|
-
"""
|
|
1163
|
+
"""Supported technology abilities by the port. This returns a value in Hex of the format HHHHHHHH (64 bits). Each bit corresponds to technology ability as defined in :class:`AutoNegTecAbility`. A bit of 1 means the corresponding technology ability is supported by the port.
|
|
1164
|
+
|
|
1165
|
+
|
|
1166
|
+
:type tech_abilities_supported: Hex, 16 characters long.
|
|
1167
|
+
"""
|
|
1042
1168
|
|
|
1043
1169
|
fec_modes_supported: Hex = field(XmpHex(size=1))
|
|
1044
|
-
"""
|
|
1170
|
+
"""Supported FEC modes by the port. This returns a value in Hex of the format HH (8 bits). Each bit corresponds to FEC mode as defined in :class:`AutoNegFECAbility`. A bit of 1 means the corresponding FEC mode is supported by the port.
|
|
1171
|
+
|
|
1172
|
+
:type fec_modes_supported: Hex, 2 characters long.
|
|
1173
|
+
"""
|
|
1045
1174
|
|
|
1046
1175
|
pause_modes_supported: Hex = field(XmpHex(size=1))
|
|
1047
|
-
"""
|
|
1176
|
+
"""Pause abilities supported by the port. This returns a value in Hex of the format HH (8 bits). Each bit corresponds to pause mode as defined in :class:`AutoNegPauseAbility`. A bit of 1 means the corresponding FEC mode is supported by the port.
|
|
1177
|
+
|
|
1178
|
+
:type pause_modes_supported: Hex, 2 characters long.
|
|
1179
|
+
"""
|
|
1048
1180
|
|
|
1049
1181
|
def get(self) -> Token[GetDataAttr]:
|
|
1182
|
+
"""Get the supported technology abilities, FEC abilities, and pause abilities of the port.
|
|
1050
1183
|
|
|
1184
|
+
:return: The supported abilities
|
|
1185
|
+
:rtype: Token[GetDataAttr]
|
|
1186
|
+
"""
|
|
1051
1187
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1052
1188
|
|
|
1053
1189
|
@register_command
|
|
@@ -1073,11 +1209,21 @@ class PL1_PCS_VARIANT:
|
|
|
1073
1209
|
"""PCS variant"""
|
|
1074
1210
|
|
|
1075
1211
|
def get(self) -> Token[GetDataAttr]:
|
|
1212
|
+
"""Get the PCS variant configuration.
|
|
1213
|
+
|
|
1214
|
+
:return: The PCS variant configuration
|
|
1215
|
+
:rtype: PL1_PCS_VARIANT.GetDataAttr
|
|
1216
|
+
"""
|
|
1076
1217
|
|
|
1077
1218
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1078
1219
|
|
|
1079
1220
|
def set(self, variant: FreyaPCSVariant) -> Token[None]:
|
|
1221
|
+
"""Set the PCS variant configuration.
|
|
1080
1222
|
|
|
1223
|
+
:param variant: The PCS variant configuration to set
|
|
1224
|
+
:type variant: FreyaPCSVariant
|
|
1225
|
+
:return: A token indicating the completion of the set operation
|
|
1226
|
+
"""
|
|
1081
1227
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, variant=variant))
|
|
1082
1228
|
|
|
1083
1229
|
|
|
@@ -1113,11 +1259,23 @@ class PL1_CWE_CYCLE:
|
|
|
1113
1259
|
"""The number of consecutive errored FEC codewords in a cycle, must not be larger than cycle_len"""
|
|
1114
1260
|
|
|
1115
1261
|
def get(self) -> Token[GetDataAttr]:
|
|
1262
|
+
"""Get the FEC codeword error injection cycle configuration.
|
|
1116
1263
|
|
|
1264
|
+
:return: The FEC codeword error injection cycle configuration
|
|
1265
|
+
:rtype: PL1_CWE_CYCLE.GetDataAttr
|
|
1266
|
+
"""
|
|
1117
1267
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1118
1268
|
|
|
1119
1269
|
def set(self, loop: int, cycle_len: int, error_len: int) -> Token[None]:
|
|
1120
|
-
|
|
1270
|
+
"""Set the FEC codeword error injection cycle configuration.
|
|
1271
|
+
|
|
1272
|
+
:param loop: Loop count of the FEC codeword error injection cycle. <loop> == 0 means continuous.
|
|
1273
|
+
:type loop: int
|
|
1274
|
+
:param cycle_len: The number of FEC codewords in the cycle, must be larger than 0 and an even number.
|
|
1275
|
+
:type cycle_len: int
|
|
1276
|
+
:param error_len: The number of consecutive errored FEC codewords in a cycle, must not be larger than cycle_len
|
|
1277
|
+
:type error_len: int
|
|
1278
|
+
"""
|
|
1121
1279
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, loop=loop, cycle_len=cycle_len, error_len=error_len))
|
|
1122
1280
|
|
|
1123
1281
|
set_continuous = functools.partialmethod(set, 0)
|
|
@@ -1168,9 +1326,19 @@ class PL1_CWE_ERR_SYM_INDICES:
|
|
|
1168
1326
|
"""
|
|
1169
1327
|
|
|
1170
1328
|
def get(self) -> Token[GetDataAttr]:
|
|
1329
|
+
"""Get the positions of the errored symbols in errored codewords.
|
|
1330
|
+
|
|
1331
|
+
:return: The positions of the errored symbols in errored codewords
|
|
1332
|
+
:rtype: PL1_CWE_ERR_SYM_INDICES.GetDataAttr
|
|
1333
|
+
"""
|
|
1171
1334
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1172
1335
|
|
|
1173
1336
|
def set(self, error_sym_indices: typing.List[int]) -> Token[None]:
|
|
1337
|
+
"""Set the positions of the errored symbols in errored codewords.
|
|
1338
|
+
|
|
1339
|
+
:param error_sym_indices: The positions of the errored symbols in errored codewords
|
|
1340
|
+
:type error_sym_indices: typing.List[int]
|
|
1341
|
+
"""
|
|
1174
1342
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, error_sym_indices=error_sym_indices))
|
|
1175
1343
|
|
|
1176
1344
|
|
|
@@ -1201,9 +1369,21 @@ class PL1_CWE_BIT_ERR_MASK:
|
|
|
1201
1369
|
"""bit error mask for the errored symbols, big endian, only 10 bits are effective."""
|
|
1202
1370
|
|
|
1203
1371
|
def get(self) -> Token[GetDataAttr]:
|
|
1372
|
+
"""Get the bit error mask configuration.
|
|
1373
|
+
|
|
1374
|
+
:return: The bit error mask mode and bitmask
|
|
1375
|
+
:rtype: PL1_CWE_BIT_ERR_MASK.GetDataAttr
|
|
1376
|
+
"""
|
|
1204
1377
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1205
1378
|
|
|
1206
1379
|
def set(self, mode: FecCodewordBitErrorMaskMode, bitmask: Hex) -> Token[None]:
|
|
1380
|
+
"""Set the bit error mask configuration.
|
|
1381
|
+
|
|
1382
|
+
:param mode: Bit error mask mode
|
|
1383
|
+
:type mode: FecCodewordBitErrorMaskMode
|
|
1384
|
+
:param bitmask: Bit error mask for the errored symbols, big endian, only 10 bits are effective
|
|
1385
|
+
:type bitmask: Hex
|
|
1386
|
+
"""
|
|
1207
1387
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, mode=mode, bitmask=bitmask))
|
|
1208
1388
|
|
|
1209
1389
|
set_all_bits = functools.partialmethod(set, FecCodewordBitErrorMaskMode.STATIC, Hex("03FF"))
|
|
@@ -1250,9 +1430,19 @@ class PL1_CWE_FEC_ENGINE:
|
|
|
1250
1430
|
"""
|
|
1251
1431
|
|
|
1252
1432
|
def get(self) -> Token[GetDataAttr]:
|
|
1433
|
+
"""Get which FEC engines are used.
|
|
1434
|
+
|
|
1435
|
+
:return: The FEC engines bitmask
|
|
1436
|
+
:rtype: PL1_CWE_FEC_ENGINE.GetDataAttr
|
|
1437
|
+
"""
|
|
1253
1438
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
1254
1439
|
|
|
1255
1440
|
def set(self, bitmask: Hex) -> Token[None]:
|
|
1441
|
+
"""Set which FEC engines to use.
|
|
1442
|
+
|
|
1443
|
+
:param bitmask: FEC engines bitmask
|
|
1444
|
+
:type bitmask: Hex
|
|
1445
|
+
"""
|
|
1256
1446
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, bitmask=bitmask))
|
|
1257
1447
|
|
|
1258
1448
|
set_all_engines = functools.partialmethod(set, Hex("0F"))
|
|
@@ -1287,6 +1477,11 @@ class PL1_CWE_FEC_STATS:
|
|
|
1287
1477
|
"""Total injected symbol errors."""
|
|
1288
1478
|
|
|
1289
1479
|
def get(self) -> Token[GetDataAttr]:
|
|
1480
|
+
"""Get FEC error injection statistics.
|
|
1481
|
+
|
|
1482
|
+
:return: FEC error injection statistics
|
|
1483
|
+
:rtype: PL1_CWE_FEC_STATS.GetDataAttr
|
|
1484
|
+
"""
|
|
1290
1485
|
|
|
1291
1486
|
return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
|
|
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@@ -1306,22 +1501,36 @@ class PL1_AUTONEG_CONFIG:
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_port: int
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class GetDataAttr(ResponseBodyStruct):
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-
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-
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tech_abilities: Hex = field(XmpHex(size=8))
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fec_abilities: Hex = field(XmpHex(size=1))
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pause_mode: Hex = field(XmpHex(size=1))
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class SetDataAttr(RequestBodyStruct):
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-
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tech_abilities: Hex = field(XmpHex(size=8))
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fec_abilities: Hex = field(XmpHex(size=1))
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pause_mode: Hex = field(XmpHex(size=1))
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def get(self) -> Token[GetDataAttr]:
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"""Get the advertised technology abilities, FEC abilities, and pause abilities of the port.
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:return: The advertised abilities
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:rtype: PL1_AUTONEG_CONFIG.GetDataAttr
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"""
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return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
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def set(self,
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def set(self, tech_abilities: Hex, fec_abilities: Hex, pause_mode: Hex) -> Token[None]:
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"""Set the advertised technology abilities, FEC abilities, and pause abilities of the port.
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:param tech_abilities: Advertised technology abilities bitmask
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:type tech_abilities: Hex
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:param fec_abilities: Advertised FEC abilities bitmask
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:type fec_abilities: Hex
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:param pause_mode: Advertised pause mode bitmask
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:type pause_mode: Hex
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"""
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return Token(self._connection, build_set_request(self, module=self._module, port=self._port, advertised_tech_abilities=
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return Token(self._connection, build_set_request(self, module=self._module, port=self._port, advertised_tech_abilities=tech_abilities, advertised_fec_abilities=fec_abilities, advertised_pause_mode=pause_mode))
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@register_command
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@dataclass
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@@ -1475,11 +1684,23 @@ class PL1_LINKTRAIN_CONFIG:
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timeout_mode: TimeoutMode = field(XmpByte())
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def get(self) -> Token[GetDataAttr]:
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"""Get the current per-port link training settings.
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:return: The current per-port link training settings
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:rtype: PL1_LINKTRAIN_CONFIG.GetDataAttr
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"""
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return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
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def set(self, oos_preset: FreyaOutOfSyncPreset, timeout_mode: TimeoutMode) -> Token[None]:
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"""Set the current per-port link training settings.
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:param oos_preset: Out-of-sync preset value
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:type oos_preset: FreyaOutOfSyncPreset
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:param timeout_mode: Timeout mode value
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:type timeout_mode: TimeoutMode
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:return: A token indicating the completion of the set operation
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"""
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return Token(self._connection, build_set_request(self, module=self._module, port=self._port, oos_preset=oos_preset, timeout_mode=timeout_mode))
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@register_command
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@@ -1537,9 +1758,20 @@ class PL1_CWE_CONTROL:
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"""Control action for FEC codeword error injection"""
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def get(self) -> Token[GetDataAttr]:
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"""Get the current control action for FEC codeword error injection.
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:return: The current control action for FEC codeword error injection
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:rtype: PL1_CWE_CONTROL.GetDataAttr
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"""
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return Token(self._connection, build_get_request(self, module=self._module, port=self._port))
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def set(self, action: StartOrStop) -> Token[None]:
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"""Set the control action for FEC codeword error injection.
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:param action: Control action for FEC codeword error injection
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:type action: StartOrStop
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:return: A token indicating the completion of the set operation
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"""
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return Token(self._connection, build_set_request(self, module=self._module, port=self._port, action=action))
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set_start = functools.partialmethod(set, StartOrStop.START)
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@@ -1667,4 +1899,39 @@ class PL1_PNSWAP_RX:
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set_off = functools.partialmethod(set, OnOff.OFF)
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"""Set P/N polarity swap of the SerDes in the receiving direction to OFF
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-
"""
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"""
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1904
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__all__ = [
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1905
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"PL1_ANLT",
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1906
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"PL1_AUTONEGINFO",
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1907
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"PL1_AUTONEG_ABILITIES",
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"PL1_AUTONEG_CONFIG",
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"PL1_AUTONEG_STATUS",
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"PL1_CFG_TMP",
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1911
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"PL1_CTRL",
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1912
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"PL1_CWE_BIT_ERR_MASK",
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1913
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"PL1_CWE_CONTROL",
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1914
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"PL1_CWE_CYCLE",
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1915
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"PL1_CWE_ERR_SYM_INDICES",
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1916
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"PL1_CWE_FEC_ENGINE",
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"PL1_CWE_FEC_STATS",
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1918
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"PL1_CWE_FEC_STATS_CLEAR",
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1919
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"PL1_GET_DATA",
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1920
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"PL1_LINKTRAININFO",
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1921
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"PL1_LINKTRAIN_CMD",
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1922
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"PL1_LINKTRAIN_CONFIG",
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1923
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"PL1_LINKTRAIN_STATUS",
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1924
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"PL1_LOG",
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1925
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"PL1_LT_PHYTXEQ_RANGE",
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1926
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"PL1_LT_PHYTXEQ_RANGE_COEFF",
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1927
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"PL1_PCS_VARIANT",
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1928
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"PL1_PHYTXEQ",
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1929
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"PL1_PHYTXEQ_COEFF",
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1930
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+
"PL1_PHYTXEQ_LEVEL",
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1931
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"PL1_PNSWAP_RX",
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1932
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"PL1_PNSWAP_TX",
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1933
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+
"PL1_PRESET_CONFIG",
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1934
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"PL1_PRESET_CONFIG_COEFF",
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1935
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+
"PL1_PRESET_CONFIG_LEVEL",
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1936
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+
"PL1_PRESET_RESET",
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1937
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+
]
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@@ -1,3 +1,4 @@
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1
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+
"""Port Length Term Commands"""
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1
2
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from __future__ import annotations
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2
3
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from dataclasses import dataclass
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3
4
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import typing
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@@ -176,3 +177,10 @@ class PL_LENGTH:
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set_at_least = functools.partialmethod(set, LengthCheckType.AT_LEAST)
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177
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"""Set the length check to be longer than or equal to the given length (at least).
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178
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"""
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180
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+
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181
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+
__all__ = [
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182
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+
"PL_CREATE",
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183
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+
"PL_DELETE",
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184
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+
"PL_INDICES",
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185
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+
"PL_LENGTH",
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186
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+
]
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@@ -1,3 +1,4 @@
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1
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+
"""Port Match Term Commands"""
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1
2
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from __future__ import annotations
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2
3
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from dataclasses import dataclass
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3
4
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import typing
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@@ -254,3 +255,13 @@ class PM_MATCH:
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254
255
|
"""
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256
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256
257
|
return Token(self._connection, build_set_request(self, module=self._module, port=self._port, indices=[self._match_term_xindex], mask=mask, value=value))
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258
|
+
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259
|
+
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260
|
+
__all__ = [
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261
|
+
"PM_CREATE",
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262
|
+
"PM_DELETE",
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263
|
+
"PM_INDICES",
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264
|
+
"PM_MATCH",
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265
|
+
"PM_POSITION",
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266
|
+
"PM_PROTOCOL",
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267
|
+
]
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