tdl-xoa-driver 1.3.0__py3-none-any.whl → 1.5.0__py3-none-any.whl

xoa_driver/internals/hli/ports/port_l23/bases/port_transceiver.py

@@ -0,0 +1,247 @@
+from typing import TYPE_CHECKING
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+from xoa_driver.internals.commands import (
+    PX_RW,
+    PX_MII,
+    PX_TEMPERATURE,
+    PX_RW_SEQ,
+    PX_I2C_CONFIG,
+    PX_RW_SEQ_BANK,
+    PX_CDB_SUPPORT,
+    PX_CDB_ABORT_PROCESSING,
+    PX_CDB_CHANGE_PASSWORD,
+    PX_CDB_ENTER_PASSWORD,
+    PX_CDB_QUERY_STATUS,
+    PX_CDB_EXTERNAL_FEATURES,
+    PX_CDB_FW_MGMT_FEATURES,
+    PX_CDB_GET_APP_ATTRIBUTES,
+    PX_CDB_GET_IF_CODE_DESCR,
+    PX_CDB_MODULE_FEATURES,
+    PX_CDB_SEC_FEAT_CAPABILITIES,
+    PX_CDB_ABORT_FW_DOWNLOAD,
+    PX_CDB_COMMIT_FW_IMAGE,
+    PX_CDB_COMPLETE_FW_DOWNLOAD,
+    PX_CDB_COPY_FW_IMAGE,
+    PX_CDB_GET_FW_INFO,
+    PX_CDB_READ_FW_BLOCK_EPL,
+    PX_CDB_READ_FW_BLOCK_LPL,
+    PX_CDB_RUN_FW_IMAGE,
+    PX_CDB_START_FW_DOWNLOAD,
+    PX_CDB_WRITE_FW_BLOCK_EPL,
+    PX_CDB_WRITE_FW_BLOCK_LPL,
+    PX_CUST_CMD,
+)
+
+
+class PortTransceiver:
+    """Transceiver access class."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+
+        self.i2c_config = PX_I2C_CONFIG(conn, module_id, port_id)
+        """
+        Access speed on a transceiver I2C access in the unit of KHz. Default to 100. 
+        
+        When the transceiver is plugged out and in again, the speed will be reset to the default value 100. The speed has a minimum and a maximum, which can be obtained from port.capabilities(). 
+        
+        The I2C speed configuration will not be included in the port configuration file (.xpc). When you load a port configuration to a port, the transceiver I2C access speed will be reset to default.
+        """
+
+        self.temperature = PX_TEMPERATURE(conn, module_id, port_id)
+        """Transceiver temperature in Celsius.
+
+        Temperature value before the decimal digit, and 1/256th of a degree Celsius after the decimal digit.
+        """
+
+        self.cmis = CMIS(conn, module_id, port_id)
+        """
+        Access CMIS interface.
+        """
+
+    def access_rw(self, page_address: int, register_address: int) -> "PX_RW":
+        """Access to register interface by the transceiver.
+
+        :param page_address: page address
+        :type page_address: int
+        :param register_address: register address
+        :type register_address: int
+        :return: transceiver register values
+        :rtype: PX_RW
+        """
+
+        return PX_RW(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            page_address,
+            register_address
+        )
+
+    def access_mii(self, register_address: int) -> "PX_MII":
+        """Access to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param register_address: register address
+        :type register_address: int
+        :return: register values
+        :rtype: PX_MII
+        """
+        return PX_MII(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            register_address
+        )
+
+    def access_rw_seq(self, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ":
+        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param page_address: page address (0-255)
+        :type page_address: int
+        :param register_address: register address (0-255)
+        :type register_address: int
+        :param byte_count: the number of bytes to read/write
+        :type byte_count: int
+        :return: transceiver register values
+        :rtype: PX_RW_SEQ
+        """
+        return PX_RW_SEQ(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            page_address,
+            register_address,
+            byte_count
+        )
+    
+    def access_rw_seq_bank(self, bank_address: int, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ_BANK":
+        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param bank_address: bank address (0-255)
+        :type bank_address: int
+        :param page_address: page address (0-255)
+        :type page_address: int
+        :param register_address: register address (0-255)
+        :type register_address: int
+        :param byte_count: the number of bytes to read/write
+        :type byte_count: int
+        :return: transceiver register values
+        :rtype: PX_RW_SEQ_BANK
+        """
+        return PX_RW_SEQ_BANK(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            bank_address,
+            page_address,
+            register_address,
+            byte_count
+        )
+
+class CMIS():
+    """CMIS access class.
+    """
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+
+        self.cdb_instances_supported = PX_CDB_SUPPORT(conn, module_id, port_id)
+        """Return the number of supported CDB instances.
+        """
+
+    def cdb(self, cdb_instance_id: int) -> "CDB":
+        """Access CMIS CDB command interface.
+
+        :param cdb_instance_id: 0 for CDB Instance 1, 1 for CDB Instance 2
+        :type cdb_instance_id: int
+        """
+        return CDB(self.__conn, self.__module_id, self.__port_id, cdb_instance_id)
+        
+
+class CDB():
+    """CMIS CDB command access class.
+    """
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, cdb_instance_id: int) -> None:
+
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+        self.__cdb_instance_id = cdb_instance_id
+
+        # CDB Module Commands
+        self.cmd_0000h_query_status = PX_CDB_QUERY_STATUS(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0000h: Query Status
+        """
+        self.cmd_0001h_enter_password = PX_CDB_ENTER_PASSWORD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0001h: Enter Password
+        """
+        self.cmd_0002h_change_password = PX_CDB_CHANGE_PASSWORD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0002h: Change Password
+        """
+        self.cmd_0004h_abort_processing = PX_CDB_ABORT_PROCESSING(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0004h: Abort Processing
+        """ 
+
+        # CDB Features and Capabilities Inquiry Commands
+        self.cmd_0040h_module_features = PX_CDB_MODULE_FEATURES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0040h: Module Features
+        """
+        self.cmd_0041h_fw_mgmt_features = PX_CDB_FW_MGMT_FEATURES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0041h: Firmware Management Features
+        """
+        self.cmd_0044h_sec_feat_capabilities = PX_CDB_SEC_FEAT_CAPABILITIES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0044h: Security Features and Capabilities
+        """
+        self.cmd_0045h_external_features = PX_CDB_EXTERNAL_FEATURES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0045h: Externally Defined Features
+        """
+        self.cmd_0050h_get_app_attributes = PX_CDB_GET_APP_ATTRIBUTES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0050h: Get Application Attributes
+        """
+        self.cmd_0051h_get_if_code_descr = PX_CDB_GET_IF_CODE_DESCR(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0051h: Get Interface Code Description
+        """
+
+        # CDB Firmware Management Commands
+        self.cmd_0100h_get_firmware_info = PX_CDB_GET_FW_INFO(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0100h: Get Firmware Info
+        """
+        self.cmd_0101h_start_firmware_download = PX_CDB_START_FW_DOWNLOAD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0101h: Start Firmware Download
+        """
+        self.cmd_0102h_abort_firmware_download = PX_CDB_ABORT_FW_DOWNLOAD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0102h: Abort Firmware Download
+        """
+        self.cmd_0103h_write_firmware_block_lpl = PX_CDB_WRITE_FW_BLOCK_LPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0103h: Write Firmware Block LPL
+        """
+        self.cmd_0104h_write_firmware_block_epl = PX_CDB_WRITE_FW_BLOCK_EPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0104h: Write Firmware Block EPL
+        """
+        self.cmd_0105h_read_firmware_block_lpl = PX_CDB_READ_FW_BLOCK_LPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0105h: Read Firmware Block LPL
+        """
+        self.cmd_0106h_read_firmware_block_epl = PX_CDB_READ_FW_BLOCK_EPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0106h: Read Firmware Block EPL
+        """
+        self.cmd_0107h_complete_firmware_download = PX_CDB_COMPLETE_FW_DOWNLOAD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0107h: Complete Firmware Download
+        """
+        self.cmd_0108h_copy_firmware_image = PX_CDB_COPY_FW_IMAGE(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0108h: Copy Firmware Image
+        """
+        self.cmd_0109h_run_firmware_image = PX_CDB_RUN_FW_IMAGE(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0109h: Run Firmware Image
+        """
+        self.cmd_010ah_commit_firmware_image = PX_CDB_COMMIT_FW_IMAGE(conn, module_id, port_id, cdb_instance_id)
+        """CMD 010Ah: Commit Firmware Image
+        """
+        
+        # Custom Commands
+        self.custom_cmd = PX_CUST_CMD(conn, module_id, port_id, cdb_instance_id)
+        """Defnes the custom CDB commdand (CMD and Reply) to be sent to the CDB instance.
+        """

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/bases/port_transmission_statistics.py

@@ -4,7 +4,7 @@ from typing import (
 )
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
-    from xoa_driver.internals.hli_v1.indices.streams.genuine_stream import GenuineStreamIdx
+    from xoa_driver.internals.hli.indices.streams.genuine_stream import GenuineStreamIdx
 from xoa_driver.internals.commands import (
     PT_TOTAL,
     PT_NOTPLD,

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/chimera/port_chimera.py

@@ -14,7 +14,7 @@ from xoa_driver.internals.commands import (
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
 
-from xoa_driver.internals.hli_v1.ports import base_port
+from xoa_driver.internals.hli.ports import base_port
 from xoa_driver.internals.utils import attributes as utils
 from xoa_driver.internals.state_storage import ports_state
 from ..pcs_pma_ijkl_chimera import PcsPma

xoa_driver/internals/hli/ports/port_l23/edun_l1.py

@@ -0,0 +1,181 @@
+from typing import (
+    TYPE_CHECKING,
+    Tuple,
+)
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+from xoa_driver.internals.commands import (
+    PP_PRECODING,
+    PP_GRAYCODING,
+    PL1_PHYTXEQ_LEVEL,
+    PL1_PHYTXEQ_COEFF,
+    PL1_PCS_VARIANT,
+    PL1_PHYTXEQ,
+    PL1_CWE_CYCLE,
+    PL1_CWE_ERR_SYM_INDICES,
+    PL1_CWE_BIT_ERR_MASK,
+    PL1_CWE_FEC_ENGINE,
+    PL1_CWE_FEC_STATS,
+    PL1_CWE_CONTROL,
+    PL1_CWE_FEC_STATS_CLEAR,
+    PP_PRBSTYPE,
+    PL1_PNSWAP_RX,
+    PL1_PNSWAP_TX,
+    PP_AUTONEG,
+    PP_AUTONEGSTATUS,
+    PP_LINKTRAIN,
+)
+from .pcs_pma_ghijkl import (
+    Prbs,
+)
+from xoa_driver import enums
+
+class EdunPMA:
+    """Edun PMA"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+        self.precoding = PP_PRECODING(conn, module_id, port_id, serdes_xindex)
+        """GET/SET Pre-Coding Configurations.
+
+        :type: PP_PRECODING
+        """
+
+        self.graycoding = PP_GRAYCODING(conn, module_id, port_id, serdes_xindex)
+        """GET/SET Gray-Coding Configurations.
+
+        :type: PP_GRAYCODING
+        """
+
+        self.pn_swap_rx = PL1_PNSWAP_RX(conn, module_id, port_id, serdes_xindex)
+        """GET/SET PN-Swap RX Configurations. 
+
+        :type: PL1_PNSWAP_RX
+        """
+
+        self.pn_swap_tx = PL1_PNSWAP_TX(conn, module_id, port_id, serdes_xindex)
+        """GET/SET PN-Swap TX Configurations.
+        
+        :type: PL1_PNSWAP_TX
+        """
+
+class EdunTxTap:
+    """Edun Tx Tap"""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+        self.native = PL1_PHYTXEQ(conn, module_id, port_id, serdes_xindex)
+        """TX tap native value. (only for Edun)
+
+        :type: PL1_PHYTXEQ
+        """
+
+        self.level = PL1_PHYTXEQ_LEVEL(conn, module_id, port_id, serdes_xindex)
+        """TX tap mV/dB value. (only for Edun)
+
+        :type: PL1_PHYTXEQ_LEVEL
+        """
+
+        self.ieee = PL1_PHYTXEQ_COEFF(conn, module_id, port_id, serdes_xindex)
+        """TX tap IEEE coefficient value. (only for Edun)
+
+        :type: PL1_PHYTXEQ_COEFF
+        """
+
+# class EdunRxTap:
+#     """Edun Rx tap
+#     """
+    # def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+    #     self.status = P_EDUN_RX_STATUS(conn, module_id, port_id, serdes_xindex)
+    #     """Edun Rx tap status
+    #     """
+
+class EdunMedium:
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+        self.tx = EdunTxTap(conn, module_id, port_id, serdes_xindex)
+        """Edun Tx tap
+        """
+        # self.rx = EdunRxTap(conn, module_id, port_id, serdes_xindex)
+        # """Edun Rx tap
+        # """
+
+class SerDesEdun:
+    """L23 high-speed port SerDes configuration and status."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, serdes_xindex: int) -> None:
+
+        self.prbs = Prbs(conn, module_id, port_id, serdes_xindex)
+        """PRBS
+        :type: Prbs
+        """
+        
+        self.pma = EdunPMA(conn, module_id, port_id, serdes_xindex)
+        """Edun PMA
+
+        :type: EdunPMA
+        """
+
+        self.medium = EdunMedium(conn, module_id, port_id, serdes_xindex)
+        """Edun medium
+
+        :type: EdunMedium
+        """
+
+class EdunAutoneg:
+    """Edun port-level autoneg. For per-serdes configuration and status, use serdes[x]
+    """
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.config = PP_AUTONEG(conn, module_id, port_id)
+        """Autoneg config and status
+        """
+        self.status = PP_AUTONEGSTATUS(conn, module_id, port_id)
+        """Autoneg status
+        """
+
+class EdunFecCodewordErrorInject:
+    """Edun FEC Codeword Error Injection
+    """
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.cycle = PL1_CWE_CYCLE(conn, module_id, port_id)
+        """FEC codeword error injection cycle.
+        """
+        self.err_symbols = PL1_CWE_ERR_SYM_INDICES(conn, module_id, port_id)
+        """The positions of the errored symbols in errored codewords.
+        """
+        self.bit_err_mask = PL1_CWE_BIT_ERR_MASK(conn, module_id, port_id)
+        """The bit error mask for the errored symbols.
+        """
+        self.engine = PL1_CWE_FEC_ENGINE(conn, module_id, port_id)
+        """The FEC engines to use.
+        """
+        self.statistics = PL1_CWE_FEC_STATS(conn, module_id, port_id)
+        """FEC error injection statistics
+        """
+        self.clear_stats = PL1_CWE_FEC_STATS_CLEAR(conn, module_id, port_id)
+        """Clear FEC codeword injection stats
+        """
+        self.control = PL1_CWE_CONTROL(conn, module_id, port_id)
+        """Control the FEC codeword error injection
+        """
+
+class Layer1:
+    def __init__(self, conn: "itf.IConnection", port) -> None:
+        self.serdes: Tuple[SerDesEdun, ...] = tuple(
+                SerDesEdun(conn, *port.kind, serdes_xindex=idx)
+                for idx in range(port.info.capabilities.serdes_count)
+                )
+        self.autoneg = EdunAutoneg(conn, *port.kind)
+        """Edun port-level autoneg. For per-serdes configuration and status, use serdes[x]
+        """
+        self.lt = PP_LINKTRAIN(conn, *port.kind)
+        """Edun Link Training on serdes level
+
+        :type: PP_LINKTRAIN
+        """
+        self.pcs_variant = PL1_PCS_VARIANT(conn, *port.kind)
+        """PCS variant configuration
+        """
+        self.fec_error_inject = EdunFecCodewordErrorInject(conn, *port.kind)
+        """FEC codeword error injection
+        """
+        self.prbs_config = PP_PRBSTYPE(conn, *port.kind)
+        """PRBS configuration, including PRBS polynomial, invert mode, and statistic collection mode (for RX).
+        """

xoa_driver/internals/hli/ports/port_l23/family_edun.py

@@ -0,0 +1,82 @@
+
+import functools
+from typing import TYPE_CHECKING, Tuple
+from typing import Self
+from xoa_driver.internals.commands import (
+    P_DYNAMIC,
+)
+from xoa_driver import enums
+from xoa_driver.internals.utils import attributes as utils
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+
+from .bases.port_l23_genuine import BasePortL23Genuine
+from .pcs_pma_ijkl_chimera import PcsPma as PcsPma1
+from .pcs_pma_ghijkl import (
+    PcsPma as PcsPma2,
+    SerDes,
+)
+from .pcs_pma_l import PcsPma as PcsPma3  
+from .edun_l1 import Layer1
+
+class PcsPma(PcsPma1, PcsPma2, PcsPma3):
+    """Edun PCS/PMA
+    """
+    def __init__(self, conn: "itf.IConnection", port) -> None:
+        PcsPma1.__init__(self, conn, port)
+        PcsPma2.__init__(self, conn, port)
+        PcsPma3.__init__(self, conn, port)
+
+class L1(Layer1):
+    """Edun L1
+    """
+    def __init__(self, conn: "itf.IConnection", port) -> None:
+        Layer1.__init__(self, conn, port)
+
+
+class FamilyEdun(BasePortL23Genuine):
+    pcs_pma: PcsPma
+    """PCS/PMA layer
+
+    :type: PcsPma
+    """
+    
+    # serdes: Tuple[SerDes, ...]
+    # """SerDes index
+
+    # :type: Tuple[SerDes, ...]
+    # """
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        super().__init__(conn, module_id, port_id)
+        self.dynamic = P_DYNAMIC(conn, module_id, port_id)
+        """L23 port's dynamic traffic change.
+        
+        :type: P_DYNAMIC
+        """
+
+        # self.fault = Fault(conn, module_id, port_id)
+
+    async def _setup(self) -> Self:
+        await super()._setup()
+        self.pcs_pma = PcsPma(self._conn, self)
+        # self.serdes = tuple(
+        #     SerDes(self._conn, *self.kind, serdes_xindex=serdes_xindex)
+        #     for serdes_xindex in range(self.info.capabilities.serdes_count)
+        # )
+        self.l1 = L1(self._conn, self)
+        return self
+
+    on_dynamic_change = functools.partialmethod(utils.on_event, P_DYNAMIC)
+    """Register a callback to the event that the port's dynamic traffic setting changes."""
+
+
+class PEdun800G3S1PSMPX_a(FamilyEdun):
+    """L23 port on Edun-800G-3S-1P-SMPX[a] module.
+    """
+    ...
+
+class PEdun1600G4S1POSFP_a(FamilyEdun):
+    """L23 port on Edun-1600G-4S-1P-OSFP[a] module.
+    """
+    ...

xoa_driver/internals/{hli_v2 → hli}/ports/port_l23/family_g.py

@@ -75,3 +75,8 @@ class PLoki100G3S1PB_b(FamilyG):
     """L23 port on Loki-100G-3S-1P-B[b] module.
     """
     ...
+
+class PLoki100G5S4P_a(FamilyG):
+    """L23 port on Loki-100G-5S-4P[a] module.
+    """
+    ...

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/family_l1.py

@@ -41,11 +41,11 @@ class FamilyFreya(BasePortL23Genuine):
     :type: PcsPma
     """
     
-    serdes: Tuple[SerDes, ...]
-    """SerDes index
+    # serdes: Tuple[SerDes, ...]
+    # """SerDes index
 
-    :type: Tuple[SerDes, ...]
-    """
+    # :type: Tuple[SerDes, ...]
+    # """
 
     def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
         super().__init__(conn, module_id, port_id)
@@ -60,10 +60,10 @@ class FamilyFreya(BasePortL23Genuine):
     async def _setup(self) -> Self:
         await super()._setup()
         self.pcs_pma = PcsPma(self._conn, self)
-        self.serdes = tuple(
-            SerDes(self._conn, *self.kind, serdes_xindex=serdes_xindex)
-            for serdes_xindex in range(self.info.capabilities.serdes_count)
-        )
+        # self.serdes = tuple(
+        #     SerDes(self._conn, *self.kind, serdes_xindex=serdes_xindex)
+        #     for serdes_xindex in range(self.info.capabilities.serdes_count)
+        # )
         self.l1 = L1(self._conn, self)
         return self
 
@@ -130,6 +130,12 @@ class PFreya800G4S1P_f(FamilyFreya):
     ...
 
 
+class PFreya800G4S2P_a(FamilyFreya):
+    """L23 port on Freya-800G-4S-2P[a] module.
+    """
+    ...
+
+
 class PFreya800G4S1POSFP_a(FamilyFreya):
     """L23 port on Freya-800G-4S-1P-OSFP[a] module.
     """

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/port_l23ve.py

@@ -11,8 +11,8 @@ from xoa_driver.internals.commands import (
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
 from xoa_driver.internals.utils.indices import index_manager as idx_mgr
-from xoa_driver.internals.hli_v1.indices.streams.base_stream import BaseStreamIdx
-from xoa_driver.internals.hli_v1.indices.filter.base_filter import BaseFilterIdx
+from xoa_driver.internals.hli.indices.streams.base_stream import BaseStreamIdx
+from xoa_driver.internals.hli.indices.filter.base_filter import BaseFilterIdx
 from xoa_driver.internals.state_storage import ports_state
 
 VEStreamIndices = idx_mgr.IndexManager[BaseStreamIdx]

xoa_driver/internals/{hli_v1 → hli}/ports/port_l47/main.py

@@ -30,11 +30,11 @@ from xoa_driver.internals.commands import (
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
 
-from xoa_driver.internals.hli_v1.ports import base_port
+from xoa_driver.internals.hli.ports import base_port
 from xoa_driver.internals.state_storage import ports_state
 from xoa_driver.internals.utils import attributes as utils
 from xoa_driver.internals.utils.indices import index_manager as im
-from xoa_driver.internals.hli_v1.indices.connection_group.cg import ConnectionGroupIdx
+from xoa_driver.internals.hli.indices.connection_group.cg import ConnectionGroupIdx
 
 from .counters import PCounters
 from .packet_engine import PacketEngine

xoa_driver/internals/{hli_v1 → hli}/testers/l23_tester.py

@@ -27,7 +27,7 @@ if TYPE_CHECKING:
 
 from xoa_driver.internals.core.transporter.logger import CustomLogger
 from xoa_driver.internals.state_storage import testers_state
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals import exceptions
 
 

xoa_driver/internals/{hli_v1 → hli}/testers/l47_tester.py

@@ -10,10 +10,10 @@ from xoa_driver.internals.commands import (
 )
 from xoa_driver.internals.core.transporter.logger import CustomLogger
 from xoa_driver.internals.utils.managers import modules_manager as mm
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals import exceptions
 if TYPE_CHECKING:
-    from xoa_driver.internals.hli_v1.modules import module_l47 as ml47
+    from xoa_driver.internals.hli.modules import module_l47 as ml47
 
 from xoa_driver.internals.state_storage import testers_state
 from ._base_tester import BaseTester

xoa_driver/internals/state_storage/modules_state.py

@@ -23,26 +23,46 @@ class ModuleLocalState:
         "reservation",
         "reserved_by",
         "model",
+        "model_name",
+        "serial_number",
+        "version_string",
+        "revision",
     )
 
     def __init__(self) -> None:
         self.reservation: enums.ReservedStatus = enums.ReservedStatus.RELEASED
         self.reserved_by: str = ""
         self.model: str = ""
+        self.model_name: str = ""
+        self.serial_number: str = ""
+        self.version_string: str = ""
+        self.revision: str = ""
 
     async def initiate(self, module) -> None:
         (
             reservation_r,
             reserved_by_r,
             model_r,
+            model_name_r,
+            serial_number_r,
+            version_string_r,
+            revision_r,
         ) = await funcs.apply(
             module.reservation.get(),
             module.reserved_by.get(),
             module.model.get(),
+            module.model_name.get(),
+            module.serial_number.get(),
+            module.version_str.get(),
+            module.revision.get(),
         )
         self.reservation = enums.ReservedStatus(reservation_r.operation)
         self.reserved_by = reserved_by_r.username
         self.model = model_r.model
+        self.model_name = enums.ModuleModelName(model_name_r.name).name
+        self.serial_number = serial_number_r.serial_number
+        self.version_string = version_string_r.version_str
+        self.revision = revision_r.revision
 
     def register_subscriptions(self, module) -> None:
         module._conn.subscribe(M_RESERVEDBY, utils.Update(self, "reserved_by", "username", module._check_identity))