tdl-xoa-driver 1.3.0__py3-none-any.whl → 1.4.0__py3-none-any.whl

xoa_driver/internals/core/transporter/_request_id_counter.py

@@ -12,7 +12,7 @@ class ReservedRequestID(IntEnum):
 
 
 class RequestIdCounter:
-    """Aggrigator of request ID."""
+    """Aggregator of request ID."""
     __slots__ = ("__req_id", "__lock",)
 
     def __init__(self) -> None:

xoa_driver/internals/core/transporter/protocol/payload/__init__.py

@@ -14,7 +14,8 @@ from .types import (
     XmpSequence,
     XmpShort,
     XmpStr,
-    Hex
+    Hex,
+    XmpJson,
 )
 
 __all__ = (
@@ -32,6 +33,7 @@ __all__ = (
     "XmpShort",
     "XmpStr",
     "Hex",
+    "XmpJson"
 )
 
 

xoa_driver/internals/core/transporter/protocol/payload/field.py

@@ -38,6 +38,7 @@ from .types import (
     # Preconverted Dynamic
     XmpStr,
     XmpSequence,
+    XmpJson,
 )
 
 
@@ -53,6 +54,7 @@ TYPES_FIXED = (
 TYPES_COMBI = (XmpHex,)
 TYPES_DYNAMIC = (XmpStr,)
 TYPES_COMPOSED = (XmpSequence,)
+TYPES_JSON = (XmpJson,)
 
 # Important: The instances of the FieldSpecs will live as a class variables
 # which mean wea are not able to update its attributes during runtime.
@@ -194,6 +196,43 @@ class HexSpec(FieldSpecs):
         return next(iter(struct.unpack_from(format, buffer, offset)), b"")
 
 
+class JsonSpec(FieldSpecs):
+    xmp_type: XmpJson
+
+    def __init__(
+        self,
+        xmp_type: XmpJson,
+        min_version: int | None = None,
+        max_version: int | None = None,
+        deprecated: bool = False,
+        deprecation_reason: str | None = None,
+    ) -> None:
+        super().__init__(xmp_type, min_version, max_version, deprecated, deprecation_reason)
+
+    @property
+    def is_dynamic(self) -> bool:
+        return True
+
+    def format(self, bsize: int | None = None) -> str:
+        return _build_format(self.xmp_type.data_format, bsize)
+
+    def calc_bsize(self, buff: memoryview | None = None, left_offset: int = 0) -> int | None:
+        if buff is None:
+            return None
+        return len(buff[left_offset:])
+
+    def get_context_formatter(self, client_type: Type[Any], is_response: bool) -> Callable[[Any], Any]:
+        if is_response:
+            return self.xmp_type.client_format
+        return self.xmp_type.server_format
+
+    def pack(self, format: str, val: bytes) -> bytes:
+        return val
+    
+    def unpack(self, format: str, buffer: memoryview, offset: int) -> Any:
+        return next(iter(struct.unpack_from(format, buffer, offset)), b"")
+    
+
 def _prepare_client_chunks(client_type: Type[Any], xmp_types_chunks: tuple) -> Callable[[Any], List[Tuple[Any, ...]]]:
     """Selecting the function for parsing data chunks from XMP types to Python types"""
     def converted_dcls(val_):
@@ -284,6 +323,8 @@ def field(
         specs_type = FieldSpecs
     elif isinstance(xmp_type, TYPES_COMBI):
         specs_type = HexSpec
+    elif isinstance(xmp_type, TYPES_JSON):
+        specs_type = JsonSpec
     else:
         return None
 

xoa_driver/internals/core/transporter/protocol/payload/types.py

@@ -10,6 +10,7 @@ from typing import (
     TypeVar,
     cast,
 )
+import json
 
 FMT_ORDER_NETWORK = '!'
 FMT_BYTES_STRING = 's'
@@ -21,6 +22,7 @@ FMT_INT = 'i'
 FMT_U_INT = 'I'
 FMT_SHORT = 'h'
 FMT_U_SHORT = 'H'
+FMT_BYTES_JSON = 's'
 
 # region Base Type
 
@@ -170,4 +172,21 @@ class XmpSequence(XmpType[tuple]):
         self.repetitions = None
         self.data_format = "".join(f"{t.repetitions or ''}{t.data_format}" for t in self.types_chunk)
 
+
+class XmpJson(XmpType[bytes]):
+    """Description class of XMP JSON type representation"""
+
+    __slots__ = ("min_len",)
+
+    def __init__(self, min_len: int | None = None) -> None:
+        self.data_format = FMT_BYTES_JSON
+        self.repetitions = None
+        self.min_len = min_len
+
+    def client_format(self, val: bytes) -> dict[str, Any]:
+        return json.loads(val.decode())
+
+    def server_format(self, val: dict) -> bytes:
+        return json.dumps(val).encode()
+
 # endregion

xoa_driver/internals/{hli_v1 → hli}/indices/filter/base_filter.py

@@ -62,4 +62,4 @@ class BaseFilterIdx(BaseIndex):
     @classmethod
     async def _new(cls: Type[FT], conn: "itf.IConnection", kind: "kind.IndicesKind", observer: "idx_obs.IndicesObserver") -> FT:
         await PF_CREATE(conn, *kind).set()
-        return cls(conn, kind, observer)
+        return cls(conn, kind, observer) # type: ignore

xoa_driver/internals/{hli_v1 → hli}/indices/length_term.py

@@ -46,4 +46,4 @@ class LengthTermIdx(BaseIndex):
     @classmethod
     async def _new(cls: Type[LT], conn: "itf.IConnection", kind: "kind.IndicesKind", observer: "idx_obs.IndicesObserver") -> LT:
         await PL_CREATE(conn, *kind).set()
-        return cls(conn, kind, observer)
+        return cls(conn, kind, observer) # type: ignore

xoa_driver/internals/{hli_v1 → hli}/indices/macsecscs/base_macsecsc.py

@@ -190,7 +190,7 @@ class BaseMacSecTxScIdx(BaseIndex):
     @classmethod
     async def _new(cls: Type[BS], conn: "itf.IConnection", kind: "kind.IndicesKind", observer: "idx_obs.IndicesObserver") -> BS:
         await P_MACSEC_TXSC_CREATE(conn, *kind).set()
-        return cls(conn, kind, observer)
+        return cls(conn, kind, observer) # type: ignore
 
 
 class BaseMacSecRxScIdx(BaseIndex):
@@ -221,4 +221,4 @@ class BaseMacSecRxScIdx(BaseIndex):
     @classmethod
     async def _new(cls: Type[BS], conn: "itf.IConnection", kind: "kind.IndicesKind", observer: "idx_obs.IndicesObserver") -> BS:
         await P_MACSEC_RXSC_CREATE(conn, *kind).set()
-        return cls(conn, kind, observer)
+        return cls(conn, kind, observer) # type: ignore

xoa_driver/internals/{hli_v1 → hli}/indices/match_term.py

@@ -61,4 +61,4 @@ class MatchTermIdx(BaseIndex):
     @classmethod
     async def _new(cls: Type[MT], conn: "itf.IConnection", kind: "kind.IndicesKind", observer: "idx_obs.IndicesObserver") -> MT:
         await PM_CREATE(conn, *kind).set()
-        return cls(conn, kind, observer)
+        return cls(conn, kind, observer) # type: ignore

xoa_driver/internals/{hli_v1 → hli}/indices/port_dataset.py

@@ -69,4 +69,4 @@ class PortDatasetIdx(BaseIndex):
     @classmethod
     async def _new(cls: Type[PD], conn: "itf.IConnection", kind: "kind.IndicesKind", observer: "idx_obs.IndicesObserver") -> PD:
         await PD_CREATE(conn, *kind).set()
-        return cls(conn, kind, observer)
+        return cls(conn, kind, observer) # type: ignore

xoa_driver/internals/{hli_v1 → hli}/indices/streams/base_stream.py

@@ -401,5 +401,5 @@ class BaseStreamIdx(BaseIndex):
     @classmethod
     async def _new(cls: Type[BS], conn: "itf.IConnection", kind: "kind.IndicesKind", observer: "idx_obs.IndicesObserver") -> BS:
         await PS_CREATE(conn, *kind).set()
-        return cls(conn, kind, observer)
+        return cls(conn, kind, observer) # type: ignore
 

xoa_driver/internals/{hli_v1 → hli}/modules/module_chimera.py

@@ -26,17 +26,17 @@ from xoa_driver.internals.commands import (
     M_RECONFIG_STATUS,
 )
 
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 from xoa_driver.internals.utils import attributes as utils
 from xoa_driver.internals.state_storage import modules_state
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1.modules.modules_l23.module_l23_base import MediaModule, CfpModule
+from xoa_driver.internals.hli.modules.modules_l23.module_l23_base import MediaModule, CfpModule
 from . import base_module as bm
 
 if typing.TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
-    from xoa_driver.internals.hli_v1.modules.modules_l23.module_l23_base import ModuleL23
+    from xoa_driver.internals.hli.modules.modules_l23.module_l23_base import ModuleL23
     from . import __interfaces as m_itf
 
 

xoa_driver/internals/{hli_v1 → hli}/modules/module_l47.py

@@ -37,7 +37,7 @@ from xoa_driver.internals.commands import (
     M4E_RESERVE,
     M4_TLS_CIPHER_SUITES,
 )
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils import attributes as utils
 from xoa_driver.internals.utils.managers import ports_manager as pm
 from xoa_driver.internals.state_storage import modules_state

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_combi.py

@@ -1,7 +1,7 @@
 import typing
 import functools
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.commands import P_CAPABILITIES
 from xoa_driver.internals.utils.managers import ports_manager as pm
 from xoa_driver.internals.utils.cap_id import CapID

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_d.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_e.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_f.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_g.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:
@@ -81,4 +81,19 @@ class MLoki100G3S1PB_b(ModuleL23):
             module_id=self.module_id,
             ports_count=self.ports_count
         )
-        """Port index manager of Loki-100G-3S-1P-B[b]"""
+        """Port index manager of Loki-100G-3S-1P-B[b]"""
+
+
+@typing.final
+@revisions.register_valkyrie_module(rev="Loki-100G-5S-4P[a]")
+class MLoki100G35S4P_a(ModuleL23):
+    """Test module Loki-100G-5S-4P[a]"""
+    def __init__(self, conn: "itf.IConnection", init_data: "m_itf.ModuleInitData") -> None:
+        super().__init__(conn, init_data)
+        self.ports: pm.PortsManager[ports.PLoki100G5S4P_a] = pm.PortsManager(
+            conn=conn,
+            ports_type=ports.PLoki100G5S4P_a,
+            module_id=self.module_id,
+            ports_count=self.ports_count
+        )
+        """Port index manager of Loki-100G-5S-4P[a]"""

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_h.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_i.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_j.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_k.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_l.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_l1.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_m.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/family_n.py

@@ -1,6 +1,6 @@
 import typing
 from xoa_driver import ports
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals.utils.managers import ports_manager as pm
 
 if typing.TYPE_CHECKING:

xoa_driver/internals/{hli_v1 → hli}/modules/modules_l23/module_l23_base.py

@@ -42,7 +42,7 @@ from .. import __interfaces as m_itf
 
 if typing.TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
-    from xoa_driver.internals.hli_v1.modules.module_chimera import ModuleChimera
+    from xoa_driver.internals.hli.modules.module_chimera import ModuleChimera
 
 
 class TXClock:

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/bases/port_l23.py

@@ -55,12 +55,12 @@ from xoa_driver.internals.commands import (
 )
 if typing.TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
-from xoa_driver.internals.hli_v1.ports import base_port
+from xoa_driver.internals.hli.ports import base_port
 from xoa_driver.internals.utils import attributes as utils
 from xoa_driver.internals.utils.indices import index_manager as idx_mgr
 from xoa_driver.internals.state_storage import ports_state
-from xoa_driver.internals.hli_v1.indices.length_term import LengthTermIdx
-from xoa_driver.internals.hli_v1.indices.match_term import MatchTermIdx
+from xoa_driver.internals.hli.indices.length_term import LengthTermIdx
+from xoa_driver.internals.hli.indices.match_term import MatchTermIdx
 
 from .port_capture import PortCapture
 

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/bases/port_l23_genuine.py

@@ -16,11 +16,11 @@ from xoa_driver.internals.commands import (
 )
 from xoa_driver.internals.utils import attributes as utils
 from xoa_driver.internals.utils.indices import index_manager as idx_mgr
-from xoa_driver.internals.hli_v1.indices.streams.genuine_stream import GenuineStreamIdx
-from xoa_driver.internals.hli_v1.indices.filter.genuine_filter import GenuineFilterIdx
-from xoa_driver.internals.hli_v1.indices.port_dataset import PortDatasetIdx
+from xoa_driver.internals.hli.indices.streams.genuine_stream import GenuineStreamIdx
+from xoa_driver.internals.hli.indices.filter.genuine_filter import GenuineFilterIdx
+from xoa_driver.internals.hli.indices.port_dataset import PortDatasetIdx
 from xoa_driver.internals.state_storage import ports_state
-from xoa_driver.internals.hli_v1.indices.macsecscs.genuine_macsecsc import GenuineMacSecTxScIdx, GenuineMacSecRxScIdx
+from xoa_driver.internals.hli.indices.macsecscs.genuine_macsecsc import GenuineMacSecTxScIdx, GenuineMacSecRxScIdx
 
 from .port_l23 import (
     BasePortL23,

xoa_driver/internals/hli/ports/port_l23/bases/port_transceiver.py

@@ -0,0 +1,247 @@
+from typing import TYPE_CHECKING
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+from xoa_driver.internals.commands import (
+    PX_RW,
+    PX_MII,
+    PX_TEMPERATURE,
+    PX_RW_SEQ,
+    PX_I2C_CONFIG,
+    PX_RW_SEQ_BANK,
+    PX_CDB_SUPPORT,
+    PX_CDB_ABORT_PROCESSING,
+    PX_CDB_CHANGE_PASSWORD,
+    PX_CDB_ENTER_PASSWORD,
+    PX_CDB_QUERY_STATUS,
+    PX_CDB_EXTERNAL_FEATURES,
+    PX_CDB_FW_MGMT_FEATURES,
+    PX_CDB_GET_APP_ATTRIBUTES,
+    PX_CDB_GET_IF_CODE_DESCR,
+    PX_CDB_MODULE_FEATURES,
+    PX_CDB_SEC_FEAT_CAPABILITIES,
+    PX_CDB_ABORT_FW_DOWNLOAD,
+    PX_CDB_COMMIT_FW_IMAGE,
+    PX_CDB_COMPLETE_FW_DOWNLOAD,
+    PX_CDB_COPY_FW_IMAGE,
+    PX_CDB_GET_FW_INFO,
+    PX_CDB_READ_FW_BLOCK_EPL,
+    PX_CDB_READ_FW_BLOCK_LPL,
+    PX_CDB_RUN_FW_IMAGE,
+    PX_CDB_START_FW_DOWNLOAD,
+    PX_CDB_WRITE_FW_BLOCK_EPL,
+    PX_CDB_WRITE_FW_BLOCK_LPL,
+    PX_CUST_CMD,
+)
+
+
+class PortTransceiver:
+    """Transceiver access class."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+
+        self.i2c_config = PX_I2C_CONFIG(conn, module_id, port_id)
+        """
+        Access speed on a transceiver I2C access in the unit of KHz. Default to 100. 
+        
+        When the transceiver is plugged out and in again, the speed will be reset to the default value 100. The speed has a minimum and a maximum, which can be obtained from port.capabilities(). 
+        
+        The I2C speed configuration will not be included in the port configuration file (.xpc). When you load a port configuration to a port, the transceiver I2C access speed will be reset to default.
+        """
+
+        self.temperature = PX_TEMPERATURE(conn, module_id, port_id)
+        """Transceiver temperature in Celsius.
+
+        Temperature value before the decimal digit, and 1/256th of a degree Celsius after the decimal digit.
+        """
+
+        self.cmis = CMIS(conn, module_id, port_id)
+        """
+        Access CMIS interface.
+        """
+
+    def access_rw(self, page_address: int, register_address: int) -> "PX_RW":
+        """Access to register interface by the transceiver.
+
+        :param page_address: page address
+        :type page_address: int
+        :param register_address: register address
+        :type register_address: int
+        :return: transceiver register values
+        :rtype: PX_RW
+        """
+
+        return PX_RW(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            page_address,
+            register_address
+        )
+
+    def access_mii(self, register_address: int) -> "PX_MII":
+        """Access to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param register_address: register address
+        :type register_address: int
+        :return: register values
+        :rtype: PX_MII
+        """
+        return PX_MII(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            register_address
+        )
+
+    def access_rw_seq(self, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ":
+        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param page_address: page address (0-255)
+        :type page_address: int
+        :param register_address: register address (0-255)
+        :type register_address: int
+        :param byte_count: the number of bytes to read/write
+        :type byte_count: int
+        :return: transceiver register values
+        :rtype: PX_RW_SEQ
+        """
+        return PX_RW_SEQ(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            page_address,
+            register_address,
+            byte_count
+        )
+    
+    def access_rw_seq_bank(self, bank_address: int, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ_BANK":
+        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param bank_address: bank address (0-255)
+        :type bank_address: int
+        :param page_address: page address (0-255)
+        :type page_address: int
+        :param register_address: register address (0-255)
+        :type register_address: int
+        :param byte_count: the number of bytes to read/write
+        :type byte_count: int
+        :return: transceiver register values
+        :rtype: PX_RW_SEQ_BANK
+        """
+        return PX_RW_SEQ_BANK(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            bank_address,
+            page_address,
+            register_address,
+            byte_count
+        )
+
+class CMIS():
+    """CMIS access class.
+    """
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+
+        self.cdb_instances_supported = PX_CDB_SUPPORT(conn, module_id, port_id)
+        """Return the number of supported CDB instances.
+        """
+
+    def cdb(self, cdb_instance_id: int) -> "CDB":
+        """Access CMIS CDB command interface.
+
+        :param cdb_instance_id: 0 for CDB Instance 1, 1 for CDB Instance 2
+        :type cdb_instance_id: int
+        """
+        return CDB(self.__conn, self.__module_id, self.__port_id, cdb_instance_id)
+        
+
+class CDB():
+    """CMIS CDB command access class.
+    """
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, cdb_instance_id: int) -> None:
+
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+        self.__cdb_instance_id = cdb_instance_id
+
+        # CDB Module Commands
+        self.cmd_0000h_query_status = PX_CDB_QUERY_STATUS(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0000h: Query Status
+        """
+        self.cmd_0001h_enter_password = PX_CDB_ENTER_PASSWORD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0001h: Enter Password
+        """
+        self.cmd_0002h_change_password = PX_CDB_CHANGE_PASSWORD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0002h: Change Password
+        """
+        self.cmd_0004h_abort_processing = PX_CDB_ABORT_PROCESSING(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0004h: Abort Processing
+        """ 
+
+        # CDB Features and Capabilities Inquiry Commands
+        self.cmd_0040h_module_features = PX_CDB_MODULE_FEATURES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0040h: Module Features
+        """
+        self.cmd_0041h_fw_mgmt_features = PX_CDB_FW_MGMT_FEATURES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0041h: Firmware Management Features
+        """
+        self.cmd_0044h_sec_feat_capabilities = PX_CDB_SEC_FEAT_CAPABILITIES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0044h: Security Features and Capabilities
+        """
+        self.cmd_0045h_external_features = PX_CDB_EXTERNAL_FEATURES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0045h: Externally Defined Features
+        """
+        self.cmd_0050h_get_app_attributes = PX_CDB_GET_APP_ATTRIBUTES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0050h: Get Application Attributes
+        """
+        self.cmd_0051h_get_if_code_descr = PX_CDB_GET_IF_CODE_DESCR(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0051h: Get Interface Code Description
+        """
+
+        # CDB Firmware Management Commands
+        self.cmd_0100h_get_firmware_info = PX_CDB_GET_FW_INFO(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0100h: Get Firmware Info
+        """
+        self.cmd_0101h_start_firmware_download = PX_CDB_START_FW_DOWNLOAD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0101h: Start Firmware Download
+        """
+        self.cmd_0102h_abort_firmware_download = PX_CDB_ABORT_FW_DOWNLOAD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0102h: Abort Firmware Download
+        """
+        self.cmd_0103h_write_firmware_block_lpl = PX_CDB_WRITE_FW_BLOCK_LPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0103h: Write Firmware Block LPL
+        """
+        self.cmd_0104h_write_firmware_block_epl = PX_CDB_WRITE_FW_BLOCK_EPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0104h: Write Firmware Block EPL
+        """
+        self.cmd_0105h_read_firmware_block_lpl = PX_CDB_READ_FW_BLOCK_LPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0105h: Read Firmware Block LPL
+        """
+        self.cmd_0106h_read_firmware_block_epl = PX_CDB_READ_FW_BLOCK_EPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0106h: Read Firmware Block EPL
+        """
+        self.cmd_0107h_complete_firmware_download = PX_CDB_COMPLETE_FW_DOWNLOAD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0107h: Complete Firmware Download
+        """
+        self.cmd_0108h_copy_firmware_image = PX_CDB_COPY_FW_IMAGE(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0108h: Copy Firmware Image
+        """
+        self.cmd_0109h_run_firmware_image = PX_CDB_RUN_FW_IMAGE(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0109h: Run Firmware Image
+        """
+        self.cmd_010ah_commit_firmware_image = PX_CDB_COMMIT_FW_IMAGE(conn, module_id, port_id, cdb_instance_id)
+        """CMD 010Ah: Commit Firmware Image
+        """
+        
+        # Custom Commands
+        self.custom_cmd = PX_CUST_CMD(conn, module_id, port_id, cdb_instance_id)
+        """Defnes the custom CDB commdand (CMD and Reply) to be sent to the CDB instance.
+        """

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/bases/port_transmission_statistics.py

@@ -4,7 +4,7 @@ from typing import (
 )
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
-    from xoa_driver.internals.hli_v1.indices.streams.genuine_stream import GenuineStreamIdx
+    from xoa_driver.internals.hli.indices.streams.genuine_stream import GenuineStreamIdx
 from xoa_driver.internals.commands import (
     PT_TOTAL,
     PT_NOTPLD,