tdl-xoa-driver 1.2.0__py3-none-any.whl → 1.4.0__py3-none-any.whl

xoa_driver/internals/hli/ports/port_l23/bases/port_transceiver.py

@@ -0,0 +1,247 @@
+from typing import TYPE_CHECKING
+if TYPE_CHECKING:
+    from xoa_driver.internals.core import interfaces as itf
+from xoa_driver.internals.commands import (
+    PX_RW,
+    PX_MII,
+    PX_TEMPERATURE,
+    PX_RW_SEQ,
+    PX_I2C_CONFIG,
+    PX_RW_SEQ_BANK,
+    PX_CDB_SUPPORT,
+    PX_CDB_ABORT_PROCESSING,
+    PX_CDB_CHANGE_PASSWORD,
+    PX_CDB_ENTER_PASSWORD,
+    PX_CDB_QUERY_STATUS,
+    PX_CDB_EXTERNAL_FEATURES,
+    PX_CDB_FW_MGMT_FEATURES,
+    PX_CDB_GET_APP_ATTRIBUTES,
+    PX_CDB_GET_IF_CODE_DESCR,
+    PX_CDB_MODULE_FEATURES,
+    PX_CDB_SEC_FEAT_CAPABILITIES,
+    PX_CDB_ABORT_FW_DOWNLOAD,
+    PX_CDB_COMMIT_FW_IMAGE,
+    PX_CDB_COMPLETE_FW_DOWNLOAD,
+    PX_CDB_COPY_FW_IMAGE,
+    PX_CDB_GET_FW_INFO,
+    PX_CDB_READ_FW_BLOCK_EPL,
+    PX_CDB_READ_FW_BLOCK_LPL,
+    PX_CDB_RUN_FW_IMAGE,
+    PX_CDB_START_FW_DOWNLOAD,
+    PX_CDB_WRITE_FW_BLOCK_EPL,
+    PX_CDB_WRITE_FW_BLOCK_LPL,
+    PX_CUST_CMD,
+)
+
+
+class PortTransceiver:
+    """Transceiver access class."""
+
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+
+        self.i2c_config = PX_I2C_CONFIG(conn, module_id, port_id)
+        """
+        Access speed on a transceiver I2C access in the unit of KHz. Default to 100. 
+        
+        When the transceiver is plugged out and in again, the speed will be reset to the default value 100. The speed has a minimum and a maximum, which can be obtained from port.capabilities(). 
+        
+        The I2C speed configuration will not be included in the port configuration file (.xpc). When you load a port configuration to a port, the transceiver I2C access speed will be reset to default.
+        """
+
+        self.temperature = PX_TEMPERATURE(conn, module_id, port_id)
+        """Transceiver temperature in Celsius.
+
+        Temperature value before the decimal digit, and 1/256th of a degree Celsius after the decimal digit.
+        """
+
+        self.cmis = CMIS(conn, module_id, port_id)
+        """
+        Access CMIS interface.
+        """
+
+    def access_rw(self, page_address: int, register_address: int) -> "PX_RW":
+        """Access to register interface by the transceiver.
+
+        :param page_address: page address
+        :type page_address: int
+        :param register_address: register address
+        :type register_address: int
+        :return: transceiver register values
+        :rtype: PX_RW
+        """
+
+        return PX_RW(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            page_address,
+            register_address
+        )
+
+    def access_mii(self, register_address: int) -> "PX_MII":
+        """Access to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param register_address: register address
+        :type register_address: int
+        :return: register values
+        :rtype: PX_MII
+        """
+        return PX_MII(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            register_address
+        )
+
+    def access_rw_seq(self, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ":
+        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param page_address: page address (0-255)
+        :type page_address: int
+        :param register_address: register address (0-255)
+        :type register_address: int
+        :param byte_count: the number of bytes to read/write
+        :type byte_count: int
+        :return: transceiver register values
+        :rtype: PX_RW_SEQ
+        """
+        return PX_RW_SEQ(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            page_address,
+            register_address,
+            byte_count
+        )
+    
+    def access_rw_seq_bank(self, bank_address: int, page_address: int, register_address: int, byte_count: int) -> "PX_RW_SEQ_BANK":
+        """Sequential read/write a number of bytes to the register interface supported by the media-independent interface (MII) transceiver.
+
+        :param bank_address: bank address (0-255)
+        :type bank_address: int
+        :param page_address: page address (0-255)
+        :type page_address: int
+        :param register_address: register address (0-255)
+        :type register_address: int
+        :param byte_count: the number of bytes to read/write
+        :type byte_count: int
+        :return: transceiver register values
+        :rtype: PX_RW_SEQ_BANK
+        """
+        return PX_RW_SEQ_BANK(
+            self.__conn,
+            self.__module_id,
+            self.__port_id,
+            bank_address,
+            page_address,
+            register_address,
+            byte_count
+        )
+
+class CMIS():
+    """CMIS access class.
+    """
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int) -> None:
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+
+        self.cdb_instances_supported = PX_CDB_SUPPORT(conn, module_id, port_id)
+        """Return the number of supported CDB instances.
+        """
+
+    def cdb(self, cdb_instance_id: int) -> "CDB":
+        """Access CMIS CDB command interface.
+
+        :param cdb_instance_id: 0 for CDB Instance 1, 1 for CDB Instance 2
+        :type cdb_instance_id: int
+        """
+        return CDB(self.__conn, self.__module_id, self.__port_id, cdb_instance_id)
+        
+
+class CDB():
+    """CMIS CDB command access class.
+    """
+    def __init__(self, conn: "itf.IConnection", module_id: int, port_id: int, cdb_instance_id: int) -> None:
+
+        self.__conn = conn
+        self.__module_id = module_id
+        self.__port_id = port_id
+        self.__cdb_instance_id = cdb_instance_id
+
+        # CDB Module Commands
+        self.cmd_0000h_query_status = PX_CDB_QUERY_STATUS(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0000h: Query Status
+        """
+        self.cmd_0001h_enter_password = PX_CDB_ENTER_PASSWORD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0001h: Enter Password
+        """
+        self.cmd_0002h_change_password = PX_CDB_CHANGE_PASSWORD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0002h: Change Password
+        """
+        self.cmd_0004h_abort_processing = PX_CDB_ABORT_PROCESSING(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0004h: Abort Processing
+        """ 
+
+        # CDB Features and Capabilities Inquiry Commands
+        self.cmd_0040h_module_features = PX_CDB_MODULE_FEATURES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0040h: Module Features
+        """
+        self.cmd_0041h_fw_mgmt_features = PX_CDB_FW_MGMT_FEATURES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0041h: Firmware Management Features
+        """
+        self.cmd_0044h_sec_feat_capabilities = PX_CDB_SEC_FEAT_CAPABILITIES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0044h: Security Features and Capabilities
+        """
+        self.cmd_0045h_external_features = PX_CDB_EXTERNAL_FEATURES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0045h: Externally Defined Features
+        """
+        self.cmd_0050h_get_app_attributes = PX_CDB_GET_APP_ATTRIBUTES(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0050h: Get Application Attributes
+        """
+        self.cmd_0051h_get_if_code_descr = PX_CDB_GET_IF_CODE_DESCR(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0051h: Get Interface Code Description
+        """
+
+        # CDB Firmware Management Commands
+        self.cmd_0100h_get_firmware_info = PX_CDB_GET_FW_INFO(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0100h: Get Firmware Info
+        """
+        self.cmd_0101h_start_firmware_download = PX_CDB_START_FW_DOWNLOAD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0101h: Start Firmware Download
+        """
+        self.cmd_0102h_abort_firmware_download = PX_CDB_ABORT_FW_DOWNLOAD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0102h: Abort Firmware Download
+        """
+        self.cmd_0103h_write_firmware_block_lpl = PX_CDB_WRITE_FW_BLOCK_LPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0103h: Write Firmware Block LPL
+        """
+        self.cmd_0104h_write_firmware_block_epl = PX_CDB_WRITE_FW_BLOCK_EPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0104h: Write Firmware Block EPL
+        """
+        self.cmd_0105h_read_firmware_block_lpl = PX_CDB_READ_FW_BLOCK_LPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0105h: Read Firmware Block LPL
+        """
+        self.cmd_0106h_read_firmware_block_epl = PX_CDB_READ_FW_BLOCK_EPL(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0106h: Read Firmware Block EPL
+        """
+        self.cmd_0107h_complete_firmware_download = PX_CDB_COMPLETE_FW_DOWNLOAD(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0107h: Complete Firmware Download
+        """
+        self.cmd_0108h_copy_firmware_image = PX_CDB_COPY_FW_IMAGE(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0108h: Copy Firmware Image
+        """
+        self.cmd_0109h_run_firmware_image = PX_CDB_RUN_FW_IMAGE(conn, module_id, port_id, cdb_instance_id)
+        """CMD 0109h: Run Firmware Image
+        """
+        self.cmd_010ah_commit_firmware_image = PX_CDB_COMMIT_FW_IMAGE(conn, module_id, port_id, cdb_instance_id)
+        """CMD 010Ah: Commit Firmware Image
+        """
+        
+        # Custom Commands
+        self.custom_cmd = PX_CUST_CMD(conn, module_id, port_id, cdb_instance_id)
+        """Defnes the custom CDB commdand (CMD and Reply) to be sent to the CDB instance.
+        """

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/bases/port_transmission_statistics.py

@@ -4,7 +4,7 @@ from typing import (
 )
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
-    from xoa_driver.internals.hli_v1.indices.streams.genuine_stream import GenuineStreamIdx
+    from xoa_driver.internals.hli.indices.streams.genuine_stream import GenuineStreamIdx
 from xoa_driver.internals.commands import (
     PT_TOTAL,
     PT_NOTPLD,

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/chimera/port_chimera.py

@@ -14,7 +14,7 @@ from xoa_driver.internals.commands import (
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
 
-from xoa_driver.internals.hli_v1.ports import base_port
+from xoa_driver.internals.hli.ports import base_port
 from xoa_driver.internals.utils import attributes as utils
 from xoa_driver.internals.state_storage import ports_state
 from ..pcs_pma_ijkl_chimera import PcsPma

xoa_driver/internals/{hli_v2 → hli}/ports/port_l23/family_g.py

@@ -75,3 +75,8 @@ class PLoki100G3S1PB_b(FamilyG):
     """L23 port on Loki-100G-3S-1P-B[b] module.
     """
     ...
+
+class PLoki100G5S4P_a(FamilyG):
+    """L23 port on Loki-100G-5S-4P[a] module.
+    """
+    ...

xoa_driver/internals/{hli_v1 → hli}/ports/port_l23/port_l23ve.py

@@ -11,8 +11,8 @@ from xoa_driver.internals.commands import (
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
 from xoa_driver.internals.utils.indices import index_manager as idx_mgr
-from xoa_driver.internals.hli_v1.indices.streams.base_stream import BaseStreamIdx
-from xoa_driver.internals.hli_v1.indices.filter.base_filter import BaseFilterIdx
+from xoa_driver.internals.hli.indices.streams.base_stream import BaseStreamIdx
+from xoa_driver.internals.hli.indices.filter.base_filter import BaseFilterIdx
 from xoa_driver.internals.state_storage import ports_state
 
 VEStreamIndices = idx_mgr.IndexManager[BaseStreamIdx]

xoa_driver/internals/{hli_v1 → hli}/ports/port_l47/main.py

@@ -30,11 +30,11 @@ from xoa_driver.internals.commands import (
 if TYPE_CHECKING:
     from xoa_driver.internals.core import interfaces as itf
 
-from xoa_driver.internals.hli_v1.ports import base_port
+from xoa_driver.internals.hli.ports import base_port
 from xoa_driver.internals.state_storage import ports_state
 from xoa_driver.internals.utils import attributes as utils
 from xoa_driver.internals.utils.indices import index_manager as im
-from xoa_driver.internals.hli_v1.indices.connection_group.cg import ConnectionGroupIdx
+from xoa_driver.internals.hli.indices.connection_group.cg import ConnectionGroupIdx
 
 from .counters import PCounters
 from .packet_engine import PacketEngine

xoa_driver/internals/{hli_v1 → hli}/testers/l23_tester.py

@@ -27,7 +27,7 @@ if TYPE_CHECKING:
 
 from xoa_driver.internals.core.transporter.logger import CustomLogger
 from xoa_driver.internals.state_storage import testers_state
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals import exceptions
 
 

xoa_driver/internals/{hli_v1 → hli}/testers/l47_tester.py

@@ -10,10 +10,10 @@ from xoa_driver.internals.commands import (
 )
 from xoa_driver.internals.core.transporter.logger import CustomLogger
 from xoa_driver.internals.utils.managers import modules_manager as mm
-from xoa_driver.internals.hli_v1 import revisions
+from xoa_driver.internals.hli import revisions
 from xoa_driver.internals import exceptions
 if TYPE_CHECKING:
-    from xoa_driver.internals.hli_v1.modules import module_l47 as ml47
+    from xoa_driver.internals.hli.modules import module_l47 as ml47
 
 from xoa_driver.internals.state_storage import testers_state
 from ._base_tester import BaseTester

xoa_driver/internals/state_storage/modules_state.py

@@ -80,7 +80,7 @@ class MediaInfo:
     :rtype: MediaConfigurationType
     """
 
-    available_speeds: List["ModuleSpeed"] = field(default_factory=list)
+    supported_configs: List["ModuleSpeed"] = field(default_factory=list)
     """List of module's port-speed information
 
     :return: list of module's port-speed information

xoa_driver/misc.py

@@ -12,24 +12,19 @@ from .internals.commands.subtypes import (
     QueueStatsElem,
 )
 
-import sys
-
-if "xoa_driver.v2" in sys.modules:
-    raise ImportError("\33[31mOnly Single interface version is allowed to being use at the same time.\33[0m")
-
 # indices types
-from .internals.hli_v1.indices.connection_group.cg import ConnectionGroupIdx as ConnectionGroup
-from .internals.hli_v1.indices.filter.base_filter import BaseFilterIdx as BasePortFilter
-from .internals.hli_v1.indices.filter.genuine_filter import GenuineFilterIdx as GenuinePortFilter
-from .internals.hli_v1.indices.length_term import LengthTermIdx as LengthTerm
-from .internals.hli_v1.indices.match_term import MatchTermIdx as MatchTerm
-from .internals.hli_v1.indices.port_dataset import PortDatasetIdx as PortDataset
-from .internals.hli_v1.indices.streams.base_stream import BaseStreamIdx as BaseStream
-from .internals.hli_v1.indices.streams.genuine_stream import GenuineStreamIdx as GenuineStream
-from .internals.hli_v1.ports.port_l23.chimera.port_emulation import CFlow as ImpairmentFlow
-from .internals.hli_v1.ports.port_l23.chimera.filter_definition.general import ModeBasic as BasicImpairmentFlowFilter
-from .internals.hli_v1.ports.port_l23.chimera.filter_definition.general import ModeExtended as ExtendedImpairmentFlowFilter
-from xoa_driver.internals.hli_v1.indices.macsecscs.genuine_macsecsc import GenuineMacSecTxScIdx, GenuineMacSecRxScIdx
+from .internals.hli.indices.connection_group.cg import ConnectionGroupIdx as ConnectionGroup
+from .internals.hli.indices.filter.base_filter import BaseFilterIdx as BasePortFilter
+from .internals.hli.indices.filter.genuine_filter import GenuineFilterIdx as GenuinePortFilter
+from .internals.hli.indices.length_term import LengthTermIdx as LengthTerm
+from .internals.hli.indices.match_term import MatchTermIdx as MatchTerm
+from .internals.hli.indices.port_dataset import PortDatasetIdx as PortDataset
+from .internals.hli.indices.streams.base_stream import BaseStreamIdx as BaseStream
+from .internals.hli.indices.streams.genuine_stream import GenuineStreamIdx as GenuineStream
+from .internals.hli.ports.port_l23.chimera.port_emulation import CFlow as ImpairmentFlow
+from .internals.hli.ports.port_l23.chimera.filter_definition.general import ModeBasic as BasicImpairmentFlowFilter
+from .internals.hli.ports.port_l23.chimera.filter_definition.general import ModeExtended as ExtendedImpairmentFlowFilter
+from xoa_driver.internals.hli.indices.macsecscs.genuine_macsecsc import GenuineMacSecTxScIdx, GenuineMacSecRxScIdx
 
 
 __all__ = (

xoa_driver/modules.py

@@ -1,24 +1,20 @@
 #: All available test module types.
-import sys
 
-if "xoa_driver.v2" in sys.modules:
-    raise ImportError("\33[31mOnly Single interface version is allowed to being use at the same time.\33[0m")
-
-from .internals.hli_v1.modules.modules_l23.module_l23_base import ModuleL23
-from .internals.hli_v1.modules.modules_l23.family_d import (
+from .internals.hli.modules.modules_l23.module_l23_base import ModuleL23
+from .internals.hli.modules.modules_l23.family_d import (
     MOdin1G3S2PT,
     MOdin1G3S6P,
     MOdin1G3S6P_b,
     MOdin1G3S6PE,
 )
-from .internals.hli_v1.modules.modules_l23.family_e import (
+from .internals.hli.modules.modules_l23.family_e import (
     MOdin5G4S6PCU,
     MOdin10G3S2PCU,
     MOdin10G3S6PCU,
     MOdin10G5S6PCU,
     MOdin10G5S6PCU_b,
 )
-from .internals.hli_v1.modules.modules_l23.family_f import (
+from .internals.hli.modules.modules_l23.family_f import (
     MOdin10G1S2P,
     MOdin10G1S2P_b,
     MOdin10G1S2P_c,
@@ -29,29 +25,29 @@ from .internals.hli_v1.modules.modules_l23.family_f import (
     MOdin10G1S12P,
     MOdin10G6S6P_a,
 )
-from .internals.hli_v1.modules.modules_l23.family_g import (
+from .internals.hli.modules.modules_l23.family_g import (
     MLoki100G3S1P,
     MLoki100G3S1P_b,
     MLoki100G3S1PSE,
     MLoki100G3S1PB,
     MLoki100G3S1PB_b,
 )
-from .internals.hli_v1.modules.modules_l23.family_h import (
+from .internals.hli.modules.modules_l23.family_h import (
     MLoki100G5S1P,
     MOdin100G3S1P,
 )
-from .internals.hli_v1.modules.modules_l23.family_i import MLoki100G5S2P
-from .internals.hli_v1.modules.modules_l23.family_j import MThor100G5S4P
-from .internals.hli_v1.modules.modules_l23.family_k import (
+from .internals.hli.modules.modules_l23.family_i import MLoki100G5S2P
+from .internals.hli.modules.modules_l23.family_j import MThor100G5S4P
+from .internals.hli.modules.modules_l23.family_k import (
     MThor400G7S1P,
     MThor400G7S1PLE,
 )
-from .internals.hli_v1.modules.modules_l23.family_l import (
+from .internals.hli.modules.modules_l23.family_l import (
     MThor400G7S1P_b,
     MThor400G7S1P_c,
     MThor400G7S1P_d,
 )
-from .internals.hli_v1.modules.modules_l23.family_l1 import (
+from .internals.hli.modules.modules_l23.family_l1 import (
     MFreya800G1S1P_a,
     MFreya800G1S1P_b,
     MFreya800G1S1POSFP_a,
@@ -101,24 +97,24 @@ from .internals.hli_v1.modules.modules_l23.family_l1 import (
     MFreya800G4S1POSFP_e_g2,
     MFreya800G4S1POSFP_f_g2,
 )
-from .internals.hli_v1.modules.modules_l23.family_m import MOdin1G3S6PT1RJ45
-from .internals.hli_v1.modules.modules_l23.family_n import (
+from .internals.hli.modules.modules_l23.family_m import MOdin1G3S6PT1RJ45
+from .internals.hli.modules.modules_l23.family_n import (
     MOdin40G2S2P,
     MOdin40G2S2PB,
 )
-from .internals.hli_v1.modules.modules_l23.family_combi import (
+from .internals.hli.modules.modules_l23.family_combi import (
     MOdin10G4S2PCombi,
     MOdin10G4S2PCombi_b,
 )
-from .internals.hli_v1.modules.module_l23ve import ModuleL23VE
-from .internals.hli_v1.modules.module_chimera import (
+from .internals.hli.modules.module_l23ve import ModuleL23VE
+from .internals.hli.modules.module_chimera import (
     ModuleChimera,
     MChi100G5S2P,
     MChi100G5S2P_b,
     MChi40G2S2P,
 )
-from .internals.hli_v1.modules.module_l47 import ModuleL47
-from .internals.hli_v1.modules.module_l47ve import ModuleL47VE
+from .internals.hli.modules.module_l47 import ModuleL47
+from .internals.hli.modules.module_l47ve import ModuleL47VE
 
 import typing
 

xoa_driver/ports.py

@@ -1,37 +1,33 @@
 #: All available test port types.
-import sys
-
-if "xoa_driver.v2" in sys.modules:
-    raise ImportError("\33[31mOnly Single interface version is allowed to being use at the same time.\33[0m")
 
 import typing
 
-from .internals.hli_v1.ports.port_l47.main import PortL47
+from .internals.hli.ports.port_l47.main import PortL47
 
-from .internals.hli_v1.ports.port_l23.port_l23ve import PortL23VE
-from .internals.hli_v1.ports.port_l23.chimera.port_chimera import (
+from .internals.hli.ports.port_l23.port_l23ve import PortL23VE
+from .internals.hli.ports.port_l23.chimera.port_chimera import (
     PortChimera,
     PChi100G5S2P,
     PChi100G5S2P_b,
     PChi40G2S2P,
 )
 
-from .internals.hli_v1.ports.port_l23.bases.port_l23 import BasePortL23
-from xoa_driver.internals.hli_v1.ports.port_l23.family_combi import (
+from .internals.hli.ports.port_l23.bases.port_l23 import BasePortL23
+from xoa_driver.internals.hli.ports.port_l23.family_combi import (
     POdin1G4S4PCombi,
     POdin1G4S4PCombi_b,
     POdin10G4S2PCombi,
     POdin10G4S2PCombi_b,
 )
 
-from xoa_driver.internals.hli_v1.ports.port_l23.family_d import (
+from xoa_driver.internals.hli.ports.port_l23.family_d import (
     POdin1G3S2PT,
     POdin1G3S6P,
     POdin1G3S6P_b,
     POdin1G3S6PE,
 )
 
-from xoa_driver.internals.hli_v1.ports.port_l23.family_e import (
+from xoa_driver.internals.hli.ports.port_l23.family_e import (
     POdin5G4S6PCU,
     POdin10G3S2PCU,
     POdin10G3S6PCU,
@@ -39,7 +35,7 @@ from xoa_driver.internals.hli_v1.ports.port_l23.family_e import (
     POdin10G5S6PCU_b,
 )
 
-from xoa_driver.internals.hli_v1.ports.port_l23.family_f import (
+from xoa_driver.internals.hli.ports.port_l23.family_f import (
     POdin10G1S2P,
     POdin10G1S2P_b,
     POdin10G1S2P_c,
@@ -53,32 +49,33 @@ from xoa_driver.internals.hli_v1.ports.port_l23.family_f import (
     POdin10G6S6P_a,
 )
 
-from xoa_driver.internals.hli_v1.ports.port_l23.family_g import (
+from xoa_driver.internals.hli.ports.port_l23.family_g import (
     PLoki100G3S1P,
     PLoki100G3S1P_b,
     PLoki100G3S1PSE,
     PLoki100G3S1PB,
     PLoki100G3S1PB_b,
+    PLoki100G5S4P_a,
 )
 
-from xoa_driver.internals.hli_v1.ports.port_l23.family_h import (
+from xoa_driver.internals.hli.ports.port_l23.family_h import (
     PLoki100G5S1P,
     POdin100G3S1P,
 )
 
-from xoa_driver.internals.hli_v1.ports.port_l23.family_i import PLoki100G5S2P
-from xoa_driver.internals.hli_v1.ports.port_l23.family_j import PThor100G5S4P
-from xoa_driver.internals.hli_v1.ports.port_l23.family_k import (
+from xoa_driver.internals.hli.ports.port_l23.family_i import PLoki100G5S2P
+from xoa_driver.internals.hli.ports.port_l23.family_j import PThor100G5S4P
+from xoa_driver.internals.hli.ports.port_l23.family_k import (
     PThor400G7S1P,
     PThor400G7S1PLE,
 )
-from xoa_driver.internals.hli_v1.ports.port_l23.family_l import (
+from xoa_driver.internals.hli.ports.port_l23.family_l import (
     PThor400G7S1P_b,
     PThor400G7S1P_c,
     PThor400G7S1P_d,
 )
 
-from xoa_driver.internals.hli_v1.ports.port_l23.family_l1 import (
+from xoa_driver.internals.hli.ports.port_l23.family_l1 import (
     PFreya800G1S1P_a,
     PFreya800G1S1P_b,
     PFreya800G1S1POSFP_a,
@@ -97,7 +94,7 @@ from xoa_driver.internals.hli_v1.ports.port_l23.family_l1 import (
     PFreya800G4S1POSFP_f,
 )
 
-from xoa_driver.internals.hli_v1.ports.port_l23.family_m import POdin1G3S6PT1RJ45
+from xoa_driver.internals.hli.ports.port_l23.family_m import POdin1G3S6PT1RJ45
 
 Z10OdinPort = typing.Union[
     POdin1G3S2PT,
@@ -136,6 +133,7 @@ Z100LokiPort = typing.Union[
     PLoki100G3S1PB_b,
     PLoki100G5S1P,
     PLoki100G5S2P,
+    PLoki100G5S4P_a,
 ]
 
 Z400ThorPort = typing.Union[
@@ -213,6 +211,7 @@ GenericL23Port = typing.Union[
     "PLoki100G3S1PB_b",
     "PLoki100G5S1P",
     "PLoki100G5S2P",
+    "PLoki100G5S4P_a",
 
     "PThor100G5S4P",
     "PThor400G7S1P",
@@ -294,6 +293,7 @@ __all__ = (
     "PLoki100G3S1PB_b",
     "PLoki100G5S1P",
     "PLoki100G5S2P",
+    "PLoki100G5S4P_a",
 
     "Z400ThorPort",
     "PThor100G5S4P",

xoa_driver/testers.py

@@ -1,13 +1,9 @@
 #: All available tester types.
-import sys
 
-if "xoa_driver.v2" in sys.modules:
-    raise ImportError("\33[31mOnly Single interface version is allowed to being use at the same time.\33[0m")
-
-from .internals.hli_v1.testers.l23_tester import L23Tester
-from .internals.hli_v1.testers.l23ve_tester import L23VeTester
-from .internals.hli_v1.testers.l47_tester import L47Tester
-from .internals.hli_v1.testers.l47ve_tester import L47VeTester
+from .internals.hli.testers.l23_tester import L23Tester
+from .internals.hli.testers.l23ve_tester import L23VeTester
+from .internals.hli.testers.l47_tester import L47Tester
+from .internals.hli.testers.l47ve_tester import L47VeTester
 
 import typing