tdl-xoa-driver 1.0.0b1__py3-none-any.whl

xoa_driver/ports.py

@@ -0,0 +1,332 @@
+#: All available test port types.
+import sys
+
+if "xoa_driver.v2" in sys.modules:
+    raise ImportError("\33[31mOnly Single interface version is allowed to being use at the same time.\33[0m")
+
+import typing
+
+from .internals.hli_v1.ports.port_l47.main import PortL47
+
+from .internals.hli_v1.ports.port_l23.port_l23ve import PortL23VE
+from .internals.hli_v1.ports.port_l23.chimera.port_chimera import (
+    PortChimera,
+    PChi100G5S2P,
+    PChi100G5S2P_b,
+    PChi40G2S2P,
+)
+
+from .internals.hli_v1.ports.port_l23.bases.port_l23 import BasePortL23
+from xoa_driver.internals.hli_v1.ports.port_l23.family_combi import (
+    POdin1G4S4PCombi,
+    POdin1G4S4PCombi_b,
+    POdin10G4S2PCombi,
+    POdin10G4S2PCombi_b,
+)
+
+from xoa_driver.internals.hli_v1.ports.port_l23.family_d import (
+    POdin1G3S2PT,
+    POdin1G3S6P,
+    POdin1G3S6P_b,
+    POdin1G3S6PE,
+)
+
+from xoa_driver.internals.hli_v1.ports.port_l23.family_e import (
+    POdin5G4S6PCU,
+    POdin10G3S2PCU,
+    POdin10G3S6PCU,
+    POdin10G5S6PCU,
+    POdin10G5S6PCU_b,
+)
+
+from xoa_driver.internals.hli_v1.ports.port_l23.family_f import (
+    POdin10G1S2P,
+    POdin10G1S2P_b,
+    POdin10G1S2P_c,
+    POdin10G1S2P_d,
+    POdin10G1S2PT,
+    POdin10G1S6P,
+    POdin10G1S6P_b,
+    POdin10G1S12P,
+    POdin40G2S2P,
+    POdin40G2S2PB,
+    POdin10G6S6P_a,
+)
+
+from xoa_driver.internals.hli_v1.ports.port_l23.family_g import (
+    PLoki100G3S1P,
+    PLoki100G3S1P_b,
+    PLoki100G3S1PSE,
+    PLoki100G3S1PB,
+    PLoki100G3S1PB_b,
+)
+
+from xoa_driver.internals.hli_v1.ports.port_l23.family_h import (
+    PLoki100G5S1P,
+    POdin100G3S1P,
+)
+
+from xoa_driver.internals.hli_v1.ports.port_l23.family_i import PLoki100G5S2P
+from xoa_driver.internals.hli_v1.ports.port_l23.family_j import PThor100G5S4P
+from xoa_driver.internals.hli_v1.ports.port_l23.family_k import (
+    PThor400G7S1P,
+    PThor400G7S1PLE,
+)
+from xoa_driver.internals.hli_v1.ports.port_l23.family_l import (
+    PThor400G7S1P_b,
+    PThor400G7S1P_c,
+    PThor400G7S1P_d,
+)
+
+from xoa_driver.internals.hli_v1.ports.port_l23.family_l1 import (
+    PFreya800G1S1P_a,
+    PFreya800G1S1P_b,
+    PFreya800G1S1POSFP_a,
+    PFreya800G1S1POSFP_b,
+    PFreya800G4S1P_a,
+    PFreya800G4S1P_b,
+    PFreya800G4S1P_c,
+    PFreya800G4S1P_d,
+    PFreya800G4S1P_e,
+    PFreya800G4S1P_f,
+    PFreya800G4S1POSFP_a,
+    PFreya800G4S1POSFP_b,
+    PFreya800G4S1POSFP_c,
+    PFreya800G4S1POSFP_d,
+    PFreya800G4S1POSFP_e,
+    PFreya800G4S1POSFP_f,
+)
+
+from xoa_driver.internals.hli_v1.ports.port_l23.family_m import POdin1G3S6PT1RJ45
+
+Z10OdinPort = typing.Union[
+    POdin1G3S2PT,
+    POdin1G3S6P,
+    POdin1G3S6P_b,
+    POdin1G3S6PE,
+    POdin1G3S6PT1RJ45,
+    POdin1G4S4PCombi,
+    POdin1G4S4PCombi_b,
+    POdin5G4S6PCU,
+    POdin10G1S2P,
+    POdin10G1S2P_b,
+    POdin10G1S2P_c,
+    POdin10G1S2P_d,
+    POdin10G1S2PT,
+    POdin10G1S6P,
+    POdin10G1S6P_b,
+    POdin10G1S12P,
+    POdin10G3S2PCU,
+    POdin10G3S6PCU,
+    POdin10G4S2PCombi,
+    POdin10G4S2PCombi_b,
+    POdin10G5S6PCU,
+    POdin10G5S6PCU_b,
+    POdin10G6S6P_a,
+    POdin40G2S2P,
+    POdin40G2S2PB,
+    POdin100G3S1P,
+]
+
+Z100LokiPort = typing.Union[
+    PLoki100G3S1P,
+    PLoki100G3S1P_b,
+    PLoki100G3S1PSE,
+    PLoki100G3S1PB,
+    PLoki100G3S1PB_b,
+    PLoki100G5S1P,
+    PLoki100G5S2P,
+]
+
+Z400ThorPort = typing.Union[
+    PThor100G5S4P,
+    PThor400G7S1P,
+    PThor400G7S1PLE,
+    PThor400G7S1P_b,
+    PThor400G7S1P_c,
+    PThor400G7S1P_d,
+]
+
+Z800FreyaPort = typing.Union[
+    PFreya800G1S1P_a,
+    PFreya800G1S1P_b,
+    PFreya800G1S1POSFP_a,
+    PFreya800G1S1POSFP_b,
+    PFreya800G4S1P_a,
+    PFreya800G4S1P_b,
+    PFreya800G4S1P_c,
+    PFreya800G4S1P_d,
+    PFreya800G4S1P_e,
+    PFreya800G4S1P_f,
+    PFreya800G4S1POSFP_a,
+    PFreya800G4S1POSFP_b,
+    PFreya800G4S1POSFP_c,
+    PFreya800G4S1POSFP_d,
+    PFreya800G4S1POSFP_e,
+    PFreya800G4S1POSFP_f,
+]
+
+E100ChimeraPort = typing.Union[
+    PortChimera,
+    PChi100G5S2P,
+    PChi100G5S2P_b,
+    PChi40G2S2P,
+]
+
+LegacyPort = typing.Union[
+    PortL47,
+    PortL23VE,
+]
+
+GenericL23Port = typing.Union[
+    "POdin1G3S2PT",
+    "POdin1G3S6P",
+    "POdin1G3S6P_b",
+    "POdin1G3S6PE",
+    "POdin1G3S6PT1RJ45",
+    "POdin1G4S4PCombi",
+    "POdin1G4S4PCombi_b",
+    "POdin5G4S6PCU",
+    "POdin10G1S2P",
+    "POdin10G1S2P_b",
+    "POdin10G1S2P_c",
+    "POdin10G1S2P_d",
+    "POdin10G1S2PT",
+    "POdin10G1S6P",
+    "POdin10G1S6P_b",
+    "POdin10G1S12P",
+    "POdin10G3S2PCU",
+    "POdin10G3S6PCU",
+    "POdin10G4S2PCombi",
+    "POdin10G4S2PCombi_b",
+    "POdin10G5S6PCU",
+    "POdin10G5S6PCU_b",
+    "POdin10G6S6P_a",
+    "POdin40G2S2P",
+    "POdin40G2S2PB",
+    "POdin100G3S1P",
+
+    "PLoki100G3S1P",
+    "PLoki100G3S1P_b",
+    "PLoki100G3S1PSE",
+    "PLoki100G3S1PB",
+    "PLoki100G3S1PB_b",
+    "PLoki100G5S1P",
+    "PLoki100G5S2P",
+
+    "PThor100G5S4P",
+    "PThor400G7S1P",
+    "PThor400G7S1PLE",
+    "PThor400G7S1P_b",
+    "PThor400G7S1P_c",
+    "PThor400G7S1P_d",
+
+    "PFreya800G1S1P_a",
+    "PFreya800G1S1P_b",
+    "PFreya800G1S1POSFP_a",
+    "PFreya800G1S1POSFP_b",
+    "PFreya800G4S1P_a",
+    "PFreya800G4S1P_b",
+    "PFreya800G4S1P_c",
+    "PFreya800G4S1P_d",
+    "PFreya800G4S1P_e",
+    "PFreya800G4S1P_f",
+    "PFreya800G4S1POSFP_a",
+    "PFreya800G4S1POSFP_b",
+    "PFreya800G4S1POSFP_c",
+    "PFreya800G4S1POSFP_d",
+    "PFreya800G4S1POSFP_e",
+    "PFreya800G4S1POSFP_f",
+]
+
+GenericAnyPort = typing.Union[
+    GenericL23Port,
+
+    "PortL47",
+    "PortL23VE",
+
+    "PortChimera",
+    "PChi100G5S2P",
+    "PChi100G5S2P_b",
+    "PChi40G2S2P",
+]
+
+__all__ = (
+    "BasePortL23",
+
+    "LegacyPort",
+    "PortL47",
+    "PortL23VE",
+
+    "Z10OdinPort",
+    "POdin1G3S2PT",
+    "POdin1G3S6P",
+    "POdin1G3S6P_b",
+    "POdin1G3S6PE",
+    "POdin1G3S6PT1RJ45",
+    "POdin1G4S4PCombi",
+    "POdin1G4S4PCombi_b",
+    "POdin5G4S6PCU",
+    "POdin10G1S2P",
+    "POdin10G1S2P_b",
+    "POdin10G1S2P_c",
+    "POdin10G1S2P_d",
+    "POdin10G1S2PT",
+    "POdin10G1S6P",
+    "POdin10G1S6P_b",
+    "POdin10G1S12P",
+    "POdin10G3S2PCU",
+    "POdin10G3S6PCU",
+    "POdin10G4S2PCombi",
+    "POdin10G4S2PCombi_b",
+    "POdin10G5S6PCU",
+    "POdin10G5S6PCU_b",
+    "POdin10G6S6P_a",
+    "POdin40G2S2P",
+    "POdin40G2S2PB",
+    "POdin100G3S1P",
+
+    "Z100LokiPort",
+    "PLoki100G3S1P",
+    "PLoki100G3S1P_b",
+    "PLoki100G3S1PSE",
+    "PLoki100G3S1PB",
+    "PLoki100G3S1PB_b",
+    "PLoki100G5S1P",
+    "PLoki100G5S2P",
+
+    "Z400ThorPort",
+    "PThor100G5S4P",
+    "PThor400G7S1P",
+    "PThor400G7S1PLE",
+    "PThor400G7S1P_b",
+    "PThor400G7S1P_c",
+    "PThor400G7S1P_d",
+
+    "Z800FreyaPort",
+    "PFreya800G1S1P_a",
+    "PFreya800G1S1P_b",
+    "PFreya800G1S1POSFP_a",
+    "PFreya800G1S1POSFP_b",
+    "PFreya800G4S1P_a",
+    "PFreya800G4S1P_b",
+    "PFreya800G4S1P_c",
+    "PFreya800G4S1P_d",
+    "PFreya800G4S1P_e",
+    "PFreya800G4S1P_f",
+    "PFreya800G4S1POSFP_a",
+    "PFreya800G4S1POSFP_b",
+    "PFreya800G4S1POSFP_c",
+    "PFreya800G4S1POSFP_d",
+    "PFreya800G4S1POSFP_e",
+    "PFreya800G4S1POSFP_f",
+
+    "E100ChimeraPort",
+    "PortChimera",
+    "PChi100G5S2P",
+    "PChi100G5S2P_b",
+    "PChi40G2S2P",
+    
+    "GenericL23Port",
+    "GenericAnyPort",
+)

xoa_driver/testers.py

@@ -0,0 +1,37 @@
+#: All available tester types.
+import sys
+
+if "xoa_driver.v2" in sys.modules:
+    raise ImportError("\33[31mOnly Single interface version is allowed to being use at the same time.\33[0m")
+
+from .internals.hli_v1.testers.l23_tester import L23Tester
+from .internals.hli_v1.testers.l23ve_tester import L23VeTester
+from .internals.hli_v1.testers.l47_tester import L47Tester
+from .internals.hli_v1.testers.l47ve_tester import L47VeTester
+
+import typing
+
+GenericAnyTester = typing.Union[
+    "L23Tester",
+    "L23VeTester",
+    "L47Tester",
+    "L47VeTester",
+]
+GenericAnyGenuineTester = typing.Union[
+    "L23Tester",
+    "L47Tester",
+]
+GenericAnyVirtualTester = typing.Union[
+    "L23VeTester",
+    "L47VeTester",
+]
+
+__all__ = (
+    "L23Tester",
+    "L23VeTester",
+    "L47Tester",
+    "L47VeTester",
+    "GenericAnyTester",
+    "GenericAnyGenuineTester",
+    "GenericAnyVirtualTester",
+)

xoa_driver/utils.py

@@ -0,0 +1,12 @@
+#: Helper functions
+
+from xoa_driver.internals.core.funcs import (
+    apply,
+    apply_iter,
+)
+
+
+__all__ = (
+    "apply",
+    "apply_iter",
+)

xoa_driver/v2/__init__.py

@@ -0,0 +1,11 @@
+import sys
+
+
+if "xoa_driver.internals.hli_v1" in sys.modules:
+    raise ImportError("\33[101mUsing xoa_driver and xoa_driver.v2 at the same time is not allowed.\33[0m")
+
+from xoa_driver.internals import warn
+
+warn.resource(
+    "xoa_driver.v2 is under development and it subject to changes without notice.",
+)

xoa_driver/v2/misc.py

@@ -0,0 +1,77 @@
+#: Other types which are used by ports or as a parameter to attribute set method.
+
+
+from xoa_driver.internals.core.token import Token
+from xoa_driver.internals.commands.subtypes import (
+    ArpChunk,
+    NdpChunk,
+)
+from xoa_driver.internals.core.transporter.protocol.payload.types import Hex
+
+# indices types
+from xoa_driver.internals.hli_v2.indices.connection_group.cg import ConnectionGroupIdx as ConnectionGroup
+from xoa_driver.internals.hli_v2.indices.filter.base_filter import BaseFilterIdx as BasePortFilter
+from xoa_driver.internals.hli_v2.indices.filter.genuine_filter import GenuineFilterIdx as GenuinePortFilter
+from xoa_driver.internals.hli_v2.indices.length_term import LengthTermIdx as LengthTerm
+from xoa_driver.internals.hli_v2.indices.match_term import MatchTermIdx as MatchTerm
+from xoa_driver.internals.hli_v2.indices.port_dataset import PortDatasetIdx as PortDataset
+from xoa_driver.internals.hli_v2.indices.streams.base_stream import BaseStreamIdx as BaseStream
+from xoa_driver.internals.hli_v2.indices.streams.genuine_stream import GenuineStreamIdx as GenuineStream
+from xoa_driver.internals.hli_v2.ports.port_l23.chimera.filter_definition.general import ProtocolSegment
+from xoa_driver.internals.hli_v2.ports.port_l23.chimera.port_emulation import (
+    CFlow as ImpairmentFlow,
+    StatisticsTotals,
+    CPerFlowStats as PerImpairmentFlowStats,
+    CLatencyJitterImpairment,
+    CDropImpairment,
+    CMisorderingImpairment,
+    CDuplicationImpairment,
+    CCorruptionImpairment,
+    CPolicerImpairment,
+    CShaperImpairment,
+)
+from xoa_driver.internals.hli_v2.ports.port_l23.chimera.filter_definition.general import ModeBasic as BasicImpairmentFlowFilter
+from xoa_driver.internals.hli_v2.ports.port_l23.chimera.filter_definition.general import ModeExtended as ExtendedImpairmentFlowFilter
+from xoa_driver.internals.hli_v2.ports.port_l23.chimera.pe_custom_distribution import (
+    CustomDistributions,
+    CustomDistribution,
+)
+from xoa_driver.internals.hli_v2.ports.port_l23.chimera.filter_definition.shadow import (
+    FilterDefinitionShadow,
+    ModeExtendedS,
+)
+from xoa_driver.internals.hli_v2.ports.port_l23.chimera.filter_definition.general import ModeBasic
+
+
+__all__ = (
+    "Token",
+    "ArpChunk",
+    "NdpChunk",
+    "Hex",
+    "ConnectionGroup",
+    "BasePortFilter",
+    "GenuinePortFilter",
+    "LengthTerm",
+    "MatchTerm",
+    "PortDataset",
+    "BaseStream",
+    "GenuineStream",
+    "ImpairmentFlow",
+    "BasicImpairmentFlowFilter",
+    "ExtendedImpairmentFlowFilter",
+    "StatisticsTotals",
+    "CustomDistributions",
+    "CustomDistribution",
+    "PerImpairmentFlowStats",
+    "CLatencyJitterImpairment",
+    "CDropImpairment",
+    "CMisorderingImpairment",
+    "CDuplicationImpairment",
+    "CCorruptionImpairment",
+    "CPolicerImpairment",
+    "CShaperImpairment",
+    "FilterDefinitionShadow",
+    "ModeExtendedS",
+    "ModeBasic",
+    "ProtocolSegment",
+)