tdl-xoa-driver 1.0.0b1__py3-none-any.whl → 1.2.0__py3-none-any.whl

xoa_driver/functions/headers.py

@@ -1,12 +1,3 @@
-################################################################
-#
-#                   HEADER BUILDER
-#
-# This script shows you how you can build your own header builder 
-# that converts human readable values into hex strings
-#
-################################################################
-
 from ipaddress import IPv4Address, IPv6Address
 from binascii import hexlify
 from xoa_driver.misc import Hex
@@ -146,7 +137,7 @@ class Ethernet:
         return f"{_dst_mac}{_src_mac}{_ethertype}".upper()
     
 ####################################
-#           VLAN               #
+#           VLAN                   #
 ####################################
 
 @dataclass
@@ -605,4 +596,314 @@ class MACControlPause:
     def __str__(self):
         _opcode: str = self.opcode
         _value = '{:04X}'.format(self.value)
-        return f"{_opcode}{_value}".upper()
+        return f"{_opcode}{_value}".upper()
+    
+
+####################################
+#       Infiniband Headers         #
+####################################
+class BTHOpcode(Enum):
+    # OpCodeValues
+    # Code Bits [7-5] Connection Type
+    #           [4-0] Message Type
+
+    # Reliable Connection (RC)
+    # [7-5] = 000
+    RC_SEND_FIRST                  = 0 # /*0x00000000 */ "RC Send First " 
+    RC_SEND_MIDDLE                 = 1 # /*0x00000001 */ "RC Send Middle "
+    RC_SEND_LAST                   = 2 # /*0x00000010 */ "RC Send Last " 
+    RC_SEND_LAST_IMM               = 3 # /*0x00000011 */ "RC Send Last Immediate "
+    RC_SEND_ONLY                   = 4 # /*0x00000100 */ "RC Send Only "
+    RC_SEND_ONLY_IMM               = 5 # /*0x00000101 */ "RC Send Only Immediate "
+    RC_RDMA_WRITE_FIRST            = 6 # /*0x00000110 */ "RC RDMA Write First " 
+    RC_RDMA_WRITE_MIDDLE           = 7 # /*0x00000111 */ "RC RDMA Write Middle "
+    RC_RDMA_WRITE_LAST             = 8 # /*0x00001000 */ "RC RDMA Write Last "
+    RC_RDMA_WRITE_LAST_IMM         = 9 # /*0x00001001 */ "RC RDMA Write Last Immediate "
+    RC_RDMA_WRITE_ONLY             = 10 # /*0x00001010 */ "RC RDMA Write Only " 
+    RC_RDMA_WRITE_ONLY_IMM         = 11 # /*0x00001011 */ "RC RDMA Write Only Immediate " 
+    RC_RDMA_READ_REQUEST           = 12 # /*0x00001100 */ "RC RDMA Read Request " 
+    RC_RDMA_READ_RESPONSE_FIRST    = 13 # /*0x00001101 */ "RC RDMA Read Response First " 
+    RC_RDMA_READ_RESPONSE_MIDDLE   = 14 # /*0x00001110 */ "RC RDMA Read Response Middle " 
+    RC_RDMA_READ_RESPONSE_LAST     = 15 # /*0x00001111 */ "RC RDMA Read Response Last " 
+    RC_RDMA_READ_RESPONSE_ONLY     = 16 # /*0x00010000 */ "RC RDMA Read Response Only " 
+    RC_ACKNOWLEDGE                 = 17 # /*0x00010001 */ "RC Acknowledge " 
+    RC_ATOMIC_ACKNOWLEDGE          = 18 # /*0x00010010 */ "RC Atomic Acknowledge "
+    RC_CMP_SWAP                    = 19 # /*0x00010011 */ "RC Compare Swap " 
+    RC_FETCH_ADD                   = 20 # /*0x00010100 */ "RC Fetch Add "
+    RC_SEND_LAST_INVAL             = 22 # /*0x00010110 */ "RC Send Last Invalidate "
+    RC_SEND_ONLY_INVAL             = 23 # /*0x00010111 */ "RC Send Only Invalidate "
+
+    # Reliable Datagram (RD)
+    # [7-5] = 010
+    RD_SEND_FIRST                  = 64 # /*0x01000000 */ "RD Send First "
+    RD_SEND_MIDDLE                 = 65 # /*0x01000001 */ "RD Send Middle "
+    RD_SEND_LAST                   = 66 # /*0x01000010 */ "RD Send Last "
+    RD_SEND_LAST_IMM               = 67 # /*0x01000011 */ "RD Send Last Immediate "
+    RD_SEND_ONLY                   = 68 # /*0x01000100 */ "RD Send Only "
+    RD_SEND_ONLY_IMM               = 69 # /*0x01000101 */ "RD Send Only Immediate "
+    RD_RDMA_WRITE_FIRST            = 70 # /*0x01000110 */ "RD RDMA Write First "
+    RD_RDMA_WRITE_MIDDLE           = 71 # /*0x01000111 */ "RD RDMA Write Middle "
+    RD_RDMA_WRITE_LAST             = 72 # /*0x01001000 */ "RD RDMA Write Last "
+    RD_RDMA_WRITE_LAST_IMM         = 73 # /*0x01001001 */ "RD RDMA Write Last Immediate "
+    RD_RDMA_WRITE_ONLY             = 74 # /*0x01001010 */ "RD RDMA Write Only "
+    RD_RDMA_WRITE_ONLY_IMM         = 75 # /*0x01001011 */ "RD RDMA Write Only Immediate "
+    RD_RDMA_READ_REQUEST           = 76 # /*0x01001100 */ "RD RDMA Read Request "
+    RD_RDMA_READ_RESPONSE_FIRST    = 77 # /*0x01001101 */ "RD RDMA Read Response First "
+    RD_RDMA_READ_RESPONSE_MIDDLE   = 78 # /*0x01001110 */ "RD RDMA Read Response Middle "
+    RD_RDMA_READ_RESPONSE_LAST     = 79 # /*0x01001111 */ "RD RDMA Read Response Last "
+    RD_RDMA_READ_RESPONSE_ONLY     = 80 # /*0x01010000 */ "RD RDMA Read Response Only "
+    RD_ACKNOWLEDGE                 = 81 # /*0x01010001 */ "RD Acknowledge "
+    RD_ATOMIC_ACKNOWLEDGE          = 82 # /*0x01010010 */ "RD Atomic Acknowledge "
+    RD_CMP_SWAP                    = 83 # /*0x01010011 */ "RD Compare Swap "
+    RD_FETCH_ADD                   = 84 # /*0x01010100 */ "RD Fetch Add "
+    RD_RESYNC                      = 85 # /*0x01010101 */ "RD RESYNC "
+
+    # Unreliable Datagram (UD)
+    # [7-5] = 011
+    UD_SEND_ONLY                  = 100 # /*0x01100100 */ "UD Send Only "
+    UD_SEND_ONLY_IMM              = 101 # /*0x01100101 */ "UD Send Only Immediate "
+
+    # Unreliable Connection (UC)
+    # [7-5] = 001
+    UC_SEND_FIRST                  = 32 # /*0x00100000 */ "UC Send First "
+    UC_SEND_MIDDLE                 = 33 # /*0x00100001 */ "UC Send Middle  "
+    UC_SEND_LAST                   = 34 # /*0x00100010 */ "UC Send Last "
+    UC_SEND_LAST_IMM               = 35 # /*0x00100011 */ "UC Send Last Immediate "
+    UC_SEND_ONLY                   = 36 # /*0x00100100 */ "UC Send Only "
+    UC_SEND_ONLY_IMM               = 37 # /*0x00100101 */ "UC Send Only Immediate "
+    UC_RDMA_WRITE_FIRST            = 38 # /*0x00100110 */ "UC RDMA Write First"
+    UC_RDMA_WRITE_MIDDLE           = 39 # /*0x00100111 */ "UC RDMA Write Middle "
+    UC_RDMA_WRITE_LAST             = 40 # /*0x00101000 */ "UC RDMA Write Last "
+    UC_RDMA_WRITE_LAST_IMM         = 41 # /*0x00101001 */ "UC RDMA Write Last Immediate"
+    UC_RDMA_WRITE_ONLY             = 42 # /*0x00101010 */ "UC RDMA Write Only "
+    UC_RDMA_WRITE_ONLY_IMM         = 43 # /*0x00101011 */ "UC RDMA Write Only Immediate"
+
+@dataclass
+class BTH:
+    """BASE TRANSPORT HEADER (BTH) - 12 BYTES
+    
+    Base Transport Header contains the fields for IBA transports.
+    """
+    opcode: BTHOpcode = BTHOpcode.RC_SEND_FIRST
+    """OpCode indicates the IBA packet type. It also
+    specifies which extension headers follow the BTH
+    """
+    se = 0
+    """Solicited Event, this bit indicates that an event
+    should be generated by the responder
+    """
+    migreq = 0
+    """This bit is used to communicate migration state
+    """
+    padcnt = 1
+    """Pad Count indicates how many extra bytes are added
+    to the payload to align to a 4 byte boundary
+    """
+    tver = 0
+    """Transport Header Version indicates the version of
+    the IBA Transport Headers
+    """ 
+    pkey = 65535
+    """Partition Key indicates which logical Partition is
+    associated with this packet
+    """
+    reserved = 7
+    """Reserved
+    """
+    destqp = 2
+    """Destination QP indicates the Work Queue Pair Number
+    (QP) at the destination
+    """
+    ackreq = 0
+    """Acknowledge Request, this bit is used to indicate
+    that an acknowledge (for this packet) should be
+    scheduled by the responder
+    """
+    reserved_7bits = 0
+    """Reserved
+    """
+    psn =0
+    """Packet Sequence Number is used to detect a missing
+    or duplicate Packet
+    """
+
+    def __str__(self):
+        _opcode = '{:02X}'.format(self.opcode.value)
+        _combo_1 = '{:02X}'.format((self.se<<7)+(self.migreq<<6)+(self.padcnt<<4)+self.tver)
+        _pk = '{:04X}'.format(self.pkey)
+        _reserved = '{:02X}'.format(self.reserved)
+        _qp = '{:06X}'.format(self.destqp)
+        _combo_2 = '{:02X}'.format((self.ackreq<<7)+self.reserved_7bits)
+        _ps = '{:06X}'.format(self.psn)
+        return f"{_opcode}{_combo_1}{_pk}{_reserved}{_qp}{_combo_2}{_ps}".upper()
+
+@dataclass
+class RETH:
+    """RDMA EXTENDED TRANSPORT HEADER (RETH) - 16 BYTES
+
+    RDMA Extended Transport Header contains the additional transport fields
+    for RDMA operations. The RETH is present in only the first (or only)
+    packet of an RDMA Request as indicated by the Base Transport Header
+    OpCode field.
+    """
+    va = 0
+    """Virtual Address of the RDMA operation
+    """
+    r_key = 0
+    """Remote Key that authorizes access for the RDMA operation
+    """
+    dma_len = 0
+    """DMA Length indicates the length (in Bytes) of the DMA operation.
+    """
+
+    def __str__(self):
+        _va = '{:016X}'.format(self.va)
+        _r_key = '{:08X}'.format(self.r_key)
+        _dma_len = '{:08X}'.format(self.dma_len)
+        return f"{_va}{_r_key}{_dma_len}".upper()
+
+@dataclass
+class AETH:
+    """ACK EXTENDED TRANSPORT HEADER (AETH) - 4 BYTES
+
+    ACK Extended Transport Header contains the additional transport fields
+    for ACK packets. The AETH is only in Acknowledge, RDMA READ Response
+    First, RDMA READ Response Last, and RDMA READ Response Only packets
+    as indicated by the Base Transport Header OpCode field.
+    """
+    syndrome = 0
+    """Syndrome indicates if this is an ACK or NAK
+    packet plus additional information about the
+    ACK or NAK
+    """
+    msn = 0
+    """Message Sequence Number indicates the sequence
+    number of the last message completed at the
+    responder
+    """
+
+    def __str__(self):
+        _syndrome = '{:02X}'.format(self.syndrome)
+        _msn = '{:06X}'.format(self.msn)
+        return f"{_syndrome}{_msn}".upper()
+
+@dataclass
+class RDETH:
+    """RELIABLE DATAGRAM EXTENDED TRANSPORT HEADER (RDETH) - 4 BYTES
+
+    Reliable Datagram Extended Transport Header contains the additional
+    transport fields for reliable datagram service. The RDETH is only
+    in Reliable Datagram packets as indicated by the Base Transport Header
+    OpCode field.
+    """
+
+    reserved = 0
+    """Reserved
+    """
+    ee_context = 0
+    """EE-Context indicates which End-to-End Context
+    should be used for this Reliable Datagram packet
+    """
+
+    def __str__(self):
+        _reserved = '{:02X}'.format(self.reserved)
+        _ee_context = '{:06X}'.format(self.ee_context)
+        return f"{_reserved}{_ee_context}".upper()
+
+@dataclass
+class DETH:
+    """DATAGRAM EXTENDED TRANSPORT HEADER (DETH) - 8 BYTES
+
+    Datagram Extended Transport Header contains the additional transport
+    fields for datagram service. The DETH is only in datagram packets if
+    indicated by the Base Transport Header OpCode field.
+    """
+    q_key = 0
+    """Queue Key is required to authorize access to the receive queue
+    """
+    reserved = 0
+    """Reserved
+    """
+    src_qp = 0
+    """Source QP indicates the Work Queue Pair Number (QP) at the source.
+    """
+
+    def __str__(self):
+        _q_key = '{:08X}'.format(self.q_key)
+        _reserved = '{:02X}'.format(self.reserved)
+        _src_qp = '{:06X}'.format(self.src_qp)
+        return f"{_q_key}{_reserved}{_src_qp}".upper()
+
+@dataclass
+class IB:
+    bth = BTH()
+    reth = RETH()
+    aeth = AETH()
+    rdeth = RDETH()
+    deth = DETH()
+
+    def __str__(self):
+        if self.bth.opcode == BTHOpcode.RC_SEND_FIRST or self.bth.opcode == BTHOpcode.RC_SEND_MIDDLE or self.bth.opcode == BTHOpcode.RC_SEND_LAST:
+            return str(self.bth)
+        if self.bth.opcode == BTHOpcode.RC_RDMA_WRITE_FIRST:
+            return str(self.bth)+str(self.reth)
+        if self.bth.opcode == BTHOpcode.RC_RDMA_WRITE_MIDDLE or self.bth.opcode == BTHOpcode.RC_RDMA_WRITE_LAST:
+            return str(self.bth)
+        if self.bth.opcode == BTHOpcode.RC_RDMA_READ_RESPONSE_FIRST or self.bth.opcode == BTHOpcode.RC_RDMA_READ_RESPONSE_LAST:
+            return str(self.bth)+str(self.aeth)
+        if self.bth.opcode == BTHOpcode.RC_RDMA_READ_RESPONSE_MIDDLE:
+            return str(self.bth)
+        if self.bth.opcode == BTHOpcode.RD_SEND_FIRST or self.bth.opcode == BTHOpcode.RD_SEND_MIDDLE or self.bth.opcode == BTHOpcode.RD_SEND_LAST:
+            return str(self.bth)+str(self.rdeth)+str(self.deth)
+        if self.bth.opcode == BTHOpcode.RD_RDMA_WRITE_FIRST:
+            return str(self.bth)+str(self.rdeth)+str(self.deth)+str(self.reth)
+        if self.bth.opcode == BTHOpcode.RD_RDMA_WRITE_MIDDLE or self.bth.opcode == BTHOpcode.RD_RDMA_WRITE_LAST:
+            return str(self.bth)+str(self.rdeth)+str(self.deth)
+        if self.bth.opcode == BTHOpcode.RD_RDMA_READ_RESPONSE_FIRST or self.bth.opcode == BTHOpcode.RD_RDMA_READ_RESPONSE_LAST:
+            return str(self.bth)+str(self.rdeth)+str(self.aeth)
+        if self.bth.opcode == BTHOpcode.RD_RDMA_READ_RESPONSE_MIDDLE:
+            return str(self.bth)+str(self.rdeth)
+        if self.bth.opcode == BTHOpcode.UD_SEND_ONLY:
+            return str(self.bth)+str(self.deth)
+
+
+######################
+#       MPLS         #
+######################
+@dataclass
+class MPLS:
+    label: int = 0
+    exp: int = 0
+    s: int = 1
+    ttl: int = 0
+
+    def __str__(self):
+        _combo: str = '{:06X}'.format((self.label<<4)+(self.exp<<1)+(self.s))
+        _ttl: str = '{:02X}'.format(self.ttl)
+        return f"{_combo}{_ttl}".upper()
+
+
+__all__ = (
+    "IPV4",
+    "IPV6",
+    "UDP",
+    "TCP",
+    "PTP",
+    "eCPRIGeneralDataTransfer",
+    "DHCPV4",
+    "DHCPOptionMessageType",
+    "DHCPOptionClientIdentifier",
+    "DHCPOptionRequestedIP",
+    "DHCPOptionParamRequestList",
+    "DHCPOptionPad",
+    "DHCPOptionEnd",
+    "MACControlPFC",
+    "MACControlPause",
+    "BTH",
+    "RETH",
+    "AETH",
+    "RDETH",
+    "DETH",
+    "IB",
+    "MPLS"
+)

xoa_driver/functions/mgmt.py

@@ -25,8 +25,6 @@ LinkTrainingSupported = FamilyL
 # region Testers
 async def reserve_tester(tester: GenericAnyTester, force: bool = True) -> None:
     """
-    .. versionadded:: 1.1
-
     Reserve a tester regardless whether it is owned by others or not.
 
     :param tester: The tester to reserve
@@ -39,25 +37,23 @@ async def reserve_tester(tester: GenericAnyTester, force: bool = True) -> None:
     r = await tester.reservation.get()
     if force and r.operation == enums.ReservedStatus.RESERVED_BY_OTHER:
         await tester.reservation.set_relinquish()
-        await asyncio.gather(*(free_module(m, True) for m in tester.modules))
+        await asyncio.gather(*(release_module(m, True) for m in tester.modules))
         await tester.reservation.set_reserve()
     elif r.operation == enums.ReservedStatus.RELEASED:
         await tester.reservation.set_reserve()
 
 
-async def free_tester(
+async def release_tester(
         tester: GenericAnyTester, 
-        should_free_modules_ports: bool = False,
+        should_release_modules_ports: bool = False,
         ) -> None:
     """
-    .. versionadded:: 1.1
-
     Free a tester. If the tester is reserved by you, release the tester. If the tester is reserved by others, relinquish the tester. The tester should have no owner afterwards.
 
     :param tester: The tester to free
     :type tester: :class:`~xoa_driver.testers.GenericAnyTester`
-    :param should_free_modules_ports: should modules and ports also be freed, defaults to False
-    :type should_free_modules_ports: bool, optional
+    :param should_release_modules_ports: should modules and ports also be freed, defaults to False
+    :type should_release_modules_ports: bool, optional
     :return:
     :rtype: None
     """
@@ -66,14 +62,12 @@ async def free_tester(
         await tester.reservation.set_relinquish()
     elif r.operation == enums.ReservedStatus.RESERVED_BY_YOU:
         await tester.reservation.set_release()
-    if should_free_modules_ports:
-        await asyncio.gather(*(free_module(m, True) for m in tester.modules))
+    if should_release_modules_ports:
+        await asyncio.gather(*(release_module(m, True) for m in tester.modules))
 
 
 async def get_chassis_sys_uptime_sec(tester: L23Tester) -> int:
     """
-    .. versionadded:: 2.7.2
-
     Get chassis system uptime in seconds
 
     :param tester: The tester to free
@@ -96,8 +90,6 @@ async def get_chassis_sys_uptime_sec(tester: L23Tester) -> int:
 
 def get_module(tester: GenericAnyTester, module_id: int) -> GenericAnyModule:
     """
-    .. versionadded:: 1.1
-
     Get a module object of the tester.
 
     :param tester: The tester object
@@ -113,8 +105,6 @@ def get_module(tester: GenericAnyTester, module_id: int) -> GenericAnyModule:
 
 def get_modules(tester: GenericAnyTester) -> tuple[GenericAnyModule, ...]:
     """
-    .. versionadded:: 1.1
-
     Get all modules of the tester
 
     :param tester: The tester object
@@ -127,8 +117,6 @@ def get_modules(tester: GenericAnyTester) -> tuple[GenericAnyModule, ...]:
 
 async def reserve_module(module: GenericAnyModule, force: bool = True) -> None:
     """
-    .. versionadded:: 1.1
-
     Reserve a module regardless whether it is owned by others or not.
 
     :param module: The module to reserve
@@ -140,24 +128,22 @@ async def reserve_module(module: GenericAnyModule, force: bool = True) -> None:
     """
     r = await module.reservation.get()
     if force and r.operation == enums.ReservedStatus.RESERVED_BY_OTHER:
-        await free_module(module, True)
+        await release_module(module, True)
         await module.reservation.set_reserve()
     elif r.operation == enums.ReservedStatus.RELEASED:
         await module.reservation.set_reserve()
 
 
-async def free_module(
-    module: GenericAnyModule, should_free_ports: bool = False
+async def release_module(
+    module: GenericAnyModule, should_release_ports: bool = False
 ) -> None:
     """
-    .. versionadded:: 1.2
-
     Free a module. If the module is reserved by you, release the module. If the module is reserved by others, relinquish the module. The module should have no owner afterwards.
 
     :param module: The module to free
     :type module: :class:`~xoa_driver.modules.GenericAnyModule`
-    :param should_free_ports: should ports also be freed, defaults to False
-    :type should_free_ports: bool, optional
+    :param should_release_ports: should ports also be freed, defaults to False
+    :type should_release_ports: bool, optional
     :return:
     :rtype: None
     """
@@ -166,16 +152,14 @@ async def free_module(
         await module.reservation.set_relinquish()
     elif r.operation == enums.ReservedStatus.RESERVED_BY_YOU:
         await module.reservation.set_release()
-    if should_free_ports:
-        await free_ports(*module.ports)
+    if should_release_ports:
+        await release_ports(*module.ports)
 
 
 def get_module_supported_media(
     module: GenericL23Module | ModuleChimera,
 ) -> list[dict[str, t.Any]]:
     """
-    .. versionadded:: 1.3
-
     Get a list of supported media, port speed and count of the module.
 
     :param module: The module object
@@ -203,8 +187,6 @@ async def set_module_media_config(
     force: bool = True,
 ) -> None:
     """
-    .. versionadded:: 1.3
-
     Set module's media configuration.
 
     :param module: The module object
@@ -241,8 +223,6 @@ async def set_module_port_config(
     force: bool = True,
 ) -> None:
     """
-    .. versionadded:: 1.3
-
     Set module's port-speed configuration
 
     :param module: The module object
@@ -259,7 +239,7 @@ async def set_module_port_config(
     """
 
     # reserve the module first
-    await free_module(module, True)
+    await release_module(module, True)
     await reserve_module(module, force)
 
     # get the supported media by the module
@@ -280,15 +260,13 @@ async def set_module_port_config(
         ):
             portspeed_list = [port_count] + port_count * [port_speed]
             await module.cfp.config.set(portspeed_list=portspeed_list)
-            await free_module(module, False)
+            await release_module(module, False)
             return None
     raise NotSupportPortSpeed(module)
 
 
 async def get_module_eol_date(module: GenericAnyModule) -> str:
     """
-    .. versionadded:: 1.3
-
     Get module's End-of-Life date
 
     :param module: The module object
@@ -303,8 +281,6 @@ async def get_module_eol_date(module: GenericAnyModule) -> str:
 
 async def get_module_eol_days(module: GenericAnyModule) -> int:
     """
-    .. versionadded:: 1.3
-
     Get days until module's End-of-Life date
 
     :param module: The module object
@@ -321,8 +297,6 @@ async def get_module_eol_days(module: GenericAnyModule) -> int:
 
 async def get_module_cage_insertion_count(module: Z800FreyaModule, cage_index: int) -> int:
     """
-    .. versionadded:: 2.7.2
-
     Get module cage insertion count
 
     :param module: The Z800 Freya module object
@@ -352,8 +326,6 @@ async def get_module_cage_insertion_count(module: Z800FreyaModule, cage_index: i
 
 def get_all_ports(tester: GenericAnyTester) -> tuple[GenericAnyPort, ...]:
     """
-    .. versionadded:: 1.1
-
     Get all ports of the tester
 
     :param tester: The tester object
@@ -367,8 +339,6 @@ def get_all_ports(tester: GenericAnyTester) -> tuple[GenericAnyPort, ...]:
 
 def get_ports(tester: GenericAnyTester, module_id: int) -> tuple[GenericAnyPort, ...]:
     """
-    .. versionadded:: 1.1
-
     Get all ports of the module
 
     :param tester: The tester object
@@ -384,8 +354,6 @@ def get_ports(tester: GenericAnyTester, module_id: int) -> tuple[GenericAnyPort,
 
 def get_port(tester: GenericAnyTester, module_id: int, port_id: int) -> GenericAnyPort:
     """
-    .. versionadded:: 1.1
-
     Get a port of the module
 
     :param tester: The tester object
@@ -402,10 +370,8 @@ def get_port(tester: GenericAnyTester, module_id: int, port_id: int) -> GenericA
     return module.ports.obtain(port_id)
 
 
-async def reserve_port(port: GenericAnyPort, force: bool = True) -> None:
+async def reserve_port(port: GenericAnyPort, force: bool = True, reset: bool = False) -> None:
     """
-    .. versionadded:: 1.1
-
     Reserve a port regardless whether it is owned by others or not.
 
     :param port: The port to reserve
@@ -423,27 +389,12 @@ async def reserve_port(port: GenericAnyPort, force: bool = True) -> None:
         )
     elif r.status == enums.ReservedStatus.RELEASED:
         await port.reservation.set_reserve()
+    if reset:
+        await port.reset.set()
 
 
-async def reset_port(port: GenericAnyPort) -> None:
-    """
-    .. versionadded:: 1.1
-
-    Reserve and reset a port
-
-    :param port: The port to reset
-    :type port: GenericAnyPort
-    :return:
-    :rtype: None
-    """
-    await reserve_port(port, False)
-    await port.reset.set()
-
-
-async def free_port(port: GenericAnyPort) -> None:
+async def release_port(port: GenericAnyPort) -> None:
     """
-    .. versionadded:: 1.1
-
     Free a port. If the port is reserved by you, release the port. If the port is reserved by others, relinquish the port. The port should have no owner afterwards.
 
     :param port: The port to free
@@ -458,16 +409,14 @@ async def free_port(port: GenericAnyPort) -> None:
         await port.reservation.set_release()
 
 
-async def free_ports(*ports: GenericAnyPort) -> None:
+async def release_ports(*ports: GenericAnyPort) -> None:
     """
-    .. versionadded:: 1.1
-
-    Free all ports on a module.
+    Free a list of ports. If the port is reserved by you, release the port. If the port is reserved by others, relinquish the port. The port should have no owner afterwards.
 
-    :param port: The port to free
-    :type port: GenericAnyPort
+    :param ports: The ports to free
+    :type ports: GenericAnyPort
     """
-    await asyncio.gather(*(free_port(port=p) for p in ports))
+    await asyncio.gather(*(release_port(port=p) for p in ports))
 
 
 
@@ -477,12 +426,10 @@ async def free_ports(*ports: GenericAnyPort) -> None:
 # region Streams
 async def remove_streams(port: GenericAnyPort) -> None:
     """
-    .. versionadded:: 2.1
+    Remove all streams on a port witout resetting the port.
 
-    Remove all streams on a port.
-
-    :param module: The port object
-    :type module: GenericAnyPort
+    :param port: The port object
+    :type port: GenericAnyPort
     """
     await port.streams.server_sync()
     await asyncio.gather(*(s.delete() for s in port.streams))
@@ -491,10 +438,10 @@ async def remove_streams(port: GenericAnyPort) -> None:
 # endregion
 
 __all__ = (
-    "free_module",
-    "free_port",
-    "free_ports",
-    "free_tester",
+    "release_module",
+    "release_port",
+    "release_ports",
+    "release_tester",
     "get_all_ports",
     "get_module",
     "get_module_eol_date",
@@ -506,7 +453,6 @@ __all__ = (
     "reserve_module",
     "reserve_port",
     "reserve_tester",
-    "reset_port",
     "set_module_media_config",
     "set_module_port_config",
     "remove_streams",

xoa_driver/functions/tools.py

@@ -253,4 +253,16 @@ def dictionize_anlt_log_ctrl_status(
         "fsm_lt_stimuli": _fsm_lt_stimuli,
         "fsm_lt_alg0": _fsm_lt_alg0,
         "fsm_lt_algn1": _fsm_lt_algn1,
-    }
+    }
+
+__all__ = (
+    "get_ctx",
+    "dictionize_autoneg_status",
+    "dictionize_lt_status",
+    "dictionize_txtap_get",
+    "dictionize_anlt_status",
+    "dictionize_lt_im_status",
+    "dictionize_lt_algorithm_status",
+    "MODULE_EOL_INFO",
+    "dictionize_anlt_log_ctrl_status",
+)