superrtl 0.2.0__py3-none-any.whl

superrtl/__init__.py

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+"""
+SuperRTL - Verilog EDA 工具的 MCP/CLI 客户端
+"""
+
+__version__ = "0.2.0"
+__author__ = "RTL-Agent Team"

superrtl/cli.py

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+"""
+SuperRTL CLI 命令行工具
+"""
+
+import asyncio
+from pathlib import Path
+
+import click
+from rich.console import Console
+from rich.syntax import Syntax
+
+from . import __version__
+
+console = Console()
+
+
+@click.group()
+@click.version_option(version=__version__, prog_name="superrtl")
+def main():
+    """SuperRTL - Verilog EDA 工具的 MCP/CLI 客户端"""
+    pass
+
+
+@main.command()
+@click.argument("file", type=click.Path(exists=True))
+@click.option("--top", "-t", default="", help="顶层模块名")
+def compile(file: str, top: str):
+    """编译 Verilog 代码"""
+    from .tools import compile_verilog
+
+    code = Path(file).read_text()
+    result = asyncio.run(compile_verilog(code, top))
+
+    if result.get("success"):
+        console.print(f"[OK] [green]编译成功[/green]: {result.get('top_module')}")
+        console.print(f"   耗时: {result.get('duration')}s")
+    else:
+        console.print("[FAIL] [red]编译失败[/red]")
+        for error in result.get("errors", []):
+            console.print(f"   {error}")
+
+
+@main.command()
+@click.argument("design", type=click.Path(exists=True))
+@click.argument("testbench", type=click.Path(exists=True))
+@click.option("--timeout", "-t", default=30, help="超时时间 (秒)")
+def simulate(design: str, testbench: str, timeout: int):
+    """运行 Verilog 仿真"""
+    from .tools import simulate_verilog
+
+    design_code = Path(design).read_text()
+    tb_code = Path(testbench).read_text()
+    result = asyncio.run(simulate_verilog(design_code, tb_code, timeout))
+
+    if result.get("success"):
+        if result.get("passed"):
+            console.print("[OK] [green]仿真通过[/green]")
+        else:
+            console.print("[FAIL] [red]仿真失败[/red]")
+        console.print(f"   耗时: {result.get('duration')}s")
+        if result.get("output"):
+            console.print(f"   输出: {result['output'][:200]}")
+    else:
+        console.print(f"[FAIL] [red]仿真错误[/red]: {result.get('error')}")
+
+
+@main.command()
+@click.argument("file", type=click.Path(exists=True))
+@click.option(
+    "--style", "-s", default="default",
+    type=click.Choice(["default", "strict", "relaxed"])
+)
+def lint(file: str, style: str):
+    """Lint 检查"""
+    from .tools import lint_verilog
+
+    code = Path(file).read_text()
+    result = asyncio.run(lint_verilog(code, style))
+
+    if result.get("success"):
+        console.print("[OK] [green]Lint 通过[/green]")
+    else:
+        console.print("[FAIL] [red]Lint 失败[/red]")
+
+    if result.get("warnings"):
+        console.print(f"   警告: {len(result['warnings'])}")
+        for w in result["warnings"][:5]:
+            console.print(f"     - {w}")
+
+    if result.get("errors"):
+        console.print(f"   错误: {len(result['errors'])}")
+        for e in result["errors"][:5]:
+            console.print(f"     - {e}")
+
+
+@main.command()
+@click.argument("file", type=click.Path(exists=True))
+@click.option("--top", "-t", default="", help="顶层模块名")
+@click.option("--target", default="generic", type=click.Choice(["generic", "xilinx", "ice40"]))
+def synthesize(file: str, top: str, target: str):
+    """综合检查"""
+    from .tools import synthesize_verilog
+
+    code = Path(file).read_text()
+    result = asyncio.run(synthesize_verilog(code, top, target))
+
+    if result.get("success"):
+        console.print(f"[OK] [green]综合通过[/green]: {result.get('top_module')}")
+        if result.get("resources"):
+            console.print("   资源:")
+            for k, v in result["resources"].items():
+                console.print(f"     {k}: {v}")
+    else:
+        console.print("[FAIL] [red]综合失败[/red]")
+        for error in result.get("errors", []):
+            console.print(f"   {error}")
+
+
+@main.command()
+@click.argument("file", type=click.Path(exists=True))
+@click.option("--style", "-s", default="basic", type=click.Choice(["basic", "comprehensive"]))
+@click.option("--cases", "-c", default=3, help="测试用例数量")
+@click.option("--output", "-o", default="", help="输出文件路径")
+def testbench(file: str, style: str, cases: int, output: str):
+    """生成 Testbench"""
+    from .tools import generate_testbench
+
+    code = Path(file).read_text()
+    result = asyncio.run(generate_testbench(code, style, cases))
+
+    if result.get("success"):
+        tb_code = result["testbench"]
+
+        if output:
+            Path(output).write_text(tb_code)
+            console.print(f"[OK] [green]Testbench 已保存[/green]: {output}")
+        else:
+            console.print(Syntax(tb_code, "verilog"))
+    else:
+        console.print("[FAIL] [red]生成失败[/red]")
+
+
+@main.command()
+@click.argument("file", type=click.Path(exists=True))
+@click.option("--signals", "-s", multiple=True, help="要分析的信号")
+def waveform(file: str, signals: tuple):
+    """分析波形"""
+    from .tools import analyze_waveform
+
+    result = asyncio.run(
+        analyze_waveform(vcd_file=file, signals=list(signals) if signals else None)
+    )
+
+    if result.get("success"):
+        console.print("[INFO] [blue]波形分析[/blue]")
+        console.print(f"   信号数: {len(result.get('signals', {}))}")
+        if result.get("ascii_waveform"):
+            console.print("\n" + result["ascii_waveform"])
+    else:
+        console.print(f"[FAIL] [red]分析失败[/red]: {result.get('error')}")
+
+
+@main.command("check-tools")
+def check_tools_cmd():
+    """检查 EDA 工具安装状态"""
+    from .setup import check_tools
+    check_tools()
+
+
+@main.command()
+@click.option("--force", "-f", is_flag=True, help="强制重新安装")
+def setup(force: bool):
+    """安装 EDA 工具（首次运行时自动下载）"""
+    from .setup import install_tools
+    install_tools(force=force)
+
+
+@main.command()
+def uninstall():
+    """卸载 EDA 工具"""
+    from .setup import uninstall_tools
+
+    if click.confirm("确定要卸载 EDA 工具吗？"):
+        uninstall_tools()
+
+
+@main.command()
+@click.option("--transport", "-t", default="stdio", type=click.Choice(["stdio", "sse"]))
+@click.option("--port", "-p", default=8080, help="SSE 端口")
+def mcp(transport: str, port: int):
+    """启动 MCP Server"""
+    from .server import main as server_main
+
+    if transport == "stdio":
+        console.print("[START] [green]启动 SuperRTL MCP Server (stdio 模式)[/green]")
+        server_main()
+    else:
+        console.print(f"[START] [green]启动 SuperRTL MCP Server (SSE 模式, 端口: {port})[/green]")
+        console.print("[yellow]SSE 模式暂未实现，请使用 stdio 模式[/yellow]")
+
+
+if __name__ == "__main__":
+    main()

superrtl/resources/__init__.py

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+"""
+MCP Resources 实现
+"""
+
+from .skills import get_skill, list_skills
+from .templates import get_template, list_templates
+
+__all__ = [
+    "get_skill",
+    "list_skills",
+    "get_template",
+    "list_templates",
+]

superrtl/resources/skills.py

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+"""
+Skills 资源管理
+"""
+
+import json
+from pathlib import Path
+
+# Skills 目录
+# 优先使用包内的 shared 目录（安装后）
+# 回退到项目根目录的 shared 目录（开发模式）
+_PACKAGE_DIR = Path(__file__).parent.parent
+SKILLS_DIR = _PACKAGE_DIR / "shared" / "skills"
+
+# 如果包内没有，尝试项目根目录（开发模式）
+if not SKILLS_DIR.exists():
+    SKILLS_DIR = _PACKAGE_DIR.parent.parent / "shared" / "skills"
+
+
+async def list_skills() -> str:
+    """列出所有可用的 Skills"""
+    skills = []
+
+    if SKILLS_DIR.exists():
+        for skill_file in SKILLS_DIR.glob("*.md"):
+            skill_name = skill_file.stem.replace("verilog_", "")
+            skills.append(skill_name)
+
+    return json.dumps({
+        "skills": skills,
+        "count": len(skills)
+    }, ensure_ascii=False)
+
+
+async def get_skill(skill_name: str) -> str:
+    """获取指定 Skill 的内容"""
+    # 尝试不同的文件名格式
+    possible_names = [
+        f"verilog_{skill_name}.md",
+        f"{skill_name}.md",
+    ]
+
+    for name in possible_names:
+        skill_file = SKILLS_DIR / name
+        if skill_file.exists():
+            return skill_file.read_text(encoding="utf-8")
+
+    # 如果找不到，返回错误
+    available = []
+    if SKILLS_DIR.exists():
+        for f in SKILLS_DIR.glob("*.md"):
+            available.append(f.stem.replace("verilog_", ""))
+
+    return json.dumps({
+        "error": f"Skill 未找到: {skill_name}",
+        "available": available
+    }, ensure_ascii=False)

superrtl/resources/templates.py

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+"""
+模板资源管理
+"""
+
+import json
+from pathlib import Path
+
+# 模板目录
+# 优先使用包内的 shared 目录（安装后）
+# 回退到项目根目录的 shared 目录（开发模式）
+_PACKAGE_DIR = Path(__file__).parent.parent
+TEMPLATES_DIR = _PACKAGE_DIR / "shared" / "templates"
+
+# 如果包内没有，尝试项目根目录（开发模式）
+if not TEMPLATES_DIR.exists():
+    TEMPLATES_DIR = _PACKAGE_DIR.parent.parent / "shared" / "templates"
+
+
+async def list_templates() -> str:
+    """列出所有可用的模板"""
+    templates = []
+
+    if TEMPLATES_DIR.exists():
+        for template_file in TEMPLATES_DIR.glob("*.v"):
+            templates.append(template_file.stem)
+
+    return json.dumps({
+        "templates": templates,
+        "count": len(templates)
+    }, ensure_ascii=False)
+
+
+async def get_template(template_name: str) -> str:
+    """获取指定模板的内容"""
+    possible_names = [
+        f"{template_name}.v",
+        f"{template_name}.sv",
+    ]
+
+    for name in possible_names:
+        template_file = TEMPLATES_DIR / name
+        if template_file.exists():
+            return template_file.read_text(encoding="utf-8")
+
+    # 如果找不到，返回错误
+    available = []
+    if TEMPLATES_DIR.exists():
+        for f in TEMPLATES_DIR.glob("*.v"):
+            available.append(f.stem)
+
+    return json.dumps({
+        "error": f"模板未找到: {template_name}",
+        "available": available
+    }, ensure_ascii=False)

superrtl/runtime.py

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+"""
+运行时环境管理
+
+管理 EDA 工具的路径和环境变量
+"""
+
+import os
+import sys
+from pathlib import Path
+
+
+def get_project_root() -> Path:
+    """获取项目根目录（当前工作目录）"""
+    return Path.cwd()
+
+
+def get_tools_dir() -> Path:
+    """获取工具安装目录"""
+    return get_project_root() / ".superrtl"
+
+
+def get_oss_cad_suite_dir() -> Path:
+    """获取 OSS CAD Suite 目录"""
+    return get_tools_dir() / "oss-cad-suite"
+
+
+def get_tools_bin_dir() -> Path:
+    """获取工具 bin 目录"""
+    return get_oss_cad_suite_dir() / "bin"
+
+
+def get_tool_path(tool_name: str) -> str:
+    """
+    获取工具的完整路径
+
+    优先使用本地安装的工具，回退到系统 PATH
+
+    Args:
+        tool_name: 工具名称 (如 iverilog, yosys, verilator)
+
+    Returns:
+        工具的完整路径或工具名（回退到系统 PATH）
+    """
+    bin_dir = get_tools_bin_dir()
+
+    if sys.platform == "win32":
+        tool_path = bin_dir / f"{tool_name}.exe"
+    else:
+        tool_path = bin_dir / tool_name
+
+    if tool_path.exists():
+        return str(tool_path)
+
+    # 回退到系统 PATH
+    return tool_name
+
+
+def get_environ() -> dict:
+    """
+    获取包含工具路径的环境变量
+
+    将本地工具目录添加到 PATH 最前面
+    """
+    env = os.environ.copy()
+
+    # 添加 bin 和 lib 目录到 PATH
+    oss_dir = get_oss_cad_suite_dir()
+    dirs_to_add = [
+        str(oss_dir / "bin"),
+        str(oss_dir / "lib"),
+    ]
+
+    current_path = env.get("PATH", "")
+    for d in dirs_to_add:
+        if d not in current_path:
+            current_path = d + os.pathsep + current_path
+
+    env["PATH"] = current_path
+
+    return env
+
+
+def tools_installed() -> bool:
+    """检查工具是否已安装"""
+    bin_dir = get_tools_bin_dir()
+
+    if sys.platform == "win32":
+        return (bin_dir / "iverilog.exe").exists()
+    else:
+        return (bin_dir / "iverilog").exists()
+
+
+def get_tools_status() -> dict:
+    """获取工具安装状态"""
+    tools = {
+        "iverilog": "Icarus Verilog (编译仿真)",
+        "vvp": "Icarus Verilog (仿真器)",
+        "yosys": "Yosys (综合检查)",
+        "verilator": "Verilator (Lint)",
+    }
+
+    status = {}
+    bin_dir = get_tools_bin_dir()
+
+    for tool, desc in tools.items():
+        if sys.platform == "win32":
+            tool_path = bin_dir / f"{tool}.exe"
+        else:
+            tool_path = bin_dir / tool
+
+        status[tool] = {
+            "name": desc,
+            "installed": tool_path.exists(),
+            "path": str(tool_path) if tool_path.exists() else None,
+        }
+
+    return status

superrtl/server.py

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+"""
+SuperRTL MCP Server
+
+提供 Verilog EDA 工具的 MCP 接口
+"""
+
+import asyncio
+import json
+
+from mcp import types
+from mcp.server import Server
+from mcp.server.stdio import stdio_server
+
+from .resources import get_skill, get_template, list_skills, list_templates
+from .tools import (
+    analyze_waveform,
+    compile_verilog,
+    generate_testbench,
+    lint_verilog,
+    simulate_verilog,
+    synthesize_verilog,
+)
+
+# 创建 MCP Server 实例
+app = Server("superrtl")
+
+
+# ============ Tools 定义 ============
+
+TOOLS = [
+    types.Tool(
+        name="compile_verilog",
+        description="使用 Icarus Verilog 编译 Verilog 代码",
+        inputSchema={
+            "type": "object",
+            "properties": {
+                "code": {"type": "string", "description": "Verilog 源代码"},
+                "top_module": {"type": "string", "description": "顶层模块名 (可选)", "default": ""},
+            },
+            "required": ["code"],
+        },
+    ),
+    types.Tool(
+        name="simulate_verilog",
+        description="使用 Icarus Verilog 运行仿真",
+        inputSchema={
+            "type": "object",
+            "properties": {
+                "code": {"type": "string", "description": "Verilog 源代码"},
+                "testbench": {"type": "string", "description": "测试平台代码"},
+                "timeout": {"type": "integer", "description": "仿真超时时间 (秒)", "default": 30},
+            },
+            "required": ["code", "testbench"],
+        },
+    ),
+    types.Tool(
+        name="lint_verilog",
+        description="使用 Verilator 进行 Lint 检查",
+        inputSchema={
+            "type": "object",
+            "properties": {
+                "code": {"type": "string", "description": "Verilog 源代码"},
+                "style": {
+                    "type": "string",
+                    "description": "检查风格",
+                    "enum": ["default", "strict", "relaxed"],
+                    "default": "default",
+                },
+            },
+            "required": ["code"],
+        },
+    ),
+    types.Tool(
+        name="synthesize_verilog",
+        description="使用 Yosys 进行综合检查",
+        inputSchema={
+            "type": "object",
+            "properties": {
+                "code": {"type": "string", "description": "Verilog 源代码"},
+                "top_module": {"type": "string", "description": "顶层模块名", "default": ""},
+                "target": {
+                    "type": "string",
+                    "description": "目标工艺库",
+                    "enum": ["generic", "xilinx", "ice40"],
+                    "default": "generic",
+                },
+            },
+            "required": ["code"],
+        },
+    ),
+    types.Tool(
+        name="generate_testbench",
+        description="自动生成 Testbench",
+        inputSchema={
+            "type": "object",
+            "properties": {
+                "code": {"type": "string", "description": "Verilog 源代码"},
+                "style": {
+                    "type": "string",
+                    "description": "测试风格",
+                    "enum": ["basic", "comprehensive"],
+                    "default": "basic",
+                },
+                "test_cases": {"type": "integer", "description": "测试用例数量", "default": 3},
+            },
+            "required": ["code"],
+        },
+    ),
+    types.Tool(
+        name="analyze_waveform",
+        description="分析 VCD 波形文件",
+        inputSchema={
+            "type": "object",
+            "properties": {
+                "vcd_file": {"type": "string", "description": "VCD 文件路径"},
+                "vcd_content": {"type": "string", "description": "VCD 内容 (直接传入)"},
+                "signals": {
+                    "type": "array",
+                    "items": {"type": "string"},
+                    "description": "要分析的信号列表",
+                },
+            },
+        },
+    ),
+]
+
+
+# ============ 注册处理器 ============
+
+@app.list_tools()
+async def list_tools() -> list[types.Tool]:
+    """列出所有可用的工具"""
+    return TOOLS
+
+
+@app.call_tool()
+async def call_tool(name: str, arguments: dict) -> list[types.TextContent]:
+    """处理工具调用"""
+    try:
+        if name == "compile_verilog":
+            result = await compile_verilog(
+                arguments["code"],
+                arguments.get("top_module", "")
+            )
+        elif name == "simulate_verilog":
+            result = await simulate_verilog(
+                arguments["code"],
+                arguments["testbench"],
+                arguments.get("timeout", 30)
+            )
+        elif name == "lint_verilog":
+            result = await lint_verilog(
+                arguments["code"],
+                arguments.get("style", "default")
+            )
+        elif name == "synthesize_verilog":
+            result = await synthesize_verilog(
+                arguments["code"],
+                arguments.get("top_module", ""),
+                arguments.get("target", "generic")
+            )
+        elif name == "generate_testbench":
+            result = await generate_testbench(
+                arguments["code"],
+                arguments.get("style", "basic"),
+                arguments.get("test_cases", 3)
+            )
+        elif name == "analyze_waveform":
+            result = await analyze_waveform(
+                arguments.get("vcd_file"),
+                arguments.get("vcd_content"),
+                arguments.get("signals")
+            )
+        else:
+            result = {"success": False, "error": f"未知工具: {name}"}
+
+        return [types.TextContent(type="text", text=json.dumps(result, ensure_ascii=False))]
+
+    except Exception as e:
+        return [types.TextContent(
+            type="text",
+            text=json.dumps({"success": False, "error": str(e)}, ensure_ascii=False)
+        )]
+
+
+# ============ Resources 定义 ============
+
+@app.list_resources()
+async def list_resources() -> list[types.Resource]:
+    """列出所有可用的资源"""
+    resources = []
+
+    # Skills
+    skills_data = json.loads(await list_skills())
+    for skill in skills_data.get("skills", []):
+        resources.append(types.Resource(
+            uri=f"skills://{skill}",
+            name=f"Skill: {skill}",
+            description=f"Verilog 设计模式: {skill}",
+            mimeType="text/markdown",
+        ))
+
+    # Templates
+    templates_data = json.loads(await list_templates())
+    for template in templates_data.get("templates", []):
+        resources.append(types.Resource(
+            uri=f"templates://{template}",
+            name=f"Template: {template}",
+            description=f"Verilog 代码模板: {template}",
+            mimeType="text/plain",
+        ))
+
+    return resources
+
+
+@app.read_resource()
+async def read_resource(uri: str) -> str:
+    """读取资源内容"""
+    try:
+        if uri.startswith("skills://"):
+            skill_name = uri.replace("skills://", "")
+            return await get_skill(skill_name)
+        elif uri.startswith("templates://"):
+            template_name = uri.replace("templates://", "")
+            return await get_template(template_name)
+        else:
+            return json.dumps({"error": f"未知资源 URI: {uri}"}, ensure_ascii=False)
+    except Exception as e:
+        return json.dumps({"error": str(e)}, ensure_ascii=False)
+
+
+# ============ 启动函数 ============
+
+async def run_stdio():
+    """以 stdio 模式运行 (用于 MCP Host 连接)"""
+    async with stdio_server() as (read, write):
+        await app.run(read, write)
+
+
+def main():
+    """主入口"""
+    asyncio.run(run_stdio())
+
+
+if __name__ == "__main__":
+    main()