splat64 0.34.3__py3-none-any.whl → 0.35.0__py3-none-any.whl

splat/__init__.py

@@ -1,7 +1,7 @@
 __package_name__ = __name__
 
 # Should be synced with pyproject.toml
-__version__ = "0.34.3"
+__version__ = "0.35.0"
 __author__ = "ethteck"
 
 from . import util as util

splat/disassembler/spimdisasm_disassembler.py

@@ -7,7 +7,7 @@ from typing import Set
 
 class SpimdisasmDisassembler(disassembler.Disassembler):
     # This value should be kept in sync with the version listed on requirements.txt and pyproject.toml
-    SPIMDISASM_MIN = (1, 33, 0)
+    SPIMDISASM_MIN = (1, 36, 0)
 
     def configure(self):
         # Configure spimdisasm
@@ -93,9 +93,15 @@ class SpimdisasmDisassembler(disassembler.Disassembler):
         )
         spimdisasm.common.GlobalConfig.ASM_DATA_LABEL = options.opts.asm_data_macro
         spimdisasm.common.GlobalConfig.ASM_TEXT_END_LABEL = options.opts.asm_end_label
+        spimdisasm.common.GlobalConfig.ASM_DATA_END_LABEL = (
+            options.opts.asm_data_end_label
+        )
         spimdisasm.common.GlobalConfig.ASM_EHTBL_LABEL = (
             options.opts.asm_ehtable_label_macro
         )
+        spimdisasm.common.GlobalConfig.ASM_NM_LABEL = (
+            options.opts.asm_nonmatching_label_macro
+        )
 
         if options.opts.asm_emit_size_directive is not None:
             spimdisasm.common.GlobalConfig.ASM_EMIT_SIZE_DIRECTIVE = (

splat/scripts/create_config.py

@@ -6,7 +6,7 @@ from pathlib import Path
 
 from ..util.n64 import find_code_length, rominfo
 from ..util.psx import psxexeinfo
-from ..util import log
+from ..util import log, file_presets, conf
 
 
 def main(file_path: Path):
@@ -70,10 +70,6 @@ options:
   use_legacy_include_asm: False
   mips_abi_float_regs: o32
 
-  asm_function_macro: glabel
-  asm_jtbl_label_macro: jlabel
-  asm_data_macro: dlabel
-
   # section_order: [".text", ".data", ".rodata", ".bss"]
   # auto_link_sections: [".data", ".rodata", ".bss"]
 
@@ -111,7 +107,7 @@ segments:
     type: header
     start: 0x0
 
-  - name: boot
+  - name: ipl3
     type: bin
     start: 0x40
 
@@ -122,7 +118,7 @@ segments:
     subsegments:
       - [0x1000, hasm]
 """
-    if rom.entrypoint_info.data_size > 0:
+    if rom.entrypoint_info.data_size is not None:
         segments += f"""\
       - [0x{0x1000 + rom.entrypoint_info.entry_size:X}, data]
 """
@@ -139,7 +135,7 @@ segments:
 
     if rom.entrypoint_info.bss_size is not None:
         segments += f"""\
-    bss_size: 0x{rom.entrypoint_info.bss_size:X}
+    bss_size: 0x{rom.entrypoint_info.bss_size.value:X}
 """
 
     segments += f"""\
@@ -152,11 +148,13 @@ segments:
         and rom.entrypoint_info.bss_start_address is not None
         and first_section_end > main_rom_start
     ):
-        bss_start = rom.entrypoint_info.bss_start_address - rom.entry_point + 0x1000
+        bss_start = (
+            rom.entrypoint_info.bss_start_address.value - rom.entry_point + 0x1000
+        )
         # first_section_end points to the start of data
         segments += f"""\
       - [0x{first_section_end:X}, data]
-      - {{ type: bss, vram: 0x{rom.entrypoint_info.bss_start_address:08X} }}
+      - {{ type: bss, vram: 0x{rom.entrypoint_info.bss_start_address.value:08X} }}
 """
         # Point next segment to the detected end of the main one
         first_section_end = bss_start
@@ -174,12 +172,93 @@ segments:
   - [0x{rom.size:X}]
 """
 
-    out_file = f"{cleaned_basename}.yaml"
-    with open(out_file, "w", newline="\n") as f:
+    out_file = Path(f"{cleaned_basename}.yaml")
+    with out_file.open("w", newline="\n") as f:
         print(f"Writing config to {out_file}")
         f.write(header)
         f.write(segments)
 
+    # `file_presets` requires an initialized `opts`.
+    # A simple way to do that is to simply load the yaml we just generated.
+    conf.load([out_file])
+    file_presets.write_all_files()
+
+    # Write reloc_addrs.txt file
+    reloc_addrs = []
+    if rom.entrypoint_info.bss_start_address is not None:
+        reloc_addrs.append(
+            f"rom:0x{rom.entrypoint_info.bss_start_address.rom_hi:06X} reloc:MIPS_HI16 symbol:main_BSS_START"
+        )
+        reloc_addrs.append(
+            f"rom:0x{rom.entrypoint_info.bss_start_address.rom_lo:06X} reloc:MIPS_LO16 symbol:main_BSS_START"
+        )
+        reloc_addrs.append("")
+    if rom.entrypoint_info.bss_size is not None:
+        reloc_addrs.append(
+            f"rom:0x{rom.entrypoint_info.bss_size.rom_hi:06X} reloc:MIPS_HI16 symbol:main_BSS_SIZE"
+        )
+        reloc_addrs.append(
+            f"rom:0x{rom.entrypoint_info.bss_size.rom_lo:06X} reloc:MIPS_LO16 symbol:main_BSS_SIZE"
+        )
+        reloc_addrs.append("")
+    if rom.entrypoint_info.bss_end_address is not None:
+        reloc_addrs.append(
+            f"rom:0x{rom.entrypoint_info.bss_end_address.rom_hi:06X} reloc:MIPS_HI16 symbol:main_BSS_END"
+        )
+        reloc_addrs.append(
+            f"rom:0x{rom.entrypoint_info.bss_end_address.rom_lo:06X} reloc:MIPS_LO16 symbol:main_BSS_END"
+        )
+        reloc_addrs.append("")
+    if rom.entrypoint_info.stack_top is not None:
+        reloc_addrs.append(
+            '// This entry corresponds to the "stack top", which is the end of the array used as the stack for the main segment.'
+        )
+        reloc_addrs.append(
+            "// It is commented out because it was not possible to infer what the start of the stack symbol is, so you'll have to figure it out by yourself."
+        )
+        reloc_addrs.append(
+            "// Once you have found it you can properly name it and specify the length of this stack as the addend value here."
+        )
+        reloc_addrs.append(
+            f"// The address of the end of the stack is 0x{rom.entrypoint_info.stack_top.value:08X}."
+        )
+        reloc_addrs.append(
+            f"// A common size for this stack is 0x2000, so try checking for the address 0x{rom.entrypoint_info.stack_top.value-0x2000:08X}. Note the stack may have a different size."
+        )
+        reloc_addrs.append(
+            f"// rom:0x{rom.entrypoint_info.stack_top.rom_hi:06X} reloc:MIPS_HI16 symbol:main_stack addend:0xXXXX"
+        )
+        reloc_addrs.append(
+            f"// rom:0x{rom.entrypoint_info.stack_top.rom_lo:06X} reloc:MIPS_LO16 symbol:main_stack addend:0xXXXX"
+        )
+        reloc_addrs.append("")
+    if reloc_addrs:
+        with Path("reloc_addrs.txt").open("w", newline="\n") as f:
+            print("Writing reloc_addrs.txt")
+            f.write(
+                "// Visit https://github.com/ethteck/splat/wiki/Advanced-Reloc for documentation about this file\n"
+            )
+            f.write("// entrypoint relocs\n")
+            contents = "\n".join(reloc_addrs)
+            f.write(contents)
+
+    # Write symbol_addrs.txt file
+    symbol_addrs = []
+    symbol_addrs.append(f"entrypoint = 0x{rom.entry_point:08X}; // type:func")
+    if rom.entrypoint_info.main_address is not None:
+        symbol_addrs.append(
+            f"main = 0x{rom.entrypoint_info.main_address.value:08X}; // type:func"
+        )
+    if symbol_addrs:
+        symbol_addrs.append("")
+        with Path("symbol_addrs.txt").open("w", newline="\n") as f:
+            print("Writing symbol_addrs.txt")
+            f.write(
+                "// Visit https://github.com/ethteck/splat/wiki/Adding-Symbols for documentation about this file\n"
+            )
+            contents = "\n".join(symbol_addrs)
+            f.write(contents)
+
 
 def create_psx_config(exe_path: Path, exe_bytes: bytes):
     exe = psxexeinfo.PsxExe.get_info(exe_path, exe_bytes)
@@ -211,10 +290,6 @@ options:
   o_as_suffix: True
   use_legacy_include_asm: False
 
-  asm_function_macro: glabel
-  asm_jtbl_label_macro: jlabel
-  asm_data_macro: dlabel
-
   section_order: [".rodata", ".text", ".data", ".bss"]
   # auto_link_sections: [".data", ".rodata", ".bss"]
 
@@ -251,7 +326,7 @@ segments:
 """
     text_offset = exe.text_offset
     if text_offset != 0x800:
-        segments += f"""\
+        segments += """\
       - [0x800, rodata, 800]
 """
     segments += f"""\
@@ -268,12 +343,17 @@ segments:
   - [0x{exe.size:X}]
 """
 
-    out_file = f"{cleaned_basename}.yaml"
-    with open(out_file, "w", newline="\n") as f:
+    out_file = Path(f"{cleaned_basename}.yaml")
+    with out_file.open("w", newline="\n") as f:
         print(f"Writing config to {out_file}")
         f.write(header)
         f.write(segments)
 
+    # `file_presets` requires an initialized `opts`.
+    # A simple way to do that is to simply load the yaml we just generated.
+    conf.load([out_file])
+    file_presets.write_all_files()
+
 
 def add_arguments_to_parser(parser: argparse.ArgumentParser):
     parser.add_argument(

splat/scripts/split.py

@@ -8,9 +8,9 @@ from pathlib import Path
 
 from .. import __package_name__, __version__
 from ..disassembler import disassembler_instance
-from ..util import cache_handler, progress_bar, vram_classes, statistics
+from ..util import cache_handler, progress_bar, vram_classes, statistics, file_presets
 
-from colorama import Fore, Style
+from colorama import Style
 from intervaltree import Interval, IntervalTree
 import sys
 
@@ -19,6 +19,7 @@ from ..segtypes.linker_entry import (
     get_segment_vram_end_symbol_name,
 )
 from ..segtypes.segment import Segment
+from ..segtypes.common.group import CommonSegGroup
 from ..util import conf, log, options, palettes, symbols, relocs
 
 linker_writer: LinkerWriter
@@ -38,6 +39,9 @@ def initialize_segments(config_segments: Union[dict, list]) -> List[Segment]:
     segments_by_name: Dict[str, Segment] = {}
     ret: List[Segment] = []
 
+    # Cross segment pairing can be quite expensive, so we try to avoid it if the user haven't requested it.
+    do_cross_segment_pairing = False
+
     last_rom_end = 0
 
     for i, seg_yaml in enumerate(config_segments):
@@ -80,6 +84,9 @@ def initialize_segments(config_segments: Union[dict, list]) -> List[Segment]:
 
             segments_by_name[segment.name] = segment
 
+        if segment.pair_segment_name is not None:
+            do_cross_segment_pairing = True
+
         ret.append(segment)
         if (
             isinstance(segment.rom_start, int)
@@ -112,6 +119,50 @@ def initialize_segments(config_segments: Union[dict, list]) -> List[Segment]:
             "Last segment in config cannot be a pad segment; see https://github.com/ethteck/splat/wiki/Segments#pad"
         )
 
+    if do_cross_segment_pairing:
+        # Do the cross segment pairing
+        for seg in ret:
+            if seg.pair_segment_name is not None:
+                found = False
+                for other_seg in ret:
+                    if seg == other_seg:
+                        continue
+                    if seg.pair_segment_name == other_seg.name and isinstance(
+                        other_seg, CommonSegGroup
+                    ):
+                        # We found the other segment specified by `pair_segment`
+
+                        if other_seg.pair_segment_name is not None:
+                            log.error(
+                                f"Both segments '{seg.name}' and '{other_seg.name}' have a `pair_segment` value, when only at most one of the cross-paired segments can have this attribute."
+                            )
+
+                        # Not user error, hopefully...
+                        assert (
+                            seg.paired_segment is None
+                        ), f"Somehow '{seg.name}' was already paired so something else? It is paired to '{seg.paired_segment.name}' instead of {other_seg.name}"
+                        assert (
+                            other_seg.paired_segment is None
+                        ), f"Somehow '{other_seg.name}' was already paired so something else? It is paired to '{other_seg.paired_segment.name}' instead of {seg.name}"
+
+                        found = True
+                        # Pair them
+                        seg.paired_segment = other_seg
+                        other_seg.paired_segment = seg
+
+                        if isinstance(seg, CommonSegGroup) and isinstance(
+                            other_seg, CommonSegGroup
+                        ):
+                            # Pair the subsegments
+                            seg.pair_subsegments_to_other_segment(other_seg)
+
+                        break
+
+                if not found:
+                    log.error(
+                        f"Segment '{seg.pair_segment_name}' not found.\n    It is referenced by segment '{seg.name}', because of the `pair_segment` attribute."
+                    )
+
     return ret
 
 
@@ -520,6 +571,8 @@ def main(
     if options.opts.is_mode_active("code"):
         dump_symbols()
 
+        file_presets.write_all_files()
+
 
 def add_arguments_to_parser(parser: argparse.ArgumentParser):
     parser.add_argument(

splat/segtypes/common/group.py

@@ -168,6 +168,10 @@ class CommonSegGroup(CommonSegment):
         for sub in self.subsegments:
             if sub.contains_vram(addr):
                 return sub
+        if isinstance(self.paired_segment, CommonSegGroup):
+            for sub in self.paired_segment.subsegments:
+                if sub.contains_vram(addr):
+                    return sub
         return None
 
     def get_next_subsegment_for_ram(
@@ -187,3 +191,22 @@ class CommonSegGroup(CommonSegment):
             if sub.vram_start > addr:
                 return sub
         return None
+
+    def pair_subsegments_to_other_segment(
+        self,
+        other_segment: "CommonSegGroup",
+    ):
+        # Pair cousins with the same name
+        for segment in self.subsegments:
+            for sibling in other_segment.subsegments:
+                if segment.name == sibling.name:
+                    # Make them reference each other
+                    segment.siblings[sibling.get_linker_section_linksection()] = sibling
+                    sibling.siblings[segment.get_linker_section_linksection()] = segment
+
+                    if segment.is_text():
+                        sibling.sibling = segment
+                    elif sibling.is_text():
+                        segment.sibling = sibling
+
+                    break

splat/segtypes/common/textbin.py

@@ -97,6 +97,8 @@ class CommonSegTextbin(CommonSegment):
 
             if self.is_text() and options.opts.asm_end_label != "":
                 f.write(f"{options.opts.asm_end_label} {sym.name}\n")
+            elif self.is_data() and options.opts.asm_data_end_label != "":
+                f.write(f"{options.opts.asm_data_end_label} {sym.name}\n")
 
             if sym.given_name_end is not None:
                 if (
@@ -106,6 +108,12 @@ class CommonSegTextbin(CommonSegment):
                     f.write(f"{asm_label} {sym.given_name_end}\n")
                     if asm_label == ".globl":
                         f.write(f"{sym.given_name_end}:\n")
+                    if self.is_text() and options.opts.asm_end_label != "":
+                        f.write(f"{options.opts.asm_end_label} {sym.given_name_end}\n")
+                    elif self.is_data() and options.opts.asm_data_end_label != "":
+                        f.write(
+                            f"{options.opts.asm_data_end_label} {sym.given_name_end}\n"
+                        )
 
     def split(self, rom_bytes):
         if self.rom_end is None:

splat/segtypes/linker_entry.py

@@ -522,7 +522,7 @@ class LinkerWriter:
             )
 
     def save_dependencies_file(self, output_path: Path, target_elf_path: Path):
-        output = f"{target_elf_path.as_posix()}:"
+        output = f"{clean_up_path(target_elf_path).as_posix()}:"
 
         for entry in self.dependencies_entries:
             if entry.object_path is None:

splat/segtypes/segment.py

@@ -274,6 +274,12 @@ class Segment:
                 return suggestion_rodata_section_start
         return None
 
+    @staticmethod
+    def parse_pair_segment(yaml: Union[dict, list]) -> Optional[str]:
+        if isinstance(yaml, dict) and "pair_segment" in yaml:
+            return yaml["pair_segment"]
+        return None
+
     def __init__(
         self,
         rom_start: Optional[int],
@@ -319,6 +325,9 @@ class Segment:
         self.parent: Optional[Segment] = None
         self.sibling: Optional[Segment] = None
         self.siblings: Dict[str, Segment] = {}
+        self.pair_segment_name: Optional[str] = self.parse_pair_segment(yaml)
+        self.paired_segment: Optional[Segment] = None
+
         self.file_path: Optional[Path] = None
 
         self.args: List[str] = args

splat/util/__init__.py

@@ -1,6 +1,7 @@
 from . import cache_handler as cache_handler
 from . import color as color
 from . import compiler as compiler
+from . import file_presets as file_presets
 from . import log as log
 from . import n64 as n64
 from . import options as options

splat/util/compiler.py

@@ -6,15 +6,18 @@ from typing import Optional, Dict
 class Compiler:
     name: str
     asm_function_macro: str = "glabel"
-    asm_function_alt_macro: str = "glabel"
-    asm_jtbl_label_macro: str = "glabel"
-    asm_data_macro: str = "glabel"
-    asm_end_label: str = ""
+    asm_function_alt_macro: str = "alabel"
+    asm_jtbl_label_macro: str = "jlabel"
+    asm_data_macro: str = "dlabel"
+    asm_end_label: str = "endlabel"
+    asm_data_end_label: str = "enddlabel"
     asm_ehtable_label_macro: str = "ehlabel"
+    asm_nonmatching_label_macro: str = "nonmatching"
     c_newline: str = "\n"
     asm_inc_header: str = ""
     asm_emit_size_directive: Optional[bool] = None
     j_as_branch: bool = False
+    uses_include_asm: bool = True
 
 
 GCC = Compiler(
@@ -30,12 +33,14 @@ SN64 = Compiler(
     asm_jtbl_label_macro=".globl",
     asm_data_macro=".globl",
     asm_end_label=".end",
+    asm_data_end_label="",
+    asm_nonmatching_label_macro="",
     c_newline="\r\n",
     asm_emit_size_directive=False,
     j_as_branch=True,
 )
 
-IDO = Compiler("IDO", asm_emit_size_directive=False)
+IDO = Compiler("IDO", asm_emit_size_directive=False, uses_include_asm=False)
 
 KMC = Compiler(
     "KMC",
@@ -55,7 +60,7 @@ PSYQ = Compiler(
 )
 
 # PS2
-MWCCPS2 = Compiler("MWCCPS2")
+MWCCPS2 = Compiler("MWCCPS2", uses_include_asm=False)
 EEGCC = Compiler("EEGCC")
 
 compiler_for_name: Dict[str, Compiler] = {