sm-blueprint-lib 0.0.1__py3-none-any.whl

sm_blueprint_lib/prebuilds/decoder.py

@@ -0,0 +1,56 @@
+from typing import Sequence
+from numpy import ndarray
+from sm_blueprint_lib import get_bits_required, check_pos, connect, num_to_bit_list
+from sm_blueprint_lib.blueprint import Blueprint
+from sm_blueprint_lib.parts.logicgate import LogicGate
+from sm_blueprint_lib.pos import Pos
+
+
+def decoder(bp: Blueprint, num_address: int, pos: Pos | Sequence = (0, 0, 0),
+            precreated_inputs_binary=None, precreated_outputs=None, precreated_output_enable=None,
+            address_divisor=1, with_enable=True):
+    pos = check_pos(pos)
+
+    if precreated_inputs_binary is not None:
+        inputs_binary = precreated_inputs_binary
+    else:
+        inputs_binary = ndarray(
+            (get_bits_required(num_address), 2), dtype=LogicGate)
+    if precreated_outputs is not None:
+        outputs = precreated_outputs
+    else:
+        outputs = [LogicGate(pos + (x+1, 0, 0), "0000FF")
+                   for x in range(num_address)]
+    if with_enable:
+        if precreated_output_enable is not None:
+            output_enable = precreated_output_enable
+        else:
+            output_enable = LogicGate(pos + (0, 0, 0), "FF0000", 1)
+
+    if precreated_inputs_binary is None:
+        for b in range(get_bits_required(num_address)):
+            inputs_binary[b, :] = [
+                LogicGate(pos + (b+1, 1, 0), "FF0000", 4),
+                LogicGate(pos + (b+1, 2, 0), "FF0000", 1),
+            ]
+
+    for x in range(num_address):
+        bit_mask = num_to_bit_list(
+            x//address_divisor, get_bits_required(num_address//address_divisor))
+        connect(inputs_binary[~bit_mask, 0], outputs[x])
+        connect(inputs_binary[bit_mask, 1], outputs[x])
+    if with_enable:
+        connect(output_enable, outputs)
+
+    if precreated_inputs_binary is None:
+        bp.add(inputs_binary)
+    if precreated_outputs is None:
+        bp.add(outputs)
+    if with_enable:
+        if precreated_output_enable is None:
+            bp.add(output_enable)
+
+    if with_enable:
+        return inputs_binary, outputs, output_enable
+    else:
+        return inputs_binary, outputs

sm_blueprint_lib/prebuilds/distance_sensor.py

@@ -0,0 +1,45 @@
+from typing import Sequence
+from numpy import array, ndarray
+from sm_blueprint_lib import get_bits_required, check_pos, connect, num_to_bit_list
+from sm_blueprint_lib.blueprint import Blueprint
+from sm_blueprint_lib.parts.logicgate import LogicGate
+from sm_blueprint_lib.parts.sensor import Sensor5
+from sm_blueprint_lib.parts.timer import Timer
+from sm_blueprint_lib.pos import Pos
+
+
+def distance_sensor(bp: Blueprint,
+                    sensor_range: range,
+                    pos: Pos | Sequence = (0, 0, 0)):
+    pos = check_pos(pos)
+    bit_length = get_bits_required(len(sensor_range))
+    out = [LogicGate(pos + (x, 0, 0), "0000FF", 2) for x in range(bit_length)]
+    out = array(out, dtype=LogicGate)
+    sensors = [Sensor5(pos + (bit_length, -1, 1), "000000",
+                       (False, True, "FFFFFF", False, x), xaxis=-3, zaxis=1) for x in sensor_range]
+
+    current_output_state = 0
+    for target in reversed(range(len(sensor_range))):
+        difference = current_output_state ^ (target+1)
+        if difference:
+            bit_mask = num_to_bit_list(difference, bit_length)
+            connect(sensors[target], out[bit_mask])
+            current_output_state ^= difference
+
+    bp.add(out, sensors)
+    return out, sensors
+
+
+def distance_sensor_raycast(bp: Blueprint,
+                            sensor_range: range,
+                            pos: Pos | Sequence = (0, 0, 0)):
+    pos = check_pos(pos)
+    bit_length = len(sensor_range)
+    out = [LogicGate(pos + (x, 0, 0), "0000FF", 2) for x in range(bit_length)]
+    sensors = [Sensor5(pos + (bit_length, -1, 0), "000000",
+                       (False, True, "FFFFFF", False, x), xaxis=1, zaxis=3) for x in sensor_range]
+
+    connect(sensors, out)
+
+    bp.add(out, sensors)
+    return out, sensors

sm_blueprint_lib/prebuilds/ram.py

@@ -0,0 +1,90 @@
+from itertools import cycle
+from typing import Sequence
+from numpy import ndarray
+from sm_blueprint_lib import get_bits_required, check_pos, connect
+from sm_blueprint_lib.blueprint import Blueprint
+from sm_blueprint_lib.parts.logicgate import LogicGate
+from sm_blueprint_lib.pos import Pos
+from sm_blueprint_lib.prebuilds.decoder import decoder
+
+
+def ram(bp: Blueprint, bit_length: int, num_address: int, pos: Pos | Sequence = (0, 0, 0),
+        address_divisor=1,
+        pre_arr=None, pre_inputs=None, pre_outputs=None):
+    pos = check_pos(pos)
+
+    arr = pre_arr if pre_arr is not None else ndarray(
+        (bit_length, num_address, 4), dtype=LogicGate)
+    writers = [LogicGate(pos + (-1, 2, y), "000000", xaxis=1, zaxis=3)
+               for y in range(num_address)]
+    readers = [LogicGate(pos + (-1, 0, y), "000000", xaxis=1, zaxis=3)
+               for y in range(num_address)]
+    inputs = pre_inputs if pre_inputs is not None else [LogicGate(pos + (x, 1, -1), "FF0000", 1, xaxis=1, zaxis=3)
+                                                        for x in range(bit_length)]
+    outputs = pre_outputs if pre_outputs is not None else [LogicGate(pos + (x, 1, -2), "0000FF", 1, xaxis=1, zaxis=3)
+                                                           for x in range(bit_length)]
+    writers_binary = ndarray(
+        (get_bits_required(num_address//address_divisor), 2), dtype=LogicGate)
+    write_enable = LogicGate(pos + (-1, 2, -1), "FF0000", 1, xaxis=1, zaxis=3)
+    readers_binary = ndarray(
+        (get_bits_required(num_address//address_divisor), 2), dtype=LogicGate)
+    read_enable = LogicGate(
+        pos + (-1, 0, -1), "FF0000", 1, xaxis=1, zaxis=3)
+
+    if pre_arr is None:
+        for x in range(bit_length):
+            for y in range(num_address):
+                # if pre_arr is None:
+                arr[x, y, :] = [
+                    # arr.flat[y*num_address + x] = [
+                    l3 := LogicGate(pos + (x, 1, y+1), "000000", xaxis=1, zaxis=-3),
+                    l2 := LogicGate(pos + (x, 2, y), "FF0000", 2),
+                    l1 := LogicGate(pos + (x, 3, y), "000000"),
+                    l0 := LogicGate(pos + (x, 3, y), "0000FF", 2, xaxis=1, zaxis=3),
+                ]
+                l2.connect(l1).connect(l0).connect(l0).connect(l2)
+                l0.connect(l3)
+                # else:
+                #     print(x, y, bit_length, num_address, arr.shape)
+                #     l3, l2, l1, l0 = arr[x, y, :]
+                #     # l3, l2, l1, l0 = arr.reshape(())[x, y, :]
+                #     l2.connect(l1).connect(l0).connect(l2)
+                #     l0.connect(l3)
+    else:
+        for l3, l2, l1, l0 in arr.reshape((arr.shape[0]*arr.shape[1], 4)):
+            l2.connect(l1).connect(l0).connect(l2)
+            l0.connect(l3)
+    connect(writers, arr[:, :, 2].T)
+    connect(readers, arr[:, :, 0].T)
+    # connect(inputs, arr[:, :, 1])
+    for i, a in zip(cycle(inputs), arr[:, :, 1].T.flat):
+        connect(i, a)
+    # connect(arr[:, :, 0], outputs)
+    for a, o, in zip(arr[:, :, 0].T.flat, cycle(outputs)):
+        connect(a, o)
+    for y in range(get_bits_required(num_address//address_divisor)):
+        writers_binary[y, :] = [
+            LogicGate(pos + (-2, 2, y), "FF0000", 4, xaxis=1, zaxis=3),
+            LogicGate(pos + (-3, 2, y), "FF0000", 1, xaxis=1, zaxis=3),
+        ]
+        readers_binary[y, :] = [
+            LogicGate(pos + (-2, 0, y),
+                      "FF0000", 4, xaxis=1, zaxis=3),
+            LogicGate(pos + (-3, 0, y),
+                      "FF0000", 1, xaxis=1, zaxis=3),
+        ]
+    decoder(bp, num_address, (0, 0, 0), writers_binary, writers,
+            write_enable, address_divisor=address_divisor)
+    decoder(bp, num_address, (0, 0, 0), readers_binary, readers,
+            read_enable, address_divisor=address_divisor)
+
+    if pre_arr is None:
+        bp.add(arr)
+    if pre_inputs is None:
+        bp.add(inputs)
+    if pre_outputs is None:
+        bp.add(outputs)
+    bp.add(writers, readers, writers_binary,
+           write_enable, readers_binary, read_enable)
+
+    return arr, inputs, outputs, writers_binary, writers, write_enable, readers_binary, readers, read_enable

sm_blueprint_lib/prebuilds/register.py

@@ -0,0 +1,72 @@
+from typing import Sequence
+from numpy import ndarray
+from sm_blueprint_lib import check_pos
+from sm_blueprint_lib.blueprint import Blueprint
+from sm_blueprint_lib.parts.logicgate import LogicGate
+from sm_blueprint_lib.pos import Pos
+from sm_blueprint_lib.prebuilds.counter import counter, counter_decrement
+
+
+def register(bp: Blueprint,
+             bit_length: int,
+             OE=True,
+             pos: Pos | Sequence = (0, 0, 0)):
+    pos = check_pos(pos)
+    write = LogicGate(pos + (-1, 2 if OE else 1, 0), "FF0000", 1)
+    if OE:
+        output_enable = LogicGate(pos + (-1, 0, 0), "FF0000", 1)
+        arr = ndarray((bit_length, 4), LogicGate)
+        for x in range(bit_length):
+            arr[x] = [
+                l0 := LogicGate(pos + (x, 0, 0), "000000"),
+                l1 := LogicGate(pos + (x, 1, 0), "0000FF", 2),
+                l2 := LogicGate(pos + (x, 2, 0), "000000"),
+                l3 := LogicGate(pos + (x, 3, 0), "FF0000", 2),
+            ]
+            l3.connect(l2).connect(l1).connect(l1).connect(l3)
+            l1.connect(l0)
+            write.connect(l2)
+            output_enable.connect(l0)
+        bp.add(output_enable)
+    else:
+        arr = ndarray((bit_length, 3), LogicGate)
+        for x in range(bit_length):
+            arr[x] = [
+                l0 := LogicGate(pos + (x, 0, 0), "0000FF", 2),
+                l1 := LogicGate(pos + (x, 1, 0), "000000"),
+                l2 := LogicGate(pos + (x, 2, 0), "FF0000", 2),
+            ]
+            l2.connect(l1).connect(l0).connect(l0).connect(l2)
+            write.connect(l1)
+    bp.add(arr, write)
+    if OE:
+        return arr, write, output_enable
+    else:
+        return arr, write
+
+
+def counter_register(bp: Blueprint,
+                     bit_length: int,
+                     OE=True,
+                     with_increment=True,
+                     with_decrement=True,
+                     pos: Pos | Sequence = (0, 0, 0)):
+    pos = check_pos(pos)
+    r = register(bp, bit_length, OE, pos)
+
+    if with_decrement:
+        cdec = counter_decrement(bp,
+                                 bit_length=bit_length,
+                                 pos=pos+(0, OE, 1),
+                                 precreated_swxors=r[0][:, int(OE)])
+    if with_increment:
+        cinc = counter(bp,
+                       bit_length=bit_length,
+                       pos=pos+(0, OE, 1+with_decrement),
+                       precreated_swxors=r[0][:, int(OE)])
+    if with_increment and with_decrement:
+        return r, cinc[0][:, 1], cinc[1], cdec[0][:, 1], cdec[1]
+    elif with_increment:
+        return r, cinc[0][:, 1], cinc[1]
+    else:
+        return r, cdec[0][:, 1], cdec[1]

sm_blueprint_lib/prebuilds/rom.py

@@ -0,0 +1,76 @@
+from itertools import batched, cycle
+from math import ceil
+from typing import Sequence
+from numpy import ndarray
+from sm_blueprint_lib import get_bits_required, check_pos, connect, num_to_bit_list
+from sm_blueprint_lib.blueprint import Blueprint
+from sm_blueprint_lib.parts.logicgate import LogicGate
+from sm_blueprint_lib.prebuilds.decoder import decoder
+from sm_blueprint_lib.parts.timer import Timer
+from sm_blueprint_lib.pos import Pos
+
+
+def rom(
+        bp: Blueprint,
+        page_size: tuple[int, int],
+        data: Sequence[int],
+        pos: Pos | Sequence = (0, 0, 0)):
+    pos = check_pos(pos)
+    data = list(data)
+    arr = ndarray((*page_size, 2), dtype=LogicGate)
+    page_read = ndarray(page_size[1], dtype=LogicGate)
+    page_read2 = ndarray(page_size[1], dtype=LogicGate)
+    page_read_binary = ndarray(
+        (get_bits_required(page_size[1]), 2), dtype=LogicGate)
+    data_out = ndarray(page_size[0], dtype=LogicGate)
+    page_writers_binary = ndarray(
+        (get_bits_required(len(data)/page_size[1]), 2), dtype=LogicGate)
+    page_writers = []
+    enable = LogicGate(pos + (-1, page_size[1], 0), "FF00FF", 1)
+
+    for x in range(page_size[0]):
+        for y in range(page_size[1]):
+            arr[x, y, :] = [
+                LogicGate(pos + (x, y, 0), "000000", 0),
+                LogicGate(pos + (x, y, 1), "0000FF", 1),
+            ]
+    page_read[:] = [LogicGate(pos + (-1, y, 0), "000000", 0)
+                    for y in range(page_size[1])]
+    page_read2[:] = [LogicGate(pos + (-1, y, 1), "000000", 0)
+                    for y in range(page_size[1])]
+    offset0 = (-get_bits_required(page_size[1]) -
+               get_bits_required(len(data)/page_size[1])-1)
+    for x in range(get_bits_required(page_size[1])):
+        page_read_binary[x] = (
+            LogicGate(pos + (x+offset0, page_size[1]-1, 0), "FF0000", 4),
+            LogicGate(pos + (x+offset0, page_size[1], 0), "FF0000", 1)
+        )
+    # page_read_binary[:] = [(LogicGate(pos + (x+offset0, page_size[1]-1, 0), "FF0000", 4),
+    #                         LogicGate(pos + (x+offset0, page_size[1], 0), "FF0000", 1))
+    #                        for x in range(get_bits_required(page_size[1]))]
+    data_out[:] = [LogicGate(pos + (x, page_size[1], 0), "0000FF", 1)
+                   for x in range(page_size[0])]
+
+    page_writers_binary[:] = [(LogicGate(pos + (x+offset0+get_bits_required(page_size[1]), page_size[1]-1, 0), "FF0000", 4),
+                               LogicGate(pos + (x+offset0+get_bits_required(page_size[1]), page_size[1], 0), "FF0000", 1))
+                              for x in range(get_bits_required(len(data)/page_size[1]))]
+
+    for i, data_batch in enumerate(batched(data, page_size[1])):
+        g0 = LogicGate(
+            pos + (-2-i//(page_size[1]), i % (page_size[1]) - 1, 0), "000000", 0)
+        page_writers.append(g0)
+        for j, d in enumerate(reversed(data_batch)):
+            connect(g0, arr[:, j, 1][num_to_bit_list(d, page_size[0])])
+
+    connect(arr[:, :, 1], arr[:, :, 0])
+    connect(arr[:, :, 0], data_out)
+    connect(page_read, page_read2)
+    connect(page_read2, arr[:, :, 0].T)
+    decoder(bp, page_size[1], precreated_inputs_binary=page_read_binary,
+            precreated_outputs=list(reversed(page_read)), precreated_output_enable=enable)
+    decoder(bp, ceil(len(data)/page_size[1]), precreated_inputs_binary=page_writers_binary,
+            precreated_outputs=page_writers, precreated_output_enable=enable, with_enable=False)
+
+    bp.add(arr, page_read, page_read2, page_read_binary, data_out,
+           page_writers_binary, page_writers, enable)
+    return arr, page_read, page_read_binary, data_out, page_writers_binary, page_writers, enable