siliconcompiler 0.36.3__py3-none-any.whl → 0.36.4__py3-none-any.whl

siliconcompiler/tools/icarus/cocotb_exec.py

@@ -0,0 +1,53 @@
+from siliconcompiler.tools._common.cocotb.cocotb_task import (
+    CocotbTask,
+    get_cocotb_config
+)
+
+
+class CocotbExecTask(CocotbTask):
+    '''
+    Run a cocotb testbench against a compiled Icarus Verilog simulation.
+
+    This task takes a compiled .vvp file from the icarus compile task and
+    executes it with the cocotb VPI module loaded, enabling Python-based
+    testbenches to interact with the simulation.
+
+    The task requires cocotb to be installed in the Python environment.
+    Test modules are specified by adding Python files to the fileset using
+    the "python" filetype.
+    '''
+
+    def tool(self):
+        return "icarus"
+
+    def parse_version(self, stdout):
+        # vvp version output: "Icarus Verilog runtime version 13.0 (devel) ..."
+        return stdout.split()[4]
+
+    def setup(self):
+        super().setup()
+
+        # vvp is the Icarus Verilog runtime
+        self.set_exe("vvp", vswitch="-V")
+        self.add_version(">=10.3")
+
+        self.set_threads()
+
+        # Input: compiled .vvp file from compile task
+        self.add_input_file(ext="vvp")
+
+    def runtime_options(self):
+        options = super().runtime_options()
+
+        libs_dir, lib_name, _ = get_cocotb_config("icarus")
+
+        # -M: VPI module search path
+        options.extend(["-M", str(libs_dir)])
+
+        # -m: VPI module to load
+        options.extend(["-m", lib_name])
+
+        # Input .vvp file
+        options.append(f"inputs/{self.design_topmodule}.vvp")
+
+        return options

siliconcompiler/tools/icarus/compile.py

@@ -1,4 +1,4 @@
-from typing import Optional
+from typing import Optional, Union
 from siliconcompiler import Task
 
 
@@ -15,6 +15,11 @@ class CompileTask(Task):
                            'See the corresponding "-g" flags in the Icarus manual for more "'
                            '"information.')
 
+        self.add_parameter("trace", "bool",
+                           'Enable waveform tracing. When enabled, a VCD dump module is '
+                           'auto-generated and compiled with the design to capture all signals.',
+                           defvalue=False)
+
     def set_icarus_veriloggeneration(self, gen: str,
                                      step: Optional[str] = None,
                                      index: Optional[str] = None):
@@ -28,6 +33,22 @@ class CompileTask(Task):
         """
         self.set("var", "verilog_generation", gen, step=step, index=index)
 
+    def set_trace_enabled(self, enabled: bool = True,
+                          step: Optional[str] = None,
+                          index: Optional[Union[str, int]] = None):
+        """
+        Enables or disables waveform tracing.
+
+        When enabled, a VCD dump module is auto-generated and compiled with
+        the design. The waveform file will be written to reports/<topmodule>.vcd.
+
+        Args:
+            enabled (bool): Whether to enable tracing. Defaults to True.
+            step (str, optional): The specific step to apply this configuration to.
+            index (str, optional): The specific index to apply this configuration to.
+        """
+        self.set("var", "trace", enabled, step=step, index=index)
+
     def tool(self):
         return "icarus"
 
@@ -74,6 +95,26 @@ class CompileTask(Task):
         if self.get("var", "verilog_generation"):
             self.add_required_key("var", "verilog_generation")
 
+    def pre_process(self):
+        super().pre_process()
+
+        # Generate VCD dump module if tracing is enabled
+        if self.get("var", "trace"):
+            self._generate_trace_module()
+
+    def _generate_trace_module(self):
+        trace_file = f"reports/{self.design_topmodule}.vcd"
+        dump_module = f"""// Auto-generated waveform dump module
+module sc_trace_dump();
+initial begin
+    $dumpfile("{trace_file}");
+    $dumpvars(0, {self.design_topmodule});
+end
+endmodule
+"""
+        with open("sc_trace_dump.v", "w") as f:
+            f.write(dump_module)
+
     def runtime_options(self):
         options = super().runtime_options()
 
@@ -137,4 +178,9 @@ class CompileTask(Task):
             for value in lib.get_file(fileset=fileset, filetype="verilog"):
                 options.append(value)
 
+        # Add trace dump module if tracing is enabled
+        if self.get("var", "trace"):
+            options.append("sc_trace_dump.v")
+            options.extend(["-s", "sc_trace_dump"])
+
         return options

siliconcompiler/tools/openroad/_apr.py

@@ -1438,13 +1438,26 @@ class APRTask(OpenROADTask):
                         libobj = self.project.get_library(lib)
                         self.add_required_key(libobj, "fileset", fileset, "file", "sdc")
 
+        load_tech = True
         if f"{self.design_topmodule}.odb" in self.get_files_from_input_nodes():
             self.add_input_file(ext="odb")
+            load_tech = False
         elif f"{self.design_topmodule}.def" in self.get_files_from_input_nodes():
             self.add_input_file(ext="def")
         else:
             pass
 
+        if load_tech:
+            pdk = self.project.get_library(self.project.get("asic", "pdk"))
+            for fs in pdk.get("pdk", "aprtechfileset", "openroad"):
+                if pdk.has_file(fileset=fs, filetype="lef"):
+                    self.add_required_key(pdk, "fileset", fs, "file", "lef")
+            for asiclib in self.project.get("asic", "asiclib"):
+                lib = self.project.get_library(asiclib)
+                for fs in lib.get("asic", "aprfileset"):
+                    if lib.has_file(fileset=fs, filetype="lef"):
+                        self.add_required_key(lib, "fileset", fs, "file", "lef")
+
     def _add_pnr_outputs(self):
         if self.get("var", "load_sdcs"):
             self.add_output_file(ext="sdc")

siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl

@@ -46,6 +46,13 @@ if { [sc_cfg_tool_task_get var write_cdl] } {
 # Generate SPEF
 ###############################
 
+set estimate_parasitics_args []
+if { [sc_has_routing] || [sc_has_global_routing] } {
+    lappend estimate_parasitics_args -global_routing
+} else {
+    lappend estimate_parasitics_args -placement
+}
+
 if { [sc_cfg_tool_task_get var write_spef] } {
     set pexfileset [sc_cfg_get library $sc_pdk pdk pexmodelfileset openroad]
     # just need to define a corner
@@ -75,11 +82,11 @@ if { [sc_cfg_tool_task_get var write_spef] } {
         }
     } else {
         # estimate for metrics
-        estimate_parasitics -global_routing
+        estimate_parasitics {*}$estimate_parasitics_args
     }
 } else {
     # estimate for metrics
-    estimate_parasitics -global_routing
+    estimate_parasitics {*}$estimate_parasitics_args
 }
 
 ###############################

siliconcompiler/tools/verilator/cocotb_compile.py

@@ -0,0 +1,55 @@
+import shlex
+
+from siliconcompiler.tools.verilator.compile import CompileTask
+from siliconcompiler.tools._common.cocotb.cocotb_task import (
+    get_cocotb_config
+)
+
+
+class CocotbCompileTask(CompileTask):
+
+    def task(self):
+        return "cocotb_compile"
+
+    def _setup_c_file_requirement(self):
+        pass
+
+    def runtime_options(self):
+        options = super().runtime_options()
+
+        # Cocotb-specific flags
+        options.append('--vpi')
+        options.append('--public-flat-rw')
+        options.extend(['--prefix', 'Vtop'])
+
+        # Get cocotb configuration
+        libs_dir, lib_name, share_dir = get_cocotb_config("verilator")
+
+        # Link flags for cocotb VPI library
+        # lib_name is like "libcocotbvpi_verilator.so", but -l expects "cocotbvpi_verilator"
+        # Strip "lib" prefix and ".so" suffix
+        link_name = lib_name
+
+        if link_name.startswith('lib'):
+            link_name = link_name[3:]
+
+        if link_name.endswith('.so'):
+            link_name = link_name[:-3]
+        elif link_name.endswith('.dylib'):
+            link_name = link_name[:-6]
+        else:
+            raise RuntimeError
+
+        cocotb_flags = [
+            f'-Wl,-rpath,{libs_dir}',
+            f'-L{libs_dir}',
+            f'-l{link_name}'
+        ]
+
+        options.extend(['-LDFLAGS', shlex.join(cocotb_flags)])
+
+        # Add cocotb's verilator.cpp as the simulation main
+        verilator_cpp = f'{share_dir}/lib/verilator/verilator.cpp'
+        options.append(verilator_cpp)
+
+        return options

siliconcompiler/tools/verilator/cocotb_exec.py

@@ -0,0 +1,52 @@
+from typing import Optional, Union
+
+from siliconcompiler.tools._common.cocotb.cocotb_task import CocotbTask
+from siliconcompiler.tools.execute.exec_input import ExecInputTask
+
+
+class CocotbExecTask(CocotbTask, ExecInputTask):
+
+    def __init__(self):
+        super().__init__()
+
+        self.add_parameter("trace", "bool",
+                           'Enable waveform tracing. The simulation must have been '
+                           'compiled with trace support enabled.',
+                           defvalue=False)
+
+        self.add_parameter("trace_type", "<vcd,fst>",
+                           'Specifies type of wave file to create when [trace] is set.',
+                           defvalue="vcd")
+
+    def set_cocotb_trace(
+        self,
+        enable: bool = True,
+        trace_type: str = "vcd",
+        step: Optional[str] = None,
+        index: Optional[Union[str, int]] = None
+    ):
+        self.set("var", "trace", enable, step=step, index=index)
+        self.set("var", "trace_type", trace_type, step=step, index=index)
+
+    def tool(self):
+        return "verilator"
+
+    def setup(self):
+        super().setup()
+
+        if self.get("var", "trace"):
+            self.add_required_key("var", "trace_type")
+
+    def runtime_options(self):
+        options = super().runtime_options()
+
+        # Add trace options if tracing is enabled
+        if self.get("var", "trace"):
+            options.append("--trace")
+
+            ext = self.get("var", "trace_type")
+
+            trace_file = f"reports/{self.design_topmodule}.{ext}"
+            options.extend(["--trace-file", trace_file])
+
+        return options

siliconcompiler/tools/verilator/compile.py

@@ -158,6 +158,17 @@ class CompileTask(VerilatorTask):
     def task(self):
         return "compile"
 
+    def _setup_c_file_requirement(self):
+        """Set up the C file requirement. Override in subclasses to customize."""
+        added_key = False
+        for lib, fileset in self.project.get_filesets():
+            if lib.has_file(fileset=fileset, filetype="c"):
+                self.add_required_key(lib, "fileset", fileset, "file", "c")
+                added_key = True
+        if not added_key:
+            self.add_required_key(self.project.design, "fileset",
+                                  self.project.get("option", "fileset")[0], "file", "c")
+
     def setup(self):
         super().setup()
         self.set_threads()
@@ -170,14 +181,7 @@ class CompileTask(VerilatorTask):
         self.add_required_key("var", "trace_type")
         self.add_required_key("var", "initialize_random")
 
-        added_key = False
-        for lib, fileset in self.project.get_filesets():
-            if lib.has_file(fileset=fileset, filetype="c"):
-                self.add_required_key(lib, "fileset", fileset, "file", "c")
-                added_key = True
-        if not added_key:
-            self.add_required_key(self.project.design, "fileset",
-                                  self.project.get("option", "fileset")[0], "file", "c")
+        self._setup_c_file_requirement()
 
         if self.get("var", "cincludes"):
             self.add_required_key("var", "cincludes")

siliconcompiler/tools/vpr/__init__.py

@@ -257,7 +257,7 @@ class VPRTask(Task):
         super().setup()
 
         self.set_exe("vpr", vswitch="--version")
-        self.add_version(">=v8.0.0-12677")
+        self.add_version(">=v8.0.0-15021")
 
         self.add_regex("warnings", "^Warning")
         self.add_regex("errors", "^Error")

siliconcompiler/tools/yosys/scripts/sc_synth_asic.tcl

@@ -461,7 +461,7 @@ foreach group "dontuse hold clkbuf clkgate clklogic" {
     }
 }
 
-yosys abc {*}$abc_args {*}$abc_dont_use
+yosys abc -showtmp {*}$abc_args {*}$abc_dont_use
 
 ########################################################
 # Cleanup

siliconcompiler/tools/yosys/syn_asic.py

@@ -241,9 +241,9 @@ class ASICSynthesis(_ASICTask, YosysTask):
         self.add_parameter(
             "synth_extra_map",
             "[file]",
-            "Files used in synthesis to perform additional techmapping",
-            "techmaps/lcu_kogge_stone.v",
-            dataroot="yosys-techmaps")
+            "Files used in synthesis to perform additional techmapping")
+        # "techmaps/lcu_kogge_stone.v",
+        # dataroot="yosys-techmaps")
 
     def __init_hierarchy_parameter(self):
         self.add_parameter(

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "11bd3ead9d12211b72706ac7c8653234cc136b8b",
+    "git-commit": "49a31384924a2c400ce27da80e270917ffddc2bb",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "dda887bc6e5160fd7c15489cc5845eaff72b5252",
+    "git-commit": "0c6c3d3d35ca2c1a103702652ddb9ddba54347a8",
     "auto-update": true
   },
   "netgen": {
@@ -76,7 +76,7 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "7f476dbf780b845d07a7642366552e799df02c93",
+    "git-commit": "fe77ace273b3f0558763e0e91d409b2d13344eff",
     "auto-update": false
   },
   "icepack": {
@@ -171,4 +171,4 @@
     "git-commit": "d647673f3b3960256069a79e8d92d36a3b89d9a4",
     "auto-update": false
   }
-}
+}

siliconcompiler/toolscripts/rhel8/install-icarus.sh

@@ -27,7 +27,7 @@ wget http://ftp.gnu.org/pub/gnu/gperf/gperf-3.1.tar.gz
 tar xvf gperf-3.1.tar.gz
 cd gperf-3.1
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 cd ..
 
@@ -42,7 +42,7 @@ git checkout $(python3 ${src_path}/_tools.py --tool icarus --field git-commit)
 
 sh autoconf.sh
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 
 cd -

siliconcompiler/toolscripts/rhel8/install-magic.sh

@@ -28,5 +28,5 @@ if [ ! -z ${PREFIX} ]; then
 fi
 
 LD_FLAGS=-shared ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install

siliconcompiler/toolscripts/rhel8/install-netgen.sh

@@ -28,5 +28,5 @@ if [ ! -z ${PREFIX} ]; then
 fi
 
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install

siliconcompiler/toolscripts/rhel8/install-surelog.sh

@@ -26,7 +26,7 @@ cd surelog
 git checkout $(python3 ${src_path}/_tools.py --tool surelog --field git-commit)
 git submodule update --init --recursive
 
-scl run gcc-toolset-12 "LDFLAGS=\"-lrt\" make -j$(nproc)"
+scl run gcc-toolset-12 "LDFLAGS=\"-lrt\" make -j${NPROC:-$(nproc)}"
 
 USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
 if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then

siliconcompiler/toolscripts/rhel8/install-sv2v.sh

@@ -31,7 +31,7 @@ git clone $(python3 ${src_path}/_tools.py --tool sv2v --field git-url) sv2v
 cd sv2v
 git checkout $(python3 ${src_path}/_tools.py --tool sv2v --field git-commit)
 
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 
 if [ ! -z ${PREFIX} ]; then
     $SUDO_INSTALL mkdir -p ${PREFIX}/bin/

siliconcompiler/toolscripts/rhel8/install-verilator.sh

@@ -28,7 +28,7 @@ tar xvf help2man-1.43.3.tar.gz
 cd help2man-1.43.3
 
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 
 cd ..
@@ -42,7 +42,7 @@ git checkout $(python3 ${src_path}/_tools.py --tool verilator --field git-commit
 autoconf
 
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 
 cd -

siliconcompiler/toolscripts/rhel8/install-xyce.sh

@@ -51,7 +51,7 @@ cmake \
     -D TPL_AMD_INCLUDE_DIRS="/usr/include/suitesparse" \
     -C "../cmake/trilinos/trilinos-base.cmake" \
     ..
-cmake --build . -j$(nproc)
+cmake --build . -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 cd ../..
 
@@ -64,7 +64,7 @@ cmake \
     -D Trilinos_ROOT=$PREFIX/trilinos \
     -D BUILD_SHARED_LIBS=ON \
     ..
-cmake --build . -j$(nproc)
-cmake --build . -j$(nproc) --target xycecinterface
+cmake --build . -j${NPROC:-$(nproc)}
+cmake --build . -j${NPROC:-$(nproc)} --target xycecinterface
 $SUDO_INSTALL make install
 cd -

siliconcompiler/toolscripts/rhel9/install-ghdl.sh

@@ -28,6 +28,6 @@ if [ ! -z ${PREFIX} ]; then
 fi
 
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 cd -

siliconcompiler/toolscripts/rhel9/install-gtkwave.sh

@@ -32,7 +32,7 @@ wget http://ftp.gnu.org/pub/gnu/gperf/gperf-3.1.tar.gz
 tar xvf gperf-3.1.tar.gz
 cd gperf-3.1
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 cd ..
 
@@ -44,5 +44,5 @@ cd gtkwave3-gtk3
 
 ./autogen.sh
 LDFLAGS="-ltcl -ltk" ./configure --enable-gtk3 $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install

siliconcompiler/toolscripts/rhel9/install-icarus.sh

@@ -27,7 +27,7 @@ wget http://ftp.gnu.org/pub/gnu/gperf/gperf-3.1.tar.gz
 tar xvf gperf-3.1.tar.gz
 cd gperf-3.1
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 cd ..
 
@@ -42,7 +42,7 @@ git checkout $(python3 ${src_path}/_tools.py --tool icarus --field git-commit)
 
 sh autoconf.sh
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 
 cd -

siliconcompiler/toolscripts/rhel9/install-magic.sh

@@ -28,5 +28,5 @@ if [ ! -z ${PREFIX} ]; then
 fi
 
 LD_FLAGS=-shared ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install

siliconcompiler/toolscripts/rhel9/install-netgen.sh

@@ -28,5 +28,5 @@ if [ ! -z ${PREFIX} ]; then
 fi
 
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install

siliconcompiler/toolscripts/rhel9/install-openroad.sh

@@ -37,7 +37,7 @@ if [ ! -z ${PREFIX} ]; then
     cmake_args="$cmake_args -DCMAKE_INSTALL_PREFIX=$PREFIX"
 fi
 
-./etc/Build.sh -cmake="$cmake_args"
+./etc/Build.sh -cmake="$cmake_args" -threads=${NPROC:-$(nproc)}
 
 cd build
 $SUDO_INSTALL make install

siliconcompiler/toolscripts/rhel9/install-opensta.sh

@@ -40,7 +40,7 @@ cd eigen
 mkdir build
 cd build
 cmake $cmake_args ..
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 
 cd ../../..
@@ -51,7 +51,7 @@ git clone --depth=1 -b 3.0.0 https://github.com/The-OpenROAD-Project/cudd.git
 cd cudd
 autoreconf
 ./configure $config_prefix
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 
 cd ../..
@@ -65,8 +65,8 @@ wget https://github.com/PCRE2Project/pcre2/releases/download/pcre2-10.42/pcre2-1
 
 ./autogen.sh
 ./configure $config_prefix
-make -j$(nproc)
-$SUDO_INSTALL make -j$(nproc) install
+make -j${NPROC:-$(nproc)}
+$SUDO_INSTALL make -j${NPROC:-$(nproc)} install
 
 cd ../..
 # opensta
@@ -78,7 +78,7 @@ git submodule update --init --recursive
 mkdir -p build
 cd build
 cmake .. $cmake_args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 
 cd -

siliconcompiler/toolscripts/rhel9/install-surelog.sh

@@ -25,7 +25,7 @@ cd surelog
 git checkout $(python3 ${src_path}/_tools.py --tool surelog --field git-commit)
 git submodule update --init --recursive
 
-scl run gcc-toolset-12 "LDFLAGS=\"-lrt\" make -j$(nproc)"
+scl run gcc-toolset-12 "LDFLAGS=\"-lrt\" make -j${NPROC:-$(nproc)}"
 
 USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
 if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then

siliconcompiler/toolscripts/rhel9/install-sv2v.sh

@@ -31,7 +31,7 @@ git clone $(python3 ${src_path}/_tools.py --tool sv2v --field git-url) sv2v
 cd sv2v
 git checkout $(python3 ${src_path}/_tools.py --tool sv2v --field git-commit)
 
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 
 if [ ! -z ${PREFIX} ]; then
     $SUDO_INSTALL mkdir -p ${PREFIX}/bin/

siliconcompiler/toolscripts/rhel9/install-verilator.sh

@@ -28,7 +28,7 @@ tar xvf help2man-1.43.3.tar.gz
 cd help2man-1.43.3
 
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 
 cd ..
@@ -42,7 +42,7 @@ git checkout $(python3 ${src_path}/_tools.py --tool verilator --field git-commit
 autoconf
 
 ./configure $args
-make -j$(nproc)
+make -j${NPROC:-$(nproc)}
 $SUDO_INSTALL make install
 
 cd -

siliconcompiler/toolscripts/rhel9/install-vpr.sh

@@ -31,6 +31,6 @@ if [ ! -z ${PREFIX} ]; then
     args="-DCMAKE_INSTALL_PREFIX=$PREFIX"
 fi
 
-make CMAKE_PARAMS="$args -DWITH_PARMYS=OFF -DWITH_ABC=OFF -DSLANG_SYSTEMVERILOG=OFF" -j$(nproc)
+make CMAKE_PARAMS="$args -DWITH_PARMYS=OFF -DWITH_ABC=OFF -DSLANG_SYSTEMVERILOG=OFF" -j${NPROC:-$(nproc)}
 cd build
 $SUDO_INSTALL make install

siliconcompiler/toolscripts/rhel9/install-wildebeest.sh

@@ -19,7 +19,7 @@ cd wildebeest
 git checkout $(python3 ${src_path}/_tools.py --tool wildebeest --field git-commit)
 
 cmake -S . -B build
-cmake --build build
+cmake --build build -j${NPROC:-$(nproc)}
 
 USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
 if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then