siliconcompiler 0.36.1__py3-none-any.whl → 0.36.3__py3-none-any.whl

siliconcompiler/tools/klayout/scripts/klayout_merge.py

@@ -0,0 +1,79 @@
+import pya
+import sys
+
+import os.path
+
+
+if __name__ == "__main__":
+    # SC_ROOT provided by CLI
+    sys.path.append(SC_KLAYOUT_ROOT)  # noqa: F821
+    sys.path.append(SC_TOOLS_ROOT)  # noqa: F821
+    sys.path.append(SC_ROOT)  # noqa: F821
+
+    from klayout_utils import (
+        technology,
+        get_schema,
+        generate_metrics
+    )
+
+    from klayout_operations import (
+        read_layout,
+        write_stream
+    )
+
+    schema = get_schema(manifest='sc_manifest.json')
+
+    # Extract info from manifest
+    sc_step = schema.get('arg', 'step')
+    sc_index = schema.get('arg', 'index')
+    sc_tool = 'klayout'
+    sc_task = 'merge'
+
+    design_name = schema.get('option', 'design')
+    fileset = schema.get("option", "fileset")[0]
+    design = schema.get("library", design_name, "fileset", fileset, "topmodule")
+
+    ref_type, ref_source0, ref_source1 = schema.get("tool", sc_tool, "task", sc_task,
+                                                    "var", "reference",
+                                                    step=sc_step, index=sc_index)
+    if ref_type == 'input':
+        step, index = ref_source0, ref_source1
+        input_file = os.path.join('inputs', f"{design}.{ref_source0}{ref_source1}.gds")
+    else:
+        input_file = schema.get("library", ref_source0, "fileset", ref_source1, "file", "gds")[0]
+
+    merge_files = []
+    for merge_type, merge_source0, merge_source1, prefix in \
+            schema.get("tool", sc_tool, "task", sc_task, "var", "merge",
+                       step=sc_step, index=sc_index):
+        if merge_type == 'input':
+            merge_file = os.path.join('inputs', f"{design}.{merge_source0}{merge_source1}.gds")
+        else:
+            merge_file = schema.get("library", merge_source0, "fileset", merge_source1,
+                                    "file", "gds")[0]
+        merge_files.append((prefix, merge_file))
+
+    tech = technology(design, schema)
+    base_layout = read_layout(input_file)
+    top_cell = base_layout.top_cell()
+    base_layout.technology_name = tech.name
+
+    for prefix, merge_file in merge_files:
+        print(f"[INFO] Merging file '{merge_file}' with prefix '{prefix}'")
+        merge_layout = read_layout(merge_file)
+
+        merge_top = merge_layout.top_cell()
+
+        new_cell_name = f"{prefix}{merge_top.name}"
+        if base_layout.cell(new_cell_name):
+            print(f"[WARN] Cell '{new_cell_name}' already exists in base layout. Skipping.")
+            continue
+        print(f"[INFO] Adding cell '{merge_top.name}' as '{new_cell_name}'")
+        new_cell = base_layout.create_cell(new_cell_name)
+        new_cell.copy_tree(merge_top)
+        cell_inst = pya.CellInstArray(new_cell.cell_index(), pya.Trans())
+        top_cell.insert(cell_inst)
+
+    write_stream(base_layout, f"outputs/{design}.gds", True)
+
+    generate_metrics()

siliconcompiler/tools/openroad/_apr.py

@@ -1218,6 +1218,10 @@ class APRTask(OpenROADTask):
                            "used to indicate if global routing information should be loaded",
                            defvalue=False)
 
+        self.add_parameter("load_sdcs", "bool",
+                           "used to indicate if SDC files should be loaded before APR",
+                           defvalue=True)
+
         self.add_parameter("global_connect_fileset", "[(str,str)]",
                            "list of libraries and filesets to generate connects from")
 
@@ -1264,6 +1268,18 @@ class APRTask(OpenROADTask):
         """
         self.set("var", "ord_heatmap_bins", (x, y), step=step, index=index)
 
+    def set_openroad_loadsdcs(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None) -> None:
+        """
+        Enables or disables loading SDC files before APR.
+
+        Args:
+            enable: True to load SDC files, False to disable.
+            step: The specific step to apply this configuration to.
+            index: The specific index to apply this configuration to.
+        """
+        self.set("var", "load_sdcs", enable, step=step, index=index)
+
     def set_openroad_powercorner(self, corner: str,
                                  step: Optional[str] = None, index: Optional[str] = None) -> None:
         """
@@ -1334,6 +1350,7 @@ class APRTask(OpenROADTask):
         self.add_required_key("var", "ord_enable_images")
         self.add_required_key("var", "ord_heatmap_bins")
         self.add_required_key("var", "load_grt_setup")
+        self.add_required_key("var", "load_sdcs")
 
         if not self.get("var", "global_connect_fileset"):
             self.__import_globalconnect_filesets()
@@ -1346,9 +1363,20 @@ class APRTask(OpenROADTask):
         libcorners = set()
         for scenario in self.project.constraint.timing.get_scenario().values():
             libcorners.update(scenario.get_libcorner(self.step, self.index))
+            self.add_required_key(scenario, "pexcorner")
+            self.add_required_key(scenario, "libcorner")
+            if scenario.get_check(self.step, self.index):
+                self.add_required_key(scenario, "check")
+            mode = scenario.get_mode(self.step, self.index)
+            if mode:
+                self.add_required_key(scenario, "mode")
+                if self.get("var", "load_sdcs"):
+                    mode_obj = self.project.constraint.timing.get_mode(mode)
+                    self.add_required_key(mode_obj, "sdcfileset")
+
         delay_model = self.project.get("asic", "delaymodel")
         for asiclib in self.project.get("asic", "asiclib"):
-            lib = self.project.get("library", asiclib, field="schema")
+            lib = self.project.get_library(asiclib)
             for corner in libcorners:
                 if not lib.valid("asic", "libcornerfileset", corner, delay_model):
                     continue
@@ -1362,24 +1390,53 @@ class APRTask(OpenROADTask):
 
     def __import_globalconnect_filesets(self):
         for lib in self.project.get("asic", "asiclib"):
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             if libobj.valid("tool", "openroad", "global_connect_fileset"):
                 for fileset in libobj.get("tool", "openroad", "global_connect_fileset"):
                     self.add_openroad_globalconnectfileset(lib, fileset)
 
     def _set_reports(self, task_reports: List[str]):
-        self.set("var", "reports", set(task_reports).difference(self.get("var", "skip_reports")))
+        skip_reports = set(self.get("var", "skip_reports"))
+
+        if not self.get("var", "load_sdcs"):
+            skip_reports.update((
+                "setup",
+                "hold",
+                "unconstrained",
+                "clock_skew",
+                "fmax",
+                "check_setup",
+                "clock_placement",
+                "clock_trees"))
+
+        self.set("var", "reports", set(task_reports).difference(skip_reports))
 
         if "power" in self.get("var", "reports"):
             self.add_required_key("var", "power_corner")
 
     def _add_pnr_inputs(self):
-        if f"{self.design_topmodule}.sdc" in self.get_files_from_input_nodes():
-            self.add_input_file(ext="sdc")
-        else:
-            for lib, fileset in self.project.get_filesets():
-                if lib.has_file(fileset=fileset, filetype="sdc"):
-                    self.add_required_key(lib, "fileset", fileset, "file", "sdc")
+        if self.get("var", "load_sdcs"):
+            if f"{self.design_topmodule}.sdc" in self.get_files_from_input_nodes():
+                self.add_input_file(ext="sdc")
+            else:
+                for lib, fileset in self.project.get_filesets():
+                    if lib.has_file(fileset=fileset, filetype="sdc"):
+                        self.add_required_key(lib, "fileset", fileset, "file", "sdc")
+
+                modes = set()
+                for scenario in self.project.constraint.timing.get_scenario().values():
+                    mode = scenario.get_mode(self.step, self.index)
+                    if mode:
+                        modes.add(mode)
+                        self.add_required_key(scenario, "mode")
+                        mode_obj = self.project.constraint.timing.get_mode(mode)
+                        self.add_required_key(mode_obj, "sdcfileset")
+
+                for mode in modes:
+                    mode_obj = self.project.constraint.timing.get_mode(mode)
+                    for lib, fileset in mode_obj.get_sdcfileset():
+                        libobj = self.project.get_library(lib)
+                        self.add_required_key(libobj, "fileset", fileset, "file", "sdc")
 
         if f"{self.design_topmodule}.odb" in self.get_files_from_input_nodes():
             self.add_input_file(ext="odb")
@@ -1389,14 +1446,15 @@ class APRTask(OpenROADTask):
             pass
 
     def _add_pnr_outputs(self):
-        self.add_output_file(ext="sdc")
+        if self.get("var", "load_sdcs"):
+            self.add_output_file(ext="sdc")
         self.add_output_file(ext="vg")
         self.add_output_file(ext="lec.vg")
         self.add_output_file(ext="def")
         self.add_output_file(ext="odb")
 
         for lib in self.project.get("asic", "asiclib"):
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             for celltype in ["decap", "tie", "filler", "tap", "endcap", "antenna", "physicalonly"]:
                 if libobj.valid("asic", "cells", celltype) and \
                         libobj.get("asic", "cells", celltype):

siliconcompiler/tools/openroad/power_grid.py

@@ -94,7 +94,7 @@ class PowerGridTask(APRTask, OpenROADSTAParameter, OpenROADPSMParameter):
 
     def __import_pdn_filesets(self):
         for lib in self.project.get("asic", "asiclib"):
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             if libobj.valid("tool", "openroad", "power_grid_fileset"):
                 for fileset in libobj.get("tool", "openroad", "power_grid_fileset"):
                     self.add_openroad_powergridfileset(lib, fileset)

siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl

@@ -2,22 +2,24 @@
 # Read timing constraints
 ###############################
 
-if { [file exists "inputs/${sc_topmodule}.sdc"] } {
-    set sdc "inputs/${sc_topmodule}.sdc"
-    puts "Reading SDC: ${sdc}"
-    read_sdc $sdc
-} else {
-    set sdcs [sc_cfg_get_fileset $sc_designlib [sc_cfg_get option fileset] sdc]
-    if { [llength $sdcs] > 0 } {
-        foreach sdc $sdcs {
+if { [sc_cfg_tool_task_get var load_sdcs] } {
+    if { [file exists "inputs/${sc_topmodule}.sdc"] } {
+        set sdc "inputs/${sc_topmodule}.sdc"
+        puts "Reading SDC: ${sdc}"
+        read_sdc $sdc
+    } else {
+        set sdcs [sc_cfg_get_fileset $sc_designlib [sc_cfg_get option fileset] sdc]
+        if { [llength $sdcs] > 0 } {
+            foreach sdc $sdcs {
+                puts "Reading SDC: ${sdc}"
+                read_sdc $sdc
+            }
+        } else {
+            # fall back on default auto generated constraints file
+            set sdc [sc_cfg_tool_task_get var opensta_generic_sdc]
             puts "Reading SDC: ${sdc}"
-            read_sdc $sdc
+            utl::warn FLW 1 "Defaulting back to default SDC"
+            read_sdc "${sdc}"
         }
-    } else {
-        # fall back on default auto generated constraints file
-        set sdc [sc_cfg_tool_task_get var opensta_generic_sdc]
-        puts "Reading SDC: ${sdc}"
-        utl::warn FLW 1 "Defaulting back to default SDC"
-        read_sdc "${sdc}"
     }
 }

siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl

@@ -1 +1,3 @@
-write_sdc "outputs/${sc_topmodule}.sdc"
+if { [sc_cfg_tool_task_get var load_sdcs] } {
+    write_sdc "outputs/${sc_topmodule}.sdc"
+}

siliconcompiler/tools/vpr/__init__.py

@@ -273,7 +273,7 @@ class VPRTask(Task):
                 self.add_required_key(lib, "fileset", fileset, "file", "sdc")
                 self.set("var", "enable_timing_analysis", True)
 
-        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
         self.add_required_key(fpga, "tool", "vpr", "devicecode")
         self.add_required_key(fpga, "tool", "vpr", "clock_model")
         self.add_required_key(fpga, "tool", "vpr", "archfile")
@@ -287,7 +287,7 @@ class VPRTask(Task):
     def runtime_options(self):
         options = super().runtime_options()
 
-        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         options.extend(["--device", fpga.get("tool", "vpr", "devicecode")])
 
@@ -393,17 +393,17 @@ class VPRTask(Task):
         for report in glob.glob("*.rpt"):
             shutil.move(report, 'reports')
 
-        fpga = self.project.get("fpga", "device")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         dff_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "registers"):
-            dff_cells = self.project.get("library", fpga, "tool", "yosys", "registers")
+        if fpga.valid("tool", "yosys", "registers"):
+            dff_cells = fpga.get("tool", "yosys", "registers")
         brams_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "brams"):
-            brams_cells = self.project.get("library", fpga, "tool", "yosys", "brams")
+        if fpga.valid("tool", "yosys", "brams"):
+            brams_cells = fpga.get("tool", "yosys", "brams")
         dsps_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "dsps"):
-            dsps_cells = self.project.get("library", fpga, "tool", "yosys", "dsps")
+        if fpga.valid("tool", "yosys", "dsps"):
+            dsps_cells = fpga.get("tool", "yosys", "dsps")
 
         stat_extract = re.compile(r'  \s*(.*)\s*:\s*([0-9]+)')
         lut_match = re.compile(r'([0-9]+)-LUT')

siliconcompiler/tools/vpr/place.py

@@ -48,8 +48,7 @@ class PlaceTask(VPRTask):
             if files:
                 pcf_file = files[0]
 
-                fpga = self.project.get("library", self.project.get("fpga", "device"),
-                                        field="schema")
+                fpga = self.project.get_library(self.project.get("fpga", "device"))
                 map_file = fpga.find_files("tool", "vpr", "constraintsmap")
 
                 constraints_map = load_constraints_map(map_file)

siliconcompiler/tools/yosys/syn_asic.py

@@ -39,7 +39,7 @@ class _ASICTask(ASICTask, YosysTask):
 
         delaymodel = self.project.get("asic", "delaymodel")
         for lib in self.project.get("asic", "asiclib"):
-            lib_obj = self.project.get("library", lib, field="schema")
+            lib_obj = self.project.get_library(lib)
             for corner in self.get("var", "synthesis_corner"):
                 if lib_obj.get("asic", "libcornerfileset", corner, delaymodel):
                     self.add_required_key(lib_obj, "asic", "libcornerfileset", corner, delaymodel)
@@ -81,7 +81,7 @@ class _ASICTask(ASICTask, YosysTask):
         # Generate synthesis_libraries for Yosys use
         fileset_map = []
         for lib in self.project.get("asic", "asiclib"):
-            lib_obj = self.project.get("library", lib, field="schema")
+            lib_obj = self.project.get_library(lib)
             for corner in self.get("var", "synthesis_corner"):
                 for fileset in lib_obj.get("asic", "libcornerfileset", corner, delaymodel):
                     fileset_map.append((lib_obj, fileset))
@@ -696,7 +696,7 @@ class ASICSynthesis(_ASICTask, YosysTask):
         self.add_output_file(ext="vg", clobber=True)
         self.add_output_file(ext="netlist.json")
 
-        mainlib = self.project.get("library", self.project.get("asic", "mainlib"), field="schema")
+        mainlib = self.project.get_library(self.project.get("asic", "mainlib"))
 
         if self.get('var', 'abc_constraint_driver') is not None:
             self.add_required_key("var", "abc_constraint_driver")
@@ -799,7 +799,7 @@ class ASICSynthesis(_ASICTask, YosysTask):
 
     def _get_clock_period(self):
         mainlib = self.project.get("asic", "mainlib")
-        clock_units_multiplier = self.project.get("library", mainlib, field="schema").get(
+        clock_units_multiplier = self.project.get_library(mainlib).get(
             "tool", "yosys", "abc_clock_multiplier") / 1000
 
         _, period = self.get_clock()

siliconcompiler/tools/yosys/syn_fpga.py

@@ -98,7 +98,7 @@ class FPGASynthesis(YosysTask):
 
         self._synthesis_post_process()
 
-        fpga = self.project.get("fpga", "device")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         with sc_open("reports/stat.json") as f:
             metrics = json.load(f)
@@ -113,15 +113,14 @@ class FPGASynthesis(YosysTask):
                 return
 
             dff_cells = []
-            if self.project.valid("library", fpga, "tool", "yosys", "registers"):
-                dff_cells = self.project.get("library", fpga, "tool", "yosys", "registers")
+            if fpga.valid("tool", "yosys", "registers"):
+                dff_cells = fpga.get("tool", "yosys", "registers")
             brams_cells = []
-            if self.project.valid("library", fpga, "tool", "yosys", "brams"):
-                brams_cells = self.project.get("library", fpga, "tool", "yosys", "brams")
+            if fpga.valid("tool", "yosys", "brams"):
+                brams_cells = fpga.get("tool", "yosys", "brams")
             dsps_cells = []
-            if self.project.valid("library", fpga, "tool", "yosys", "dsps"):
-                dsps_cells = self.project.get("library", fpga, "tool", "yosys", "dsps")
-
+            if fpga.valid("tool", "yosys", "dsps"):
+                dsps_cells = fpga.get("tool", "yosys", "dsps")
             data = {
                 "registers": 0,
                 "luts": 0,

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "0004adbadb9b28cbc00b87c0b2a089164e439441",
+    "git-commit": "11bd3ead9d12211b72706ac7c8653234cc136b8b",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "128ea3cf283ba2ac0af699543c8e037cc9bfc0a5",
+    "git-commit": "dda887bc6e5160fd7c15489cc5845eaff72b5252",
     "auto-update": true
   },
   "netgen": {
@@ -101,7 +101,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.60",
+    "git-commit": "v0.61",
     "version-prefix": "",
     "auto-update": true
   },
@@ -145,7 +145,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "64b44616a3798f07453b14ea03e4ac8a16b77313",
+    "git-commit": "4e1ad7c11e23cffe131aa5c478083f1d99f0c0be",
     "docker-depends": "yosys",
     "auto-update": true
   },
@@ -168,7 +168,7 @@
   },
   "keplerformal": {
     "git-url": "https://github.com/keplertech/kepler-formal.git",
-    "git-commit": "c1edd4a196536385255f4c882e4001d534d4638b",
+    "git-commit": "d647673f3b3960256069a79e8d92d36a3b89d9a4",
     "auto-update": false
   }
-}
+}

siliconcompiler/utils/logging.py

@@ -145,3 +145,9 @@ def get_console_formatter(project, in_run, step, index):
     if support_color:
         return SCColorLoggerFormatter(base_format)
     return base_format
+
+
+def get_stream_handler(project, in_run, step, index):
+    handler = logging.StreamHandler(stream=sys.stdout)
+    handler.setFormatter(get_console_formatter(project, in_run, step, index))
+    return handler

{siliconcompiler-0.36.1.dist-info → siliconcompiler-0.36.3.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: siliconcompiler
-Version: 0.36.1
+Version: 0.36.3
 Summary: A compiler framework that automates translation from source code to silicon.
 Author: Zero ASIC
 License: Apache License 2.0
@@ -38,12 +38,12 @@ Requires-Dist: PyYAML<7.0.0,>=6.0.0
 Requires-Dist: GitPython<3.2,>=3.1.44
 Requires-Dist: PyGithub<2.9.0,>=2.8.0
 Requires-Dist: urllib3>=1.26.0
-Requires-Dist: lambdapdk>=0.2.6
+Requires-Dist: lambdapdk>=0.2.7
 Requires-Dist: fasteners>=0.20
 Requires-Dist: pandas>=1.1.5
 Requires-Dist: psutil>=5.8.0
 Requires-Dist: Jinja2>=2.11.3
-Requires-Dist: pyslang==9.1.0
+Requires-Dist: pyslang==10.0.0
 Requires-Dist: importlib_metadata; python_version < "3.10"
 Requires-Dist: streamlit==1.46.1; python_full_version != "3.9.7"
 Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"