siliconcompiler 0.36.1__py3-none-any.whl → 0.36.2__py3-none-any.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.36.1'
+version = '0.36.2'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/asic.py

@@ -244,7 +244,7 @@ class ASIC(Project):
             if pdk not in self.getkeys("library"):
                 error = True
                 self.logger.error(f"{pdk} library has not been loaded")
-            elif not isinstance(self.get("library", pdk, field="schema"), PDK):
+            elif not isinstance(self.get_library(pdk), PDK):
                 error = True
                 self.logger.error(f"{pdk} must be a PDK")
 
@@ -432,7 +432,7 @@ class ASIC(Project):
         if not self.get("asic", "pdk") and self.get("asic", "mainlib"):
             mainlib = None
             if self._has_library(self.get("asic", "mainlib")):
-                mainlib = self.get("library", self.get("asic", "mainlib"), field="schema")
+                mainlib = self.get_library(self.get("asic", "mainlib"))
             if mainlib:
                 mainlib_pdk = mainlib.get("asic", "pdk")
                 if mainlib_pdk:
@@ -530,7 +530,7 @@ class ASICTask(Task):
             raise ValueError("mainlib has not been defined in [asic,mainlib]")
         if mainlib not in self.project.getkeys("library"):
             raise LookupError(f"{mainlib} has not been loaded")
-        return self.project.get("library", mainlib, field="schema")
+        return self.project.get_library(mainlib)
 
     @property
     def pdk(self) -> PDK:
@@ -540,7 +540,7 @@ class ASICTask(Task):
             raise ValueError("pdk has not been defined in [asic,pdk]")
         if pdk not in self.project.getkeys("library"):
             raise LookupError(f"{pdk} has not been loaded")
-        return self.project.get("library", pdk, field="schema")
+        return self.project.get_library(pdk)
 
     def set_asic_var(self,
                      key: str,

siliconcompiler/design.py

@@ -694,7 +694,12 @@ class Design(DependencySchema, LibrarySchema):
         if dataroot is ...:
             dataroot = None
         else:
-            dataroot = self._get_active_dataroot(dataroot)
+            if option in ['idir', 'libdir']:
+                try:
+                    dataroot = self._get_active_dataroot(dataroot)
+                except ValueError as e:
+                    if any(not os.path.isabs(v) for v in value):
+                        raise e
 
         with self.active_dataroot(dataroot):
             if list in typelist and not clobber:

siliconcompiler/package/__init__.py

@@ -72,9 +72,10 @@ class Resolver:
         self.__cacheid = None
 
         if self.__root and hasattr(self.__root, "logger"):
-            self.__logger = self.__root.logger.getChild(f"resolver-{self.name}")
+            rootlogger = self.__root.logger
         else:
-            self.__logger = logging.getLogger(f"resolver-{self.name}")
+            rootlogger = MPManager.logger()
+        self.__logger = rootlogger.getChild(f"resolver-{self.name}")
 
     @staticmethod
     def populate_resolvers() -> None:

siliconcompiler/project.py

@@ -1,6 +1,5 @@
 import logging
 import os
-import sys
 import uuid
 
 import os.path
@@ -28,7 +27,7 @@ from siliconcompiler.schema_support.pathschema import PathSchemaBase
 
 from siliconcompiler.report.dashboard.cli import CliDashboard
 from siliconcompiler.scheduler import Scheduler, SCRuntimeError
-from siliconcompiler.utils.logging import SCColorLoggerFormatter, SCLoggerFormatter
+from siliconcompiler.utils.logging import get_stream_handler
 from siliconcompiler.utils import get_file_ext
 from siliconcompiler.utils.multiprocessing import MPManager
 from siliconcompiler.utils.paths import jobdir, workdir
@@ -143,12 +142,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
         self.__logger = MPManager.logger().getChild(f"project_{uuid.uuid4().hex}")
         self.__logger.setLevel(logging.INFO)
 
-        self._logger_console = logging.StreamHandler(stream=sys.stdout)
-        if SCColorLoggerFormatter.supports_color(sys.stdout):
-            self._logger_console.setFormatter(SCColorLoggerFormatter(SCLoggerFormatter()))
-        else:
-            self._logger_console.setFormatter(SCLoggerFormatter())
-
+        self._logger_console = get_stream_handler(self, in_run=False, step=None, index=None)
         self.__logger.addHandler(self._logger_console)
 
     def __init_dashboard(self):
@@ -225,7 +219,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
         if not self.valid("library", design_name):
             raise KeyError(f"{design_name} design has not been loaded")
 
-        return self.get("library", design_name, field="schema")
+        return self.get_library(design_name)
 
     @property
     def option(self) -> OptionSchema:
@@ -482,7 +476,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
             if not self._has_library(src_lib):
                 continue
 
-            if not self.get("library", src_lib, field="schema").has_fileset(src_fileset):
+            if not self.get_library(src_lib).has_fileset(src_fileset):
                 self.logger.error(f"{src_fileset} is not a valid fileset in {src_lib}")
                 error = True
                 continue
@@ -496,7 +490,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
                 continue
 
             if dst_fileset and \
-                    not self.get("library", dst_lib, field="schema").has_fileset(dst_fileset):
+                    not self.get_library(dst_lib).has_fileset(dst_fileset):
                 self.logger.error(f"{dst_fileset} is not a valid fileset in {dst_lib}")
                 error = True
                 continue
@@ -715,7 +709,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
             if dst_lib:
                 if not self._has_library(dst_lib):
                     raise KeyError(f"{dst_lib} is not a loaded library")
-                dst_obj = self.get("library", dst_lib, field="schema")
+                dst_obj = self.get_library(dst_lib)
             else:
                 dst_obj = None
             if not dst_fileset:
@@ -844,7 +838,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
 
         if isinstance(src_dep, str):
             if self._has_library(src_dep):
-                src_dep = self.get("library", src_dep, field="schema")
+                src_dep = self.get_library(src_dep)
             else:
                 src_dep_name = src_dep
                 src_dep = None
@@ -875,7 +869,7 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
                 if not self._has_library(alias_dep):
                     raise KeyError(f"{alias_dep} has not been loaded")
 
-                alias_dep = self.get("library", alias_dep, field="schema")
+                alias_dep = self.get_library(alias_dep)
 
         if alias_dep is not None:
             if isinstance(alias_dep, Design):
@@ -894,6 +888,28 @@ class Project(PathSchemaBase, CommandLineSchema, BaseSchema):
         else:
             return self.add("option", "alias", alias)
 
+    def get_library(self, library: str) -> NamedSchema:
+        """
+        Retrieves a library by name from the project.
+
+        Args:
+            library (str): The name of the library to retrieve.
+
+        Returns:
+            NamedSchema: The `NamedSchema` object representing the library.
+
+        Raises:
+            KeyError: If the specified library is not found in the project.
+            TypeError: If the provided `library` is not a string.
+        """
+        if not isinstance(library, str):
+            raise TypeError("library must be a string")
+
+        if not self._has_library(library):
+            raise KeyError(f"{library} is not a valid library")
+
+        return self.get("library", library, field="schema")
+
     def _has_library(self, library: Union[str, NamedSchema]) -> bool:
         """
         Checks if a library with the given name exists and is loaded in the project.

siliconcompiler/schema_support/filesetschema.py

@@ -1,5 +1,7 @@
 import contextlib
 
+import os.path
+
 from pathlib import Path
 
 from typing import List, Tuple, Optional, Union, Iterable, Set
@@ -118,8 +120,14 @@ class FileSetSchema(PathSchema):
             ext = utils.get_file_ext(filename)
             filetype = utils.get_default_iomap().get(ext, ext)
 
+        try:
+            dataroot = self._get_active_dataroot(dataroot)
+        except ValueError as e:
+            if not os.path.isabs(filename):
+                raise e
+
         # adding files to dictionary
-        with self.active_dataroot(self._get_active_dataroot(dataroot)):
+        with self.active_dataroot(dataroot):
             if clobber:
                 return self.set('fileset', fileset, 'file', filetype, filename)
             else:

siliconcompiler/schema_support/pathschema.py

@@ -11,7 +11,9 @@ from siliconcompiler.schema.parameter import Parameter, Scope
 from siliconcompiler.schema.utils import trim
 
 from siliconcompiler.package import Resolver
+from siliconcompiler.utils.logging import get_stream_handler
 from siliconcompiler.utils.paths import collectiondir, cwdirsafe
+from siliconcompiler.utils.multiprocessing import MPManager
 
 
 class PathSchemaBase(BaseSchema):
@@ -19,6 +21,15 @@ class PathSchemaBase(BaseSchema):
     Schema extension to add simpler find_files and check_filepaths
     '''
 
+    def __getlogger(self, logger_name: str) -> logging.Logger:
+        schema_root = self._parent(root=True)
+        root_logger = getattr(schema_root, "logger", MPManager.logger())
+        logger = root_logger.getChild(logger_name)
+        if not logger.handlers:
+            logger.addHandler(get_stream_handler(schema_root, in_run=False, step=None, index=None))
+            logger.setLevel(logging.INFO)
+        return logger
+
     def find_files(self, *keypath: str,
                    missing_ok: bool = False,
                    step: Optional[str] = None, index: Optional[Union[int, str]] = None) \
@@ -69,13 +80,10 @@ class PathSchemaBase(BaseSchema):
             True if all file paths are valid, otherwise False.
         '''
         schema_root = self._parent(root=True)
-        logger = getattr(schema_root,
-                         "logger",
-                         logging.getLogger("siliconcompiler.check_filepaths"))
 
         return super()._check_filepaths(
             ignore_keys=ignore_keys,
-            logger=logger,
+            logger=self.__getlogger("check_filepaths"),
             collection_dir=collectiondir(schema_root),
             cwd=cwdirsafe(schema_root))
 
@@ -121,13 +129,11 @@ class PathSchemaBase(BaseSchema):
             >>> hashlist = hash_files('input', 'rtl', 'verilog')
             Computes, stores, and returns hashes of files in :keypath:`input, rtl, verilog`.
         '''
-        schema_root = self._parent(root=True)
-        logger = getattr(schema_root,
-                         "logger",
-                         logging.getLogger("siliconcompiler.hash_files"))
-
         if verbose:
-            logger.info(f"Computing hash value for [{','.join([*self._keypath, *keypath])}]")
+            self.__getlogger("hash_files").info(
+                f"Computing hash value for [{','.join([*self._keypath, *keypath])}]")
+
+        schema_root = self._parent(root=True)
 
         hashes = super()._hash_files(*keypath,
                                      missing_ok=missing_ok,

siliconcompiler/tool.py

@@ -997,7 +997,7 @@ class Task(NamedSchema, PathSchema, DocsSchema):
                      open(stderr_file, 'w') as stderr_writer:
                     if stderr_file == stdout_file:
                         stderr_writer.close()
-                        stderr_writer = sys.stdout
+                        stderr_writer = stdout_writer
 
                     with contextlib.redirect_stderr(stderr_writer), \
                          contextlib.redirect_stdout(stdout_writer):
@@ -1009,6 +1009,8 @@ class Task(NamedSchema, PathSchema, DocsSchema):
             finally:
                 with sc_open(stdout_file) as stdout_reader, \
                      sc_open(stderr_file) as stderr_reader:
+                    if stdout_file == stderr_file:
+                        stderr_reader = None
                     read_stdio(stdout_reader, stderr_reader)
 
                 if resource:

siliconcompiler/tools/keplerformal/lec.py

@@ -37,7 +37,7 @@ class LECTask(Task):
         libcorners = scenario.get_libcorner(self.step, self.index)
         delay_model = self.project.get("asic", "delaymodel")
         for asiclib in self.project.get("asic", "asiclib"):
-            lib = self.project.get("library", asiclib, field="schema")
+            lib = self.project.get_library(asiclib)
             for corner in libcorners:
                 if not lib.valid("asic", "libcornerfileset", corner, delay_model):
                     continue
@@ -64,7 +64,7 @@ class LECTask(Task):
             libcorners = scenario.get_libcorner(self.step, self.index)
             delay_model = self.project.get("asic", "delaymodel")
             for asiclib in self.project.get("asic", "asiclib"):
-                lib = self.project.get("library", asiclib, field="schema")
+                lib = self.project.get_library(asiclib)
                 for corner in libcorners:
                     if not lib.valid("asic", "libcornerfileset", corner, delay_model):
                         continue

siliconcompiler/tools/klayout/export.py

@@ -98,7 +98,7 @@ class ExportTask(KLayoutTask, ScreenshotParams):
                 lib_requires_stream = False
 
             req_set = False
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             for s in sc_stream_order:
                 for fileset in libobj.get("asic", "aprfileset"):
                     if libobj.valid("fileset", fileset, "file", s):

siliconcompiler/tools/openroad/_apr.py

@@ -1218,6 +1218,10 @@ class APRTask(OpenROADTask):
                            "used to indicate if global routing information should be loaded",
                            defvalue=False)
 
+        self.add_parameter("load_sdcs", "bool",
+                           "used to indicate if SDC files should be loaded before APR",
+                           defvalue=True)
+
         self.add_parameter("global_connect_fileset", "[(str,str)]",
                            "list of libraries and filesets to generate connects from")
 
@@ -1264,6 +1268,18 @@ class APRTask(OpenROADTask):
         """
         self.set("var", "ord_heatmap_bins", (x, y), step=step, index=index)
 
+    def set_openroad_loadsdcs(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None) -> None:
+        """
+        Enables or disables loading SDC files before APR.
+
+        Args:
+            enable: True to load SDC files, False to disable.
+            step: The specific step to apply this configuration to.
+            index: The specific index to apply this configuration to.
+        """
+        self.set("var", "load_sdcs", enable, step=step, index=index)
+
     def set_openroad_powercorner(self, corner: str,
                                  step: Optional[str] = None, index: Optional[str] = None) -> None:
         """
@@ -1334,6 +1350,7 @@ class APRTask(OpenROADTask):
         self.add_required_key("var", "ord_enable_images")
         self.add_required_key("var", "ord_heatmap_bins")
         self.add_required_key("var", "load_grt_setup")
+        self.add_required_key("var", "load_sdcs")
 
         if not self.get("var", "global_connect_fileset"):
             self.__import_globalconnect_filesets()
@@ -1346,9 +1363,20 @@ class APRTask(OpenROADTask):
         libcorners = set()
         for scenario in self.project.constraint.timing.get_scenario().values():
             libcorners.update(scenario.get_libcorner(self.step, self.index))
+            self.add_required_key(scenario, "pexcorner")
+            self.add_required_key(scenario, "libcorner")
+            if scenario.get_check(self.step, self.index):
+                self.add_required_key(scenario, "check")
+            mode = scenario.get_mode(self.step, self.index)
+            if mode:
+                self.add_required_key(scenario, "mode")
+                if self.get("var", "load_sdcs"):
+                    mode_obj = self.project.constraint.timing.get_mode(mode)
+                    self.add_required_key(mode_obj, "sdcfileset")
+
         delay_model = self.project.get("asic", "delaymodel")
         for asiclib in self.project.get("asic", "asiclib"):
-            lib = self.project.get("library", asiclib, field="schema")
+            lib = self.project.get_library(asiclib)
             for corner in libcorners:
                 if not lib.valid("asic", "libcornerfileset", corner, delay_model):
                     continue
@@ -1362,24 +1390,53 @@ class APRTask(OpenROADTask):
 
     def __import_globalconnect_filesets(self):
         for lib in self.project.get("asic", "asiclib"):
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             if libobj.valid("tool", "openroad", "global_connect_fileset"):
                 for fileset in libobj.get("tool", "openroad", "global_connect_fileset"):
                     self.add_openroad_globalconnectfileset(lib, fileset)
 
     def _set_reports(self, task_reports: List[str]):
-        self.set("var", "reports", set(task_reports).difference(self.get("var", "skip_reports")))
+        skip_reports = set(self.get("var", "skip_reports"))
+
+        if not self.get("var", "load_sdcs"):
+            skip_reports.update((
+                "setup",
+                "hold",
+                "unconstrained",
+                "clock_skew",
+                "fmax",
+                "check_setup",
+                "clock_placement",
+                "clock_trees"))
+
+        self.set("var", "reports", set(task_reports).difference(skip_reports))
 
         if "power" in self.get("var", "reports"):
             self.add_required_key("var", "power_corner")
 
     def _add_pnr_inputs(self):
-        if f"{self.design_topmodule}.sdc" in self.get_files_from_input_nodes():
-            self.add_input_file(ext="sdc")
-        else:
-            for lib, fileset in self.project.get_filesets():
-                if lib.has_file(fileset=fileset, filetype="sdc"):
-                    self.add_required_key(lib, "fileset", fileset, "file", "sdc")
+        if self.get("var", "load_sdcs"):
+            if f"{self.design_topmodule}.sdc" in self.get_files_from_input_nodes():
+                self.add_input_file(ext="sdc")
+            else:
+                for lib, fileset in self.project.get_filesets():
+                    if lib.has_file(fileset=fileset, filetype="sdc"):
+                        self.add_required_key(lib, "fileset", fileset, "file", "sdc")
+
+                modes = set()
+                for scenario in self.project.constraint.timing.get_scenario().values():
+                    mode = scenario.get_mode(self.step, self.index)
+                    if mode:
+                        modes.add(mode)
+                        self.add_required_key(scenario, "mode")
+                        mode_obj = self.project.constraint.timing.get_mode(mode)
+                        self.add_required_key(mode_obj, "sdcfileset")
+
+                for mode in modes:
+                    mode_obj = self.project.constraint.timing.get_mode(mode)
+                    for lib, fileset in mode_obj.get_sdcfileset():
+                        libobj = self.project.get_library(lib)
+                        self.add_required_key(libobj, "fileset", fileset, "file", "sdc")
 
         if f"{self.design_topmodule}.odb" in self.get_files_from_input_nodes():
             self.add_input_file(ext="odb")
@@ -1389,14 +1446,15 @@ class APRTask(OpenROADTask):
             pass
 
     def _add_pnr_outputs(self):
-        self.add_output_file(ext="sdc")
+        if self.get("var", "load_sdcs"):
+            self.add_output_file(ext="sdc")
         self.add_output_file(ext="vg")
         self.add_output_file(ext="lec.vg")
         self.add_output_file(ext="def")
         self.add_output_file(ext="odb")
 
         for lib in self.project.get("asic", "asiclib"):
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             for celltype in ["decap", "tie", "filler", "tap", "endcap", "antenna", "physicalonly"]:
                 if libobj.valid("asic", "cells", celltype) and \
                         libobj.get("asic", "cells", celltype):

siliconcompiler/tools/openroad/power_grid.py

@@ -94,7 +94,7 @@ class PowerGridTask(APRTask, OpenROADSTAParameter, OpenROADPSMParameter):
 
     def __import_pdn_filesets(self):
         for lib in self.project.get("asic", "asiclib"):
-            libobj = self.project.get("library", lib, field="schema")
+            libobj = self.project.get_library(lib)
             if libobj.valid("tool", "openroad", "power_grid_fileset"):
                 for fileset in libobj.get("tool", "openroad", "power_grid_fileset"):
                     self.add_openroad_powergridfileset(lib, fileset)

siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl

@@ -2,22 +2,24 @@
 # Read timing constraints
 ###############################
 
-if { [file exists "inputs/${sc_topmodule}.sdc"] } {
-    set sdc "inputs/${sc_topmodule}.sdc"
-    puts "Reading SDC: ${sdc}"
-    read_sdc $sdc
-} else {
-    set sdcs [sc_cfg_get_fileset $sc_designlib [sc_cfg_get option fileset] sdc]
-    if { [llength $sdcs] > 0 } {
-        foreach sdc $sdcs {
+if { [sc_cfg_tool_task_get var load_sdcs] } {
+    if { [file exists "inputs/${sc_topmodule}.sdc"] } {
+        set sdc "inputs/${sc_topmodule}.sdc"
+        puts "Reading SDC: ${sdc}"
+        read_sdc $sdc
+    } else {
+        set sdcs [sc_cfg_get_fileset $sc_designlib [sc_cfg_get option fileset] sdc]
+        if { [llength $sdcs] > 0 } {
+            foreach sdc $sdcs {
+                puts "Reading SDC: ${sdc}"
+                read_sdc $sdc
+            }
+        } else {
+            # fall back on default auto generated constraints file
+            set sdc [sc_cfg_tool_task_get var opensta_generic_sdc]
             puts "Reading SDC: ${sdc}"
-            read_sdc $sdc
+            utl::warn FLW 1 "Defaulting back to default SDC"
+            read_sdc "${sdc}"
         }
-    } else {
-        # fall back on default auto generated constraints file
-        set sdc [sc_cfg_tool_task_get var opensta_generic_sdc]
-        puts "Reading SDC: ${sdc}"
-        utl::warn FLW 1 "Defaulting back to default SDC"
-        read_sdc "${sdc}"
     }
 }

siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl

@@ -1 +1,3 @@
-write_sdc "outputs/${sc_topmodule}.sdc"
+if { [sc_cfg_tool_task_get var load_sdcs] } {
+    write_sdc "outputs/${sc_topmodule}.sdc"
+}

siliconcompiler/tools/vpr/__init__.py

@@ -273,7 +273,7 @@ class VPRTask(Task):
                 self.add_required_key(lib, "fileset", fileset, "file", "sdc")
                 self.set("var", "enable_timing_analysis", True)
 
-        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
         self.add_required_key(fpga, "tool", "vpr", "devicecode")
         self.add_required_key(fpga, "tool", "vpr", "clock_model")
         self.add_required_key(fpga, "tool", "vpr", "archfile")
@@ -287,7 +287,7 @@ class VPRTask(Task):
     def runtime_options(self):
         options = super().runtime_options()
 
-        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         options.extend(["--device", fpga.get("tool", "vpr", "devicecode")])
 
@@ -393,17 +393,17 @@ class VPRTask(Task):
         for report in glob.glob("*.rpt"):
             shutil.move(report, 'reports')
 
-        fpga = self.project.get("fpga", "device")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         dff_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "registers"):
-            dff_cells = self.project.get("library", fpga, "tool", "yosys", "registers")
+        if fpga.valid("tool", "yosys", "registers"):
+            dff_cells = fpga.get("tool", "yosys", "registers")
         brams_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "brams"):
-            brams_cells = self.project.get("library", fpga, "tool", "yosys", "brams")
+        if fpga.valid("tool", "yosys", "brams"):
+            brams_cells = fpga.get("tool", "yosys", "brams")
         dsps_cells = []
-        if self.project.valid("library", fpga, "tool", "yosys", "dsps"):
-            dsps_cells = self.project.get("library", fpga, "tool", "yosys", "dsps")
+        if fpga.valid("tool", "yosys", "dsps"):
+            dsps_cells = fpga.get("tool", "yosys", "dsps")
 
         stat_extract = re.compile(r'  \s*(.*)\s*:\s*([0-9]+)')
         lut_match = re.compile(r'([0-9]+)-LUT')

siliconcompiler/tools/vpr/place.py

@@ -48,8 +48,7 @@ class PlaceTask(VPRTask):
             if files:
                 pcf_file = files[0]
 
-                fpga = self.project.get("library", self.project.get("fpga", "device"),
-                                        field="schema")
+                fpga = self.project.get_library(self.project.get("fpga", "device"))
                 map_file = fpga.find_files("tool", "vpr", "constraintsmap")
 
                 constraints_map = load_constraints_map(map_file)

siliconcompiler/tools/yosys/syn_asic.py

@@ -39,7 +39,7 @@ class _ASICTask(ASICTask, YosysTask):
 
         delaymodel = self.project.get("asic", "delaymodel")
         for lib in self.project.get("asic", "asiclib"):
-            lib_obj = self.project.get("library", lib, field="schema")
+            lib_obj = self.project.get_library(lib)
             for corner in self.get("var", "synthesis_corner"):
                 if lib_obj.get("asic", "libcornerfileset", corner, delaymodel):
                     self.add_required_key(lib_obj, "asic", "libcornerfileset", corner, delaymodel)
@@ -81,7 +81,7 @@ class _ASICTask(ASICTask, YosysTask):
         # Generate synthesis_libraries for Yosys use
         fileset_map = []
         for lib in self.project.get("asic", "asiclib"):
-            lib_obj = self.project.get("library", lib, field="schema")
+            lib_obj = self.project.get_library(lib)
             for corner in self.get("var", "synthesis_corner"):
                 for fileset in lib_obj.get("asic", "libcornerfileset", corner, delaymodel):
                     fileset_map.append((lib_obj, fileset))
@@ -696,7 +696,7 @@ class ASICSynthesis(_ASICTask, YosysTask):
         self.add_output_file(ext="vg", clobber=True)
         self.add_output_file(ext="netlist.json")
 
-        mainlib = self.project.get("library", self.project.get("asic", "mainlib"), field="schema")
+        mainlib = self.project.get_library(self.project.get("asic", "mainlib"))
 
         if self.get('var', 'abc_constraint_driver') is not None:
             self.add_required_key("var", "abc_constraint_driver")
@@ -799,7 +799,7 @@ class ASICSynthesis(_ASICTask, YosysTask):
 
     def _get_clock_period(self):
         mainlib = self.project.get("asic", "mainlib")
-        clock_units_multiplier = self.project.get("library", mainlib, field="schema").get(
+        clock_units_multiplier = self.project.get_library(mainlib).get(
             "tool", "yosys", "abc_clock_multiplier") / 1000
 
         _, period = self.get_clock()

siliconcompiler/tools/yosys/syn_fpga.py

@@ -98,7 +98,7 @@ class FPGASynthesis(YosysTask):
 
         self._synthesis_post_process()
 
-        fpga = self.project.get("fpga", "device")
+        fpga = self.project.get_library(self.project.get("fpga", "device"))
 
         with sc_open("reports/stat.json") as f:
             metrics = json.load(f)
@@ -113,15 +113,14 @@ class FPGASynthesis(YosysTask):
                 return
 
             dff_cells = []
-            if self.project.valid("library", fpga, "tool", "yosys", "registers"):
-                dff_cells = self.project.get("library", fpga, "tool", "yosys", "registers")
+            if fpga.valid("tool", "yosys", "registers"):
+                dff_cells = fpga.get("tool", "yosys", "registers")
             brams_cells = []
-            if self.project.valid("library", fpga, "tool", "yosys", "brams"):
-                brams_cells = self.project.get("library", fpga, "tool", "yosys", "brams")
+            if fpga.valid("tool", "yosys", "brams"):
+                brams_cells = fpga.get("tool", "yosys", "brams")
             dsps_cells = []
-            if self.project.valid("library", fpga, "tool", "yosys", "dsps"):
-                dsps_cells = self.project.get("library", fpga, "tool", "yosys", "dsps")
-
+            if fpga.valid("tool", "yosys", "dsps"):
+                dsps_cells = fpga.get("tool", "yosys", "dsps")
             data = {
                 "registers": 0,
                 "luts": 0,

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "0004adbadb9b28cbc00b87c0b2a089164e439441",
+    "git-commit": "e7da048335b841ec917d0c421200f2b0eda54f2c",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "128ea3cf283ba2ac0af699543c8e037cc9bfc0a5",
+    "git-commit": "0429ac324b2cd4a12783e053b9c85f5d40f4cde8",
     "auto-update": true
   },
   "netgen": {
@@ -101,7 +101,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.60",
+    "git-commit": "v0.61",
     "version-prefix": "",
     "auto-update": true
   },
@@ -145,7 +145,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "64b44616a3798f07453b14ea03e4ac8a16b77313",
+    "git-commit": "4e1ad7c11e23cffe131aa5c478083f1d99f0c0be",
     "docker-depends": "yosys",
     "auto-update": true
   },

siliconcompiler/utils/logging.py

@@ -145,3 +145,9 @@ def get_console_formatter(project, in_run, step, index):
     if support_color:
         return SCColorLoggerFormatter(base_format)
     return base_format
+
+
+def get_stream_handler(project, in_run, step, index):
+    handler = logging.StreamHandler(stream=sys.stdout)
+    handler.setFormatter(get_console_formatter(project, in_run, step, index))
+    return handler

{siliconcompiler-0.36.1.dist-info → siliconcompiler-0.36.2.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: siliconcompiler
-Version: 0.36.1
+Version: 0.36.2
 Summary: A compiler framework that automates translation from source code to silicon.
 Author: Zero ASIC
 License: Apache License 2.0
@@ -38,7 +38,7 @@ Requires-Dist: PyYAML<7.0.0,>=6.0.0
 Requires-Dist: GitPython<3.2,>=3.1.44
 Requires-Dist: PyGithub<2.9.0,>=2.8.0
 Requires-Dist: urllib3>=1.26.0
-Requires-Dist: lambdapdk>=0.2.6
+Requires-Dist: lambdapdk>=0.2.7
 Requires-Dist: fasteners>=0.20
 Requires-Dist: pandas>=1.1.5
 Requires-Dist: psutil>=5.8.0

{siliconcompiler-0.36.1.dist-info → siliconcompiler-0.36.2.dist-info}/RECORD

@@ -1,16 +1,16 @@
 siliconcompiler/__init__.py,sha256=I1RN8BMRpuAx9tdx5CLNlpIqT-xg2EwvOB8TcqHQSN0,1114
 siliconcompiler/_common.py,sha256=1bY1qdFxnstAyhJrkJCBhSlZ614dlmcwL0Bf7NOneyY,1047
-siliconcompiler/_metadata.py,sha256=-pxs4KeKbkUBRc5ueEJUJTf85aJaDo9JcbOMvtxp5mw,1286
-siliconcompiler/asic.py,sha256=KXs-mjFHjiCRlyUClNIb-Zvdkxa8dGafStHm-rX3vu8,28912
+siliconcompiler/_metadata.py,sha256=Wbvn4WiI5YksrKzN6imES3t0IdAE2duTyS4WDyLixpg,1286
+siliconcompiler/asic.py,sha256=IFKPCZrhXHtyp9qieRqVA1jhKPPmVmYBnC1DvCXpPTo,28836
 siliconcompiler/checklist.py,sha256=MD0cVYm5RrxSDCBVO1nakGC6LH5hWnzisaF4e0V6eV8,24909
-siliconcompiler/design.py,sha256=vFcenCV1Q3IVsdpeh4h9wCm4lyAfJMH5e-Oqg4Ji4sQ,34555
+siliconcompiler/design.py,sha256=dUQolB1fzQX20WWGxxl8LMaDma0DITv_OY6_qIgPk5M,34766
 siliconcompiler/flowgraph.py,sha256=oGWC84amHIcx2gUO7QMkJ7vphfaOzrkp0LXHPsIZVpU,65557
 siliconcompiler/fpga.py,sha256=8uvmIyvWOWx5X1JP3xaSpkA9hVyox4l-hK63aYzN8-w,9075
 siliconcompiler/library.py,sha256=pPzUaVZXizS6eRLsnSrILwCgBtHfOzWk9CwC5COoHOk,16065
 siliconcompiler/pdk.py,sha256=rENDQve5edt7EkdgnNfW-mfgJVklShLbvYddaEA1-_k,31581
-siliconcompiler/project.py,sha256=dyqKwlKnv23ccvWs-8jghmE8_16qcMGCfdz_azGLMCE,51820
+siliconcompiler/project.py,sha256=tOQsb0WuWyCmGlIWICD0IOYxx7se-CMc94d_0hyj9yY,52191
 siliconcompiler/schematic.py,sha256=0PVFqZvJZW_e2NRGvv6DJPHGjwOlao1qHgZLhgCaEcQ,18385
-siliconcompiler/tool.py,sha256=U56aDkSm2kkn_BdmBgxV0id9CmgKLw6JSWUV5F_1Y58,111684
+siliconcompiler/tool.py,sha256=BpwmHLpvepyPoKxEfSspbXtBR0PUf4rjHQ0uzqaRGG8,111783
 siliconcompiler/apps/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/apps/_common.py,sha256=uldDgTeAEfo1Y0X_hxpr0yjSW0W0c5UaiuSpgk7aUuk,8605
 siliconcompiler/apps/sc_dashboard.py,sha256=BU3hPC7OzfUpkKEVsBD_46zd4OzHO86eJMB5CaWpVf0,3496
@@ -84,7 +84,7 @@ siliconcompiler/metrics/asic.py,sha256=SwhBh2xSni4yYcV-PMfW4V3UhBptLtHhKlv-sv7CJ
 siliconcompiler/metrics/fpga.py,sha256=UgAi0O67aIc2evdBvSsy226UcHlxqYOZqPv8NfEfys8,10057
 siliconcompiler/optimizer/__init__.py,sha256=wdSuv3U7hoSdZn-TkaQtYehVdhS5F35Mb1McgaUw3hc,6599
 siliconcompiler/optimizer/vizier.py,sha256=JtoPktsa-qHN0i4PsfRnxvQAT0yVvQVRfdyYNOCYgU4,9011
-siliconcompiler/package/__init__.py,sha256=bXV3U6glsViFjDr1B1sKtNfymPEBhrQ1Sny5tkLha48,25479
+siliconcompiler/package/__init__.py,sha256=kWzaJBioKcJBlbmKJKcopp0BjKULyNeFNdYJKdIIs1g,25484
 siliconcompiler/package/git.py,sha256=xq8_qi-2pmhswJ9ssUtRgSUNxpMGKZLDmnkdFYeq9iA,5950
 siliconcompiler/package/github.py,sha256=bzV-XrcmFMloa7_yhdxFjfe4r9OH36xHGY6ZCgHv0mA,6785
 siliconcompiler/package/https.py,sha256=OJL1PxOf6FbuGUrEx3gWpLEocd7p9gf9uvKh6a-7OQc,5753
@@ -156,11 +156,11 @@ siliconcompiler/schema/docs/utils.py,sha256=SCR9hYlQHUWbC6fT7LttKIfktzhMfrCL0BVx
 siliconcompiler/schema_support/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/schema_support/cmdlineschema.py,sha256=r-v1lOMOx0wehG3-hgy6JuJVuzivhxt5t83KwxS8pfs,10691
 siliconcompiler/schema_support/dependencyschema.py,sha256=LY6RhtxLOxjOBj7FBw88i0TlLd7WZlNh5omHBtU5VO8,9895
-siliconcompiler/schema_support/filesetschema.py,sha256=CE_JpDJYWqQzGgImgwPWOS7z_ymk4hY3H5I0qVU33Qo,11513
+siliconcompiler/schema_support/filesetschema.py,sha256=ouKKUSNCry7ggzya8wGFvbEf2u3GwyERMhyYxUf3fmM,11675
 siliconcompiler/schema_support/metric.py,sha256=mLzdtpM76l2cPINGWONrAjBMU28ZnQR_yLOGMYBLBV4,16158
 siliconcompiler/schema_support/option.py,sha256=URcEzo4qL34BU5j55hw0hnGy1Q-cVaHefTVmuYzYnOE,56105
 siliconcompiler/schema_support/packageschema.py,sha256=tB6wYEhZliaUVZDq40DlEfoo8ken6-Xh6zIafBRrxr4,10508
-siliconcompiler/schema_support/pathschema.py,sha256=Itr7HXf2xpGrZYzh4KIwBpuMqiD8KvWGyqHwkFyffVw,20876
+siliconcompiler/schema_support/pathschema.py,sha256=EJ1n7wrUVKKhe46M9Ip6PNJU1WvOzWU1Ol5F0jduuqY,21198
 siliconcompiler/schema_support/record.py,sha256=LjosKbOerR3-j5e2rAOQTDm932caeiiiTXKBW2mh_uE,19653
 siliconcompiler/targets/__init__.py,sha256=eWgvV4DeombChYqLxs5z_rOZ7Mt1q7N0WEetuBcNjZ4,1678
 siliconcompiler/targets/asap7_demo.py,sha256=sG3GdqkqGjhco43JHVV6-ys734fYTksx68VIJpZ4_IU,4760
@@ -210,11 +210,11 @@ siliconcompiler/tools/icarus/compile.py,sha256=dsbPgns_5VVclpQHTZZxAG9A2UUMYjpXY
 siliconcompiler/tools/icepack/__init__.py,sha256=FJnRz9I3Y5c2stJJXHSSBySTkpwJsYJ_HP1IuTPNZTo,226
 siliconcompiler/tools/icepack/bitstream.py,sha256=3tkwpZ84kQT7Rk0BlWdNEcx1KginTqNkKfyXIrcYKlY,598
 siliconcompiler/tools/keplerformal/__init__.py,sha256=ENX6RIvg1q0byEyiIN5WDo-igP6wNYviZc4-N0FvQMg,275
-siliconcompiler/tools/keplerformal/lec.py,sha256=6fJmWvXywRMBVKvDK-lm7ol19w1VqY53nwhttfWlyp0,4669
+siliconcompiler/tools/keplerformal/lec.py,sha256=SePSOeQm-VbpnblcZXU7KyfK8MWzk4MHevMtx3PEBM0,4631
 siliconcompiler/tools/klayout/__init__.py,sha256=t2WHhiUAltGLFkw0N7wzs0m9Hx1xZo2tGx4d3uKSusY,8670
 siliconcompiler/tools/klayout/convert_drc_db.py,sha256=ekzfQJ5Gef0Xo9KzrbXgCC4P5KpGKS4ZSfWHrM9Gmic,812
 siliconcompiler/tools/klayout/drc.py,sha256=DgdUMVmNEQ56Imd2Z5LYkuBr7yUAK-wy6_cBGAUGc9E,3530
-siliconcompiler/tools/klayout/export.py,sha256=itIlyHayyihSvmXyZYi0XsspFpGMK5wXBhmLec6BhL8,5026
+siliconcompiler/tools/klayout/export.py,sha256=42fviCWLIyMsXvSygGUErq1oypKqZNh2X1qlOFRFuqc,5007
 siliconcompiler/tools/klayout/operations.py,sha256=sUSHDPsgDm6PnehgANQIlDP6K2rnNLgMpQEXVakBQ3c,8681
 siliconcompiler/tools/klayout/screenshot.py,sha256=hpUfZJ6dcgYypyLtcgfWByJOCPh4r16UvmoX_DgbOgg,4979
 siliconcompiler/tools/klayout/show.py,sha256=Lkmf90qOomLvrYELRhSSzH9F2i7cgsAfETHU2lVRxDs,1494
@@ -238,7 +238,7 @@ siliconcompiler/tools/netgen/scripts/sc_lvs.tcl,sha256=8zZGe5WS6LNnvNiw7zouCvOyc
 siliconcompiler/tools/nextpnr/__init__.py,sha256=IbOR4eOErXQ2fETrFZTW1LYECkp-umXad2iNBGnp7rk,274
 siliconcompiler/tools/nextpnr/apr.py,sha256=pWkV3gnz4m8Nap7HvMSJNCfYBnhEE6EtfU4fzADGMzs,2540
 siliconcompiler/tools/openroad/__init__.py,sha256=clCBUnzpaLWA0wga6rx-N7bJMiSaM8ERnSqNZnWtDWw,19637
-siliconcompiler/tools/openroad/_apr.py,sha256=uYsFGVzHpSp8_hlTnlX4oF7z6XyHpVqF6c7aP30hOUY,81731
+siliconcompiler/tools/openroad/_apr.py,sha256=-4fbiyH9M7h5wYNBS9dcuHrf63Eg3WyExsV7Gx3FDe0,84244
 siliconcompiler/tools/openroad/antenna_repair.py,sha256=L4F5dprHfUz641t-XlvPi1Kkgl1P-mdXUqP3wUeV9yE,2858
 siliconcompiler/tools/openroad/clock_tree_synthesis.py,sha256=w6xXtx3y1hXnjIYk3qX46JyghGne2yCTfgRz97sACIU,1009
 siliconcompiler/tools/openroad/detailed_placement.py,sha256=dZDRwjkExZjPRRJjgxQLX3khpOR3mJe5mnJ7rc_32Os,911
@@ -252,7 +252,7 @@ siliconcompiler/tools/openroad/init_floorplan.py,sha256=ro-HNuf-MIDlNHdMrHaYCW0d
 siliconcompiler/tools/openroad/macro_placement.py,sha256=M-BwOeKsoJAqpsDhRz2of_5fsrmterwkzfpS6mqvemo,18870
 siliconcompiler/tools/openroad/metrics.py,sha256=rJc3Ea9PS6C6Qp1dOJqcIFRF3sX-FnyvYIKNRQm1I1s,771
 siliconcompiler/tools/openroad/pin_placement.py,sha256=utwYKDk0SlZVoBkPCp_40qzjHRN_7P8lVasT47T8WEw,768
-siliconcompiler/tools/openroad/power_grid.py,sha256=OZFHEXRy1vrJY_CCkZnHuUiWymeGnb1HO_wVeGGbSpA,4572
+siliconcompiler/tools/openroad/power_grid.py,sha256=Zs8glIIfzSeN5RqVIjVi0iE7Q1H8UDVslZED__kwlIs,4553
 siliconcompiler/tools/openroad/power_grid_analysis.py,sha256=KeOjbUuOW4Hp7u3jVaNmGcZgnRasmFnprbPNWUQioZk,7233
 siliconcompiler/tools/openroad/rcx_bench.py,sha256=PxBM3fx-x1ZY5RGg5JhG05LVL2oQW0Lfv4QUEhvONlk,1949
 siliconcompiler/tools/openroad/rcx_extract.py,sha256=-rUKqhPSvDw0-p5CLq6SG1QZ6C1YUxmt-PAh1o3Y3q0,1267
@@ -289,12 +289,12 @@ siliconcompiler/tools/openroad/scripts/common/debugging.tcl,sha256=i4oNtC0rQq3Ja
 siliconcompiler/tools/openroad/scripts/common/procs.tcl,sha256=kOS5ZJ-DEZxpr4Xy90ftSm68Y1TJujRoAA5YtrXDUA4,26474
 siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl,sha256=ghCw5V7GzM6sNUrNVh31rHd36re-ueZWtWaqesFcQmc,1888
 siliconcompiler/tools/openroad/scripts/common/read_liberty.tcl,sha256=xdNEJEKqQyVPiZ6xSHJv0lg8sFMPXoQ9q9OQ0F_4boA,880
-siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl,sha256=gUYXIH_cUXBU1WnJOd6_V2sVKkoDz_3TrTGSV7IC05Q,723
+siliconcompiler/tools/openroad/scripts/common/read_timing_constraints.tcl,sha256=LX0MEK0KNUGmDR3R9f7A4B1gEOYf-zqNYZQxurr-6wE,847
 siliconcompiler/tools/openroad/scripts/common/reports.tcl,sha256=9gdzKYiacv35R9XlGtL-cw4IXstyPZF6GbPxDTWAAtU,7474
 siliconcompiler/tools/openroad/scripts/common/screenshot.tcl,sha256=1pZNbKsxo6x0sprTbv1MrbmSScM8g71XdDt3RiZizTo,330
 siliconcompiler/tools/openroad/scripts/common/write_data.tcl,sha256=xFFgR6mCpQEy8ATfSz1kUFr2BBnaPsv4cSHnWh7JqC8,100
 siliconcompiler/tools/openroad/scripts/common/write_data_physical.tcl,sha256=V-Ul99R2j8xuCQEfySuUKGXu5YonIoa4ByBjY2odR7E,436
-siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl,sha256=_Axy9V9r0xWU0xLVwMdgkPUF6-C3cVmtE8J-j0OIzII,40
+siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl,sha256=gzKYlbvRCKOaUaXmv3ZkPiLHwFjCA5hKJkA2ayCjZhM,92
 siliconcompiler/tools/openroad/scripts/common/write_images.tcl,sha256=uvCmhhN9cY9TC_I99Nbv6TP7vepNqdwZYzC_Fce0ezo,13778
 siliconcompiler/tools/openroad/scripts/rcx/sc_rcx_bench.tcl,sha256=eEYI8U26LYGR-zIaYPKCxg1IzohudquhpmuWYkTA4-Q,664
 siliconcompiler/tools/openroad/scripts/rcx/sc_rcx_extract.tcl,sha256=1mPpVpBAX7uiBESb1rVBrYk-IzCkd-GaH2ghFSuguMo,487
@@ -334,10 +334,10 @@ siliconcompiler/tools/vivado/scripts/sc_place.tcl,sha256=QwxhxL69lCrReqwx_lnHMqf
 siliconcompiler/tools/vivado/scripts/sc_route.tcl,sha256=rdKwlSkpTEh_c95GnSaywfeh14sddBKjXaKZ3l-rqLA,367
 siliconcompiler/tools/vivado/scripts/sc_run.tcl,sha256=FwW6-_EdryI3eZ7lFKSRK3oVIk5Y51B9tRVSSlDEPrY,1052
 siliconcompiler/tools/vivado/scripts/sc_syn_fpga.tcl,sha256=Eyc1zxdmm0K0g8efee3qbWhhXs61XwIHcg6-0l28V4Q,1259
-siliconcompiler/tools/vpr/__init__.py,sha256=n55Cghyzlw_gQ7gdSdAh1hHMXYqrbUcs-vfV_hKtl10,23014
+siliconcompiler/tools/vpr/__init__.py,sha256=P5ndAbUO9pDPGHLhV1K52J2QcdGjy4adIkvcRust_L4,22852
 siliconcompiler/tools/vpr/_json_constraint.py,sha256=KcNcOQq7LZDiOXmQTwcGKczljs-7ugr-b8CNGHilnRc,2251
 siliconcompiler/tools/vpr/_xml_constraint.py,sha256=f7AeAtu4gDV08hPuorjRcniCyM5CLxJ6e8NgTbE79tw,2995
-siliconcompiler/tools/vpr/place.py,sha256=2D_Uc_-rRLIBABDUobXTFLkAktjuchVpSLsC2hFtgxU,3175
+siliconcompiler/tools/vpr/place.py,sha256=qZyEukI8kJ6-a0wrkdnmzVB-cvHddR5k71MwXFKXosY,3116
 siliconcompiler/tools/vpr/route.py,sha256=ImuAvlXEnsw93CMg33zt8-MY6Nh4lC2FqCOFrRTLmzw,7438
 siliconcompiler/tools/vpr/screenshot.py,sha256=JIiyvDrySNCfa0TOfrLoMJ63VcalDZASXRJUFns0Tho,1316
 siliconcompiler/tools/vpr/show.py,sha256=-DFoCRg9XqPwpb4_Frb39Qm6c_dPpzEsr9TqKSmrEaU,2344
@@ -348,8 +348,8 @@ siliconcompiler/tools/xyce/simulate.py,sha256=CQoDy0aOj9nbJkGFgHZnvKKIcimbz2abx3
 siliconcompiler/tools/yosys/__init__.py,sha256=prf36_x6A61lMnLXM3FRzlRZrJqEEMv-C7hyEi1b2Oo,18451
 siliconcompiler/tools/yosys/lec_asic.py,sha256=uOku8yyfVzlb9D_rEAIztDeKtz3DPE6peoz71nj3gvE,2168
 siliconcompiler/tools/yosys/prepareLib.py,sha256=8ppIR-o_EJiNZrpGg_sewJ4qyjtFXre9-iwo-a5Ev_g,2438
-siliconcompiler/tools/yosys/syn_asic.py,sha256=2zB0qtEYMY3zjGw7TAR3xvPWnVoa9ElYGtBBcUPlWSE,35772
-siliconcompiler/tools/yosys/syn_fpga.py,sha256=pBdOetcFD3LcE8BEjiUFyM4cNdQ0haq8UgWEMC1ZiFI,5291
+siliconcompiler/tools/yosys/syn_asic.py,sha256=tJiIoIuWnzIOG42kgoHC5Ge4sXqiVH1mcY0oa2jIYFc,35696
+siliconcompiler/tools/yosys/syn_fpga.py,sha256=NgiO6z9PJ1SxJHNkko1GD1CkdOj_UN18dmDSmFNOYzg,5166
 siliconcompiler/tools/yosys/scripts/procs.tcl,sha256=oJZJrcMHUyBLEKlUEd3PwwNBIDSCUIZlpfjsAuM2WUQ,4607
 siliconcompiler/tools/yosys/scripts/sc_lec.tcl,sha256=K2gsSg2cs1Dx3g4MP1EbkSv-ZkYDnU4iSHepj20TXSE,2996
 siliconcompiler/tools/yosys/scripts/sc_screenshot.tcl,sha256=Ss1c4ebLHy7QU1qX5Dn3OsDUOUVXmW9kvkMbr5TcMMw,2842
@@ -360,7 +360,7 @@ siliconcompiler/tools/yosys/techmaps/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeu
 siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v,sha256=M4T-ygiKmlsprl5eGGLaV5w6HVqlEepn0wlUDmOkapg,773
 siliconcompiler/tools/yosys/templates/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/yosys/templates/abc.const,sha256=TAq9ThdLMYCJGrtToEU0gWcLuEtjE4Gk8huBbTm1v-I,116
-siliconcompiler/toolscripts/_tools.json,sha256=AOzILpXFIgUB26QpsCeuY2bh8pLFlQXpCot6zgEHqE4,5271
+siliconcompiler/toolscripts/_tools.json,sha256=I4DJo2XABBfkduAkOF4nMBO68X2WpACH8KhU6hWO0Jc,5271
 siliconcompiler/toolscripts/_tools.py,sha256=P30KY_xbbjl8eHGsPAxDcAzWvJJpiL07ZfGZZDQbdR8,7174
 siliconcompiler/toolscripts/rhel8/install-chisel.sh,sha256=RJ7BiZhsXBLTgQhHUcRZmHqhKB6syVaC2nvVoGrIXOI,709
 siliconcompiler/toolscripts/rhel8/install-icarus.sh,sha256=EW7308IUGYOx7A22s7s0tNq90nHhrpHHUMrx3cd9lMM,962
@@ -475,15 +475,15 @@ siliconcompiler/toolscripts/ubuntu24/install-yosys.sh,sha256=0ZKbB8f7MrNd_u8IVav
 siliconcompiler/utils/__init__.py,sha256=bGyb85ncMnc4NpKR4y3g4I6WX9mQPhFw6l_AlSpYCg4,19444
 siliconcompiler/utils/curation.py,sha256=xVozvS1w77hLUomeVyWKUWxD5LJ7BZPjpd35D7zoY50,9228
 siliconcompiler/utils/issue.py,sha256=R6_HvVgp5uPQ72QKwAM8CQfDfKs3IKutykisq8Ht5vs,11029
-siliconcompiler/utils/logging.py,sha256=V3l07YocXPfD_0QbBDiW11bnnF4AWQMEmFvJfQscJnI,4667
+siliconcompiler/utils/logging.py,sha256=PAQp1skaxCKzhW5DnRdR7FB1-QCwqXCsurS13dDwkhE,4875
 siliconcompiler/utils/multiprocessing.py,sha256=zmSzHRThGYSioIcTbD_mtz84jjjlsAfZE97lK3RkffE,11624
 siliconcompiler/utils/paths.py,sha256=322TbbEaU5wM-06Xo-E8IlzMNV3DRi4GKDwg2EgTry4,4813
 siliconcompiler/utils/settings.py,sha256=8Zj5LDP32RAg8xisMJFgTxaoY7NWT90nAxaggk7K0sA,5819
 siliconcompiler/utils/showtools.py,sha256=ZWD2frgt0t2Eh8S9Hl3CwGEa1cnNiQx-06pWtyDTiic,1375
 siliconcompiler/utils/units.py,sha256=mppo7T5xI2P2S7SweE_qsOuoTc7RezVX61G2whCzpV4,6261
-siliconcompiler-0.36.1.dist-info/licenses/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
-siliconcompiler-0.36.1.dist-info/METADATA,sha256=2fmSrnW2HA3SVmyhfDhm6nH6EQdHZQGNpRcY9LMaHRY,11302
-siliconcompiler-0.36.1.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
-siliconcompiler-0.36.1.dist-info/entry_points.txt,sha256=5I-z7cmFNPRpD_x1dMQnm-oLwTPOMURxD5frvUM0GE8,832
-siliconcompiler-0.36.1.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
-siliconcompiler-0.36.1.dist-info/RECORD,,
+siliconcompiler-0.36.2.dist-info/licenses/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
+siliconcompiler-0.36.2.dist-info/METADATA,sha256=uhE-GmBSSTs8tLWD93WzQJdPJJftu_YLi6ntMJEZ2Lw,11302
+siliconcompiler-0.36.2.dist-info/WHEEL,sha256=_zCd3N1l69ArxyTb8rzEoP9TpbYXkqRFSNOD5OuxnTs,91
+siliconcompiler-0.36.2.dist-info/entry_points.txt,sha256=5I-z7cmFNPRpD_x1dMQnm-oLwTPOMURxD5frvUM0GE8,832
+siliconcompiler-0.36.2.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
+siliconcompiler-0.36.2.dist-info/RECORD,,