siliconcompiler 0.35.3__py3-none-any.whl → 0.36.0__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/common/write_images.tcl

@@ -1,6 +1,6 @@
 # Adopted from https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/3f9740e6b3643835e918d78ae1d377d65af0f0fb/flow/scripts/save_images.tcl
 
-proc sc_image_heatmap { name ident image_name title { gif false } { allow_bin_adjust 1 } } {
+proc sc_image_heatmap { name ident image_name title { gif -1 } { allow_bin_adjust 1 } } {
     lassign [sc_cfg_tool_task_get var ord_heatmap_bins] ord_heatmap_bins_x ord_heatmap_bins_y
 
     file mkdir reports/images/heatmap
@@ -124,12 +124,12 @@ proc sc_image_irdrop { net corner } {
         return
     }
 
-    set gif false
+    set gif -1
     if { [sc_check_version 21574] } {
-        set gif true
-    }
-    if { $gif } {
-        save_animated_gif -start "reports/images/heatmap/irdrop/${net}.${corner}.gif"
+        set gif [save_animated_gif -start "reports/images/heatmap/irdrop/${net}.${corner}.gif"]
+        if { $gif == "" } {
+            set gif 0
+        }
     }
     foreach layer [[ord::get_db_tech] getLayers] {
         if { [$layer getRoutingLevel] == 0 } {
@@ -160,8 +160,12 @@ proc sc_image_irdrop { net corner } {
             gui::delete_label $label
         }
     }
-    if { $gif } {
-        save_animated_gif -end
+    if { $gif >= 0 } {
+        if { [sc_check_version 26866] } {
+            save_animated_gif -end -key $gif
+        } else {
+            save_animated_gif -end
+        }
     }
 }
 
@@ -176,7 +180,7 @@ proc sc_image_routing_congestion { } {
         "Routing" \
         "routing_congestion.png" \
         "routing congestion" \
-        0 \
+        -1 \
         0
 }
 
@@ -194,7 +198,7 @@ proc sc_image_estimated_routing_congestion { } {
             "RUDY" \
             "estimated_routing_congestion.png" \
             "estimated routing congestion" \
-            0 \
+            -1 \
             0
     } err
     unsuppress_message GRT 10
@@ -342,7 +346,7 @@ proc sc_image_timing_histograms { } {
 
     if { [sc_cfg_tool_task_check_in_list setup var reports] } {
         set path reports/images/timing/setup.histogram.png
-        utl::info FLW 1 "Saving setup timing histogram to $path"
+        utl::info FLW 1 "Saving \"setup timing histogram\" to $path"
         save_histogram_image $path \
             -mode setup \
             -width 500 \
@@ -350,7 +354,7 @@ proc sc_image_timing_histograms { } {
     }
     if { [sc_cfg_tool_task_check_in_list hold var reports] } {
         set path reports/images/timing/hold.histogram.png
-        utl::info FLW 1 "Saving hold timing histogram to $path"
+        utl::info FLW 1 "Saving \"hold timing histogram\" to $path"
         save_histogram_image $path \
             -mode hold \
             -width 500 \

siliconcompiler/tools/openroad/scripts/rcx/sc_rcx_bench.tcl

@@ -1,10 +1,8 @@
 #https://github.com/The-OpenROAD-Project/OpenROAD/blob/9b52b1d9cfb532f9872739ffe482afb5ac9def92/src/rcx/calibration/script/generate_rules.tcl
 
-set openroad_bench_length \
-    [lindex [sc_cfg_tool_task_get {var} bench_length] 0]
+set openroad_bench_length [sc_cfg_tool_task_get {var} bench_length]
 
-set sc_maxmetal \
-    [sc_get_layer_name [lindex [sc_cfg_tool_task_get {var} max_layer] 0]]
+set sc_maxmetal [sc_get_layer_name [sc_cfg_tool_task_get {var} max_layer]]
 set openroad_top_metal_number [[[ord::get_db_tech] findLayer $sc_maxmetal] getRoutingLevel]
 
 # Creates the patterns and

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -149,5 +149,7 @@ utl::pop_metrics_stage
 ###############################
 
 utl::push_metrics_stage "sc__write__{}"
-source "$sc_refdir/common/write_data_physical.tcl"
+write_db "outputs/${sc_topmodule}.odb"
+write_def "outputs/${sc_topmodule}.def"
+write_verilog -include_pwr_gnd "outputs/${sc_topmodule}.vg"
 utl::pop_metrics_stage

siliconcompiler/tools/openroad/write_data.py

@@ -74,10 +74,10 @@ class WriteViewsTask(APRTask, OpenROADSTAParameter, OpenROADPSMParameter):
             for corner in self.get("var", "pex_corners"):
                 self.add_output_file(ext=f"{corner}.spef")
         if self.get("var", "write_liberty"):
-            for corner in self.project.getkeys("constraint", "timing"):
+            for corner in self.project.getkeys("constraint", "timing", "scenario"):
                 self.add_output_file(ext=f"{corner}.lib")
         if self.get("var", "write_sdf"):
-            for corner in self.project.getkeys("constraint", "timing"):
+            for corner in self.project.getkeys("constraint", "timing", "scenario"):
                 self.add_output_file(ext=f"{corner}.sdf")
 
         self.add_required_key("var", "ord_abstract_lef_bloat_layers")

siliconcompiler/tools/opensta/__init__.py

@@ -37,7 +37,7 @@ class OpenSTATask(Task):
         self.set_threads()
 
         self.add_regex("warnings", r'^\[WARNING|^Warning')
-        self.add_regex("errors", r'^\[ERROR')
+        self.add_regex("errors", r'^\[ERROR|^Error')
 
     def runtime_options(self):
         options = super().runtime_options()

siliconcompiler/tools/opensta/scripts/sc_check_library.tcl

@@ -22,7 +22,7 @@ set sc_design [sc_top]
 # APR Parameters
 set sc_targetlibs [sc_get_asic_libraries logic]
 set sc_delaymodel [sc_cfg_get asic delaymodel]
-set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing scenario]]
 
 ###############################
 # Optional
@@ -41,7 +41,7 @@ define_corners {*}$sc_scenarios
 foreach lib "$sc_targetlibs $sc_macrolibs" {
     #Liberty
     foreach corner $sc_scenarios {
-        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+        foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
             if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
                 foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
                     puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"

siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl

@@ -22,7 +22,7 @@ set sc_design [sc_top]
 # APR Parameters
 set sc_targetlibs [sc_get_asic_libraries logic]
 set sc_delaymodel [sc_cfg_get asic delaymodel]
-set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing scenario]]
 
 ###############################
 # Optional
@@ -41,7 +41,7 @@ define_corners {*}$sc_scenarios
 foreach lib "$sc_targetlibs $sc_macrolibs" {
     #Liberty
     foreach corner $sc_scenarios {
-        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+        foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
             if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
                 foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
                     puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -12,7 +12,7 @@ set sc_topmodulelib [sc_cfg_get option design]
 set sc_filesets [sc_cfg_get option fileset]
 
 # APR Parameters
-set sc_timing_mode [lindex [sc_cfg_tool_task_get var timing_mode] 0]
+set sc_timing_mode [sc_cfg_tool_task_get var timing_mode]
 
 set sc_mainlib []
 set sc_logiclibs []
@@ -23,8 +23,11 @@ if { $opensta_timing_mode == "asic" } {
     set sc_logiclibs [sc_cfg_get asic asiclib]
     set sc_delaymodel [sc_cfg_get asic delaymodel]
 
-    foreach corner [dict keys [sc_cfg_get constraint timing]] {
-        if { [sc_cfg_get constraint timing $corner mode] == $sc_timing_mode } {
+    foreach corner [dict keys [sc_cfg_get constraint timing scenario]] {
+        if {
+            $sc_timing_mode == {} ||
+            [sc_cfg_get constraint timing scenario $corner mode] == $sc_timing_mode
+        } {
             lappend sc_scenarios $corner
         }
     }
@@ -53,7 +56,7 @@ if { $opensta_timing_mode == "asic" } {
     foreach corner $sc_scenarios {
         foreach lib $sc_logiclibs {
             set lib_filesets []
-            foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+            foreach libcorner [sc_cfg_get constraint timing scenario $corner libcorner] {
                 if {
                     [sc_cfg_exists library $lib asic \
                         libcornerfileset $libcorner $sc_delaymodel]
@@ -111,8 +114,8 @@ if { [file exists "inputs/${sc_topmodule}.sdc"] } {
         lappend sdc_files $sdc
     }
 
-    set sdcfileset [sc_cfg_get constraint timing $corner sdcfileset]
-    foreach corner $sc_scenarios {
+    if { $sc_timing_mode != {} } {
+        set sdcfileset [sc_cfg_get constraint timing mode $sc_timing_mode sdcfileset]
         foreach sdc [sc_cfg_get_fileset $sc_topmodulelib $sdcfileset sdc] {
             if { [lsearch -exact $sdc_files $sdc] == -1 } {
                 # read step constraint if exists
@@ -137,7 +140,7 @@ if { [llength [sta::path_group_names]] == 0 } {
 
     if {
         [llength [all_clocks]] == 1 ||
-        [lindex [sc_cfg_tool_task_get var unique_path_groups_per_clock] 0] == "false"
+        ![sc_cfg_tool_task_get var unique_path_groups_per_clock]
     } {
         sc_path_group -name in2reg -from [all_inputs -no_clocks] -to [all_registers]
         sc_path_group -name reg2reg -from [all_registers] -to [all_registers]
@@ -163,7 +166,7 @@ puts "Timing path groups: [sta::path_group_names]"
 
 if { $opensta_timing_mode == "asic" } {
     foreach corner $sc_scenarios {
-        set pex_corner [sc_cfg_get constraint timing $corner pexcorner]
+        set pex_corner [sc_cfg_get constraint timing scenario $corner pexcorner]
 
         set spef_file "inputs/${sc_topmodule}.${pex_corner}.spef"
         if { [file exists $spef_file] } {
@@ -173,7 +176,7 @@ if { $opensta_timing_mode == "asic" } {
     }
 
     foreach corner $sc_scenarios {
-        set pex_corner [sc_cfg_get constraint timing $corner pexcorner]
+        set pex_corner [sc_cfg_get constraint timing scenario $corner pexcorner]
 
         set input_sdf_file "inputs/${sc_topmodule}.${pex_corner}.sdf"
         if { [file exists $input_sdf_file] } {
@@ -195,7 +198,7 @@ if { $opensta_timing_mode == "asic" } {
 # Report Metrics
 ###############################
 
-set opensta_top_n_paths [lindex [sc_cfg_tool_task_get var top_n_paths] 0]
+set opensta_top_n_paths [sc_cfg_tool_task_get var top_n_paths]
 
 set fields "{capacitance slew input_pins hierarcial_pins net fanout}"
 set PREFIX "SC_METRIC:"

siliconcompiler/tools/opensta/timing.py

@@ -2,6 +2,8 @@ import re
 
 import os.path
 
+from typing import Optional
+
 from siliconcompiler import sc_open
 
 from siliconcompiler.tools.opensta import OpenSTATask
@@ -27,7 +29,7 @@ class TimingTaskBase(OpenSTATask):
                            defvalue="tools/_common/sdc/sc_constraints.sdc",
                            dataroot="siliconcompiler")
 
-    def set_timing_mode(self, mode: str, step: str = None, index: str = None):
+    def set_timing_mode(self, mode: str, step: Optional[str] = None, index: Optional[str] = None):
         return self.set("var", "timing_mode", mode, step=step, index=index)
 
     def setup(self):
@@ -40,6 +42,8 @@ class TimingTaskBase(OpenSTATask):
 
         if self.get("var", "timing_mode"):
             self.add_required_key("var", "timing_mode")
+            if self.get("var", "timing_mode") not in self.project.constraint.timing.get_modes():
+                raise LookupError(f'{self.get("var", "timing_mode")} is not a defined mode')
         self.add_required_key("var", "top_n_paths")
         self.add_required_key("var", "unique_path_groups_per_clock")
         self.add_required_key("var", "opensta_generic_sdc")
@@ -149,7 +153,7 @@ class TimingTaskBase(OpenSTATask):
             self.record_metric("drvs", drv_count, source_file=[drv_report])
 
     def __report_map(self, metric):
-        corners = self.project.getkeys('constraint', 'timing')
+        corners = self.project.getkeys('constraint', 'timing', 'scenario')
         mapping = {
             "power": [f"reports/power.{corner}.rpt" for corner in corners],
             "unconstrained": ["reports/unconstrained.rpt", "reports/unconstrained.topN.rpt"],

siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl

@@ -1,2 +1,13 @@
 open_checkpoint "inputs/${sc_topmodule}.dcp"
+
+foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+    puts "Sourcing pre script: ${sc_pre_script}"
+    source $sc_pre_script
+}
+
 write_bitstream -force -file "outputs/${sc_topmodule}.bit"
+
+foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+    puts "Sourcing post script: ${sc_post_script}"
+    source $sc_post_script
+}

siliconcompiler/tools/vivado/scripts/sc_place.tcl

@@ -1,2 +1,13 @@
 open_checkpoint "inputs/${sc_topmodule}.dcp"
+
+foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+    puts "Sourcing pre script: ${sc_pre_script}"
+    source $sc_pre_script
+}
+
 place_design
+
+foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+    puts "Sourcing post script: ${sc_post_script}"
+    source $sc_post_script
+}

siliconcompiler/tools/vivado/scripts/sc_route.tcl

@@ -1,4 +1,15 @@
 open_checkpoint "inputs/${sc_topmodule}.dcp"
+
+foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+    puts "Sourcing pre script: ${sc_pre_script}"
+    source $sc_pre_script
+}
+
 phys_opt_design
 power_opt_design
 route_design
+
+foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+    puts "Sourcing post script: ${sc_post_script}"
+    source $sc_post_script
+}

siliconcompiler/tools/vivado/scripts/sc_syn_fpga.tcl

@@ -3,6 +3,11 @@ create_project $sc_topmodule -force
 set_property part $sc_partname [current_project]
 set_property target_language Verilog [current_project]
 
+foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+    puts "Sourcing pre script: ${sc_pre_script}"
+    source $sc_pre_script
+}
+
 # add imported files
 if { [string equal [get_filesets -quiet sources_1] ""] } {
     create_fileset -srcset sources_1
@@ -28,3 +33,8 @@ if { $synth_mode != "none" } {
 synth_design -top $sc_topmodule {*}$synth_args
 
 opt_design
+
+foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+    puts "Sourcing post script: ${sc_post_script}"
+    source $sc_post_script
+}

siliconcompiler/tools/vpr/__init__.py

@@ -272,8 +272,17 @@ class VPRTask(Task):
             if lib.has_file(fileset=fileset, filetype="sdc"):
                 self.add_required_key(lib, "fileset", fileset, "file", "sdc")
                 self.set("var", "enable_timing_analysis", True)
+
+        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        self.add_required_key(fpga, "tool", "vpr", "devicecode")
+        self.add_required_key(fpga, "tool", "vpr", "clock_model")
+        self.add_required_key(fpga, "tool", "vpr", "archfile")
+        self.add_required_key(fpga, "tool", "vpr", "graphfile")
+        self.add_required_key(fpga, "tool", "vpr", "channelwidth")
         if self.get("var", "router_lookahead"):
             self.add_required_key("var", "router_lookahead")
+        else:
+            self.add_required_key(fpga, "tool", "vpr", "router_lookahead")
 
     def runtime_options(self):
         options = super().runtime_options()
@@ -520,3 +529,22 @@ class VPRTask(Task):
                 if path.match(line):
                     count += 1
         return count
+
+    @classmethod
+    def make_docs(cls):
+        from siliconcompiler import Flowgraph, Design, FPGA
+        from siliconcompiler.scheduler import SchedulerNode
+        from siliconcompiler.demos.fpga_demo import Z1000
+        design = Design("<design>")
+        with design.active_fileset("docs"):
+            design.set_topmodule("top")
+        proj = FPGA(design)
+        proj.add_fileset("docs")
+        proj.set_fpga(Z1000())
+        flow = Flowgraph("docsflow")
+        flow.node("<step>", cls(), index="<index>")
+        proj.set_flow(flow)
+
+        node = SchedulerNode(proj, "<step>", "<index>")
+        node.setup()
+        return node.task

siliconcompiler/tools/yosys/scripts/sc_screenshot.tcl

@@ -43,7 +43,7 @@ if { [file exists "inputs/$sc_design.v"] } {
     set file_type "vg"
 } elseif { [sc_cfg_tool_task_exists var show_filepath] } {
     yosys read_verilog -noblackbox -sv [sc_cfg_tool_task_get var show_filepath]
-    set file_type [lindex [sc_cfg_tool_task_get var show_filetype] 0]
+    set file_type [sc_cfg_tool_task_get var show_filetype]
 }
 
 ########################################################

siliconcompiler/tools/yosys/scripts/sc_synth_asic.tcl

@@ -80,7 +80,16 @@ if { ![file exists $input_verilog] } {
     }
 }
 
-if { [sc_cfg_tool_task_get var use_slang] && [sc_load_plugin slang] } {
+set use_slang false
+if { [sc_cfg_tool_task_get var use_slang] } {
+    if { ![sc_load_plugin slang] } {
+        puts "WARNING: Unable to load slang plugin reverting back to yosys read_verilog"
+    } else {
+        set use_slang true
+    }
+}
+
+if { $use_slang } {
     # This needs some reordering of loaded to ensure blackboxes are handled
     # before this
     set slang_params []
@@ -90,6 +99,7 @@ if { [sc_cfg_tool_task_get var use_slang] && [sc_load_plugin slang] } {
             lappend slang_params -G "${key}=${value}"
         }
     }
+    yosys slang_version
     yosys read_slang \
         -D SYNTHESIS \
         --keep-hierarchy \
@@ -272,7 +282,29 @@ if { !$flatten_design && [sc_cfg_tool_task_get var auto_flatten] } {
 }
 
 # Finish synthesis
-yosys synth {*}$synth_args -top $sc_topmodule -run fine:check
+# Unroll of synth -run fine:check
+set opt_args []
+if { [sc_cfg_tool_task_get var opt_undriven] } {
+    lappend opt_args -undriven
+}
+yosys opt -fast -mux_undef -mux_bool -fine {*}$opt_args
+yosys memory_map
+yosys opt -mux_undef -mux_bool -fine {*}$opt_args
+
+set tech_map_args []
+lappend tech_map_args "-map" "+/techmap.v"
+foreach extra_map [sc_cfg_tool_task_get var synth_extra_map] {
+    lappend tech_map_args "-map" $extra_map
+}
+yosys techmap {*}$tech_map_args
+
+yosys opt -fast
+yosys abc -fast
+yosys opt -fast
+
+yosys hierarchy -check
+yosys stat
+yosys check
 
 # Logic locking
 if { [sc_cfg_tool_task_get var lock_design] } {
@@ -440,7 +472,11 @@ yosys clean -purge
 # Recheck hierarchy to remove all unused modules
 yosys hierarchy -top $sc_topmodule
 
-yosys setundef -zero
+if { [sc_cfg_tool_task_get var tie_undef] == "high" } {
+    yosys setundef -one
+} elseif { [sc_cfg_tool_task_get var tie_undef] == "low" } {
+    yosys setundef -zero
+}
 
 yosys splitnets
 
@@ -453,7 +489,7 @@ if { [sc_has_tie_cell low] } {
 if { [sc_has_tie_cell high] } {
     lappend yosys_hilomap_args -hicell {*}[sc_get_tie_cell high]
 }
-if { [llength $yosys_hilomap_args] != 0 } {
+if { [sc_cfg_tool_task_get var add_tieoffs] && [llength $yosys_hilomap_args] != 0 } {
     yosys hilomap -singleton {*}$yosys_hilomap_args
 }
 

siliconcompiler/tools/yosys/scripts/sc_synth_fpga.tcl

@@ -30,7 +30,16 @@ if { ![file exists $input_verilog] } {
     set input_verilog "inputs/$sc_topmodule.sv"
 }
 
-if { [sc_cfg_tool_task_get var use_slang] && [sc_load_plugin slang] } {
+set use_slang false
+if { [sc_cfg_tool_task_get var use_slang] } {
+    if { ![sc_load_plugin slang] } {
+        puts "WARNING: Unable to load slang plugin reverting back to yosys read_verilog"
+    } else {
+        set use_slang true
+    }
+}
+
+if { $use_slang } {
     # This needs some reordering of loaded to ensure blackboxes are handled
     # before this
     set slang_params []
@@ -40,6 +49,7 @@ if { [sc_cfg_tool_task_get var use_slang] && [sc_load_plugin slang] } {
             lappend slang_params -G "${key}=${value}"
         }
     }
+    yosys slang_version
     yosys read_slang \
         -D SYNTHESIS \
         --keep-hierarchy \
@@ -73,9 +83,7 @@ set sc_syn_lut_size [sc_cfg_get library $sc_designlib fpga lutsize]
 # comment in syn_asic.tcl for longer explanation.
 yosys hierarchy -top $sc_topmodule
 
-if { [string match {ice*} $sc_partname] } {
-    yosys synth_ice40 -top $sc_topmodule
-} elseif {
+if {
     [sc_cfg_exists library $sc_designlib tool yosys fpga_config] &&
     [sc_cfg_get library $sc_designlib tool yosys fpga_config] != {} &&
     [sc_load_plugin wildebeest]
@@ -83,7 +91,7 @@ if { [string match {ice*} $sc_partname] } {
     set synth_fpga_args []
     if { [sc_cfg_tool_task_get var synth_opt_mode] != "none" } {
         lappend synth_fpga_args \
-            -opt [lindex [sc_cfg_tool_task_get var synth_opt_mode] 0]
+            -opt [sc_cfg_tool_task_get var synth_opt_mode]
     }
     if { [sc_cfg_tool_task_get var synth_insert_buffers] } {
         lappend synth_fpga_args -insbuf
@@ -94,6 +102,8 @@ if { [string match {ice*} $sc_partname] } {
         -show_config \
         -top $sc_topmodule \
         {*}$synth_fpga_args
+} elseif { [string match {ice*} $sc_partname] } {
+    yosys synth_ice40 -top $sc_topmodule
 } else {
     set sc_syn_feature_set [sc_cfg_get library $sc_designlib tool yosys feature_set]
 

siliconcompiler/tools/yosys/syn_asic.py

@@ -2,6 +2,8 @@ import json
 
 import os.path
 
+from typing import Optional
+
 from siliconcompiler.tools.yosys.prepareLib import process_liberty_file
 from siliconcompiler import sc_open
 from siliconcompiler import utils
@@ -177,6 +179,21 @@ class ASICSynthesis(_ASICTask, YosysTask):
             "bool",
             "true/false, flag to indicate whether to add buffers or not.",
             True)
+        self.add_parameter(
+            "tie_undef",
+            "<high,low,none>",
+            "Flag to indicate how to handle undefined signals in netlist",
+            "low")
+        self.add_parameter(
+            "add_tieoffs",
+            "bool",
+            "true/false, flag to indicate add tie high and tie low cells.",
+            True)
+        self.add_parameter(
+            "opt_undriven",
+            "bool",
+            "true/false, flag to indicate if optimizations should mark undriven nets",
+            True)
 
         self.__init_techmapping_parameter()
         self.__init_hierarchy_parameter()
@@ -297,6 +314,26 @@ class ASICSynthesis(_ASICTask, YosysTask):
             "str",
             "lock locking port name")
 
+    def set_yosys_useslang(self, enable: bool,
+                           step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "use_slang", enable, step=step, index=index)
+
+    def set_yosys_tieundefined(self, tie: str,
+                               step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "tie_undef", tie, step=step, index=index)
+
+    def set_yosys_addtiecells(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "add_tieoffs", enable, step=step, index=index)
+
+    def set_yosys_addbuffers(self, enable: bool,
+                             step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "add_buffers", enable, step=step, index=index)
+
+    def set_yosys_optundriven(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "opt_undriven", enable, step=step, index=index)
+
     def task(self):
         return "syn_asic"
 
@@ -374,6 +411,11 @@ class ASICSynthesis(_ASICTask, YosysTask):
         if self.get("var", "blackbox_modules"):
             self.add_required_key("var", "blackbox_modules")
 
+        self.add_required_key("var", "use_slang")
+        self.add_required_key("var", "add_buffers")
+        self.add_required_key("var", "tie_undef")
+        self.add_required_key("var", "add_tieoffs")
+        self.add_required_key("var", "opt_undriven")
         self.add_required_key("var", "flatten")
         self.add_required_key("var", "auto_flatten")
         self.add_required_key("var", "hier_threshold")

siliconcompiler/tools/yosys/syn_fpga.py

@@ -1,5 +1,7 @@
 import json
 
+from typing import Optional
+
 from siliconcompiler import sc_open
 
 from siliconcompiler.tools.yosys import YosysTask
@@ -26,6 +28,10 @@ class FPGASynthesis(YosysTask):
             "perform buffer insertion",
             True)
 
+    def set_yosys_useslang(self, enable: bool,
+                           step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "use_slang", enable, step=step, index=index)
+
     def task(self):
         return "syn_fpga"
 
@@ -53,6 +59,8 @@ class FPGASynthesis(YosysTask):
         self.add_output_file(ext="netlist.json")
         self.add_output_file(ext="blif")
 
+        self.add_required_key("var", "use_slang")
+
     def post_process(self):
         super().post_process()