siliconcompiler 0.34.0__py3-none-any.whl → 0.34.2__py3-none-any.whl

siliconcompiler/tools/yosys/scripts/procs.tcl

@@ -0,0 +1,143 @@
+# This file contains a set of procedures that are shared
+# between syn_asic.tcl and syn_fpga.tcl
+
+proc post_techmap { { opt_args "" } } {
+    # perform techmap in case previous techmaps introduced constructs
+    # that need techmapping
+    yosys techmap
+    # Quick optimization
+    yosys opt {*}$opt_args -purge
+}
+
+proc sc_map_memory { lib_file techmap_file do_rom } {
+    set design_mod 0
+
+    if { $lib_file != "" } {
+        yosys memory_libmap -lib $lib_file
+        set design_mod 1
+    }
+
+    if { $do_rom } {
+        yosys memory_map -rom-only
+        set design_mod 1
+    }
+
+    if { $techmap_file != "" } {
+        yosys techmap -map $techmap_file
+        set design_mod 1
+    }
+
+    return $design_mod
+}
+
+proc sc_apply_params { } {
+    global sc_design
+
+    yosys chparam -list $sc_design
+    if { [sc_cfg_exists option param] } {
+        yosys echo off
+        set module_params [yosys tee -q -s result.string chparam -list $sc_design]
+        yosys echo on
+
+        dict for {key value} [sc_cfg_get option param] {
+            if { ![string is integer $value] } {
+                set value [concat \"$value\"]
+            }
+
+            if { [string first $key $module_params] != -1 } {
+                yosys chparam -set $key $value $sc_design
+            } else {
+                puts "Warning: $key is not a defined parameter in $sc_design"
+            }
+        }
+    }
+}
+
+proc sc_get_scratchpad { name } {
+    yosys echo off
+    set value [yosys tee -q -s result.string scratchpad -get $name]
+    yosys echo on
+
+    return $value
+}
+
+proc sc_load_plugin { name } {
+    catch { yosys tee -q -s sc.load.test plugin -i $name }
+    set load_test [sc_get_scratchpad sc.load.test]
+    if { [string first "ERROR" $load_test] == -1 } {
+        return 1
+    }
+    return 0
+}
+
+proc sc_fpga_legalize_flops { feature_set } {
+    set legalize_flop_types []
+
+    if {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_set] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN?_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_PN?P_
+        lappend legalize_flop_types \$_DFFSR_PNN_
+        lappend legalize_flop_types \$_DFFSRE_PNNP_
+    } elseif {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_set] >= 0
+    } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN1_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_PN1P_
+    } elseif {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN0_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_PN0P_
+    } elseif { [lsearch -exact $feature_set enable] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_P??_
+        lappend legalize_flop_types \$_DFFE_PP_
+        lappend legalize_flop_types \$_DFFE_P??P_
+    } elseif {
+        [lsearch -exact $feature_set async_set] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN?_
+        lappend legalize_flop_types \$_DFFSR_PNN_
+    } elseif { [lsearch -exact $feature_set async_set] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN1_
+    } elseif { [lsearch -exact $feature_set async_reset] >= 0 } {
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_PN0_
+    } else {
+        # Choose to legalize to async resets even though they
+        # won't tech map.  Goal is to get the user to fix
+        # their code and put in synchronous resets
+        lappend legalize_flop_types \$_DFF_P_
+        lappend legalize_flop_types \$_DFF_P??_
+    }
+
+    set legalize_list []
+    foreach flop_type $legalize_flop_types {
+        lappend legalize_list -cell $flop_type 01
+    }
+    yosys log "Legalize list: $legalize_list"
+    yosys dfflegalize {*}$legalize_list
+}
+
+proc sc_fpga_get_dsp_options { sc_syn_dsp_options } {
+    set option_text [list]
+    foreach dsp_option $sc_syn_dsp_options {
+        lappend option_text -D $dsp_option
+    }
+    return $option_text
+}

siliconcompiler/tools/yosys/{sc_synth_asic.tcl → scripts/sc_synth_asic.tcl}

@@ -507,6 +507,10 @@ yosys abc {*}$abc_args {*}$abc_dont_use
 ########################################################
 
 yosys clean -purge
+
+# Recheck hierarchy to remove all unused modules
+yosys hierarchy -top $sc_design
+
 yosys setundef -zero
 
 yosys splitnets

siliconcompiler/tools/yosys/{sc_synth_fpga.tcl → scripts/sc_synth_fpga.tcl}

@@ -57,9 +57,12 @@ if { [file exists $input_verilog] } {
         yosys read_slang \
             -D SYNTHESIS \
             --keep-hierarchy \
+            --ignore-assertions \
+            --allow-use-before-declare \
             --top $sc_design \
             {*}$slang_params \
             $input_verilog
+        yosys setattr -unset init
     } else {
         # Use -noblackbox to correctly interpret empty modules as empty,
         # actual black boxes are read in later
@@ -74,81 +77,6 @@ if { [file exists $input_verilog] } {
     }
 }
 
-####################
-# Helper functions
-####################
-proc legalize_flops { feature_set } {
-    set legalize_flop_types []
-
-    if {
-        [lsearch -exact $feature_set enable] >= 0 &&
-        [lsearch -exact $feature_set async_set] >= 0 &&
-        [lsearch -exact $feature_set async_reset] >= 0
-    } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN?_
-        lappend legalize_flop_types \$_DFFE_PP_
-        lappend legalize_flop_types \$_DFFE_PN?P_
-        lappend legalize_flop_types \$_DFFSR_PNN_
-        lappend legalize_flop_types \$_DFFSRE_PNNP_
-    } elseif {
-        [lsearch -exact $feature_set enable] >= 0 &&
-        [lsearch -exact $feature_set async_set] >= 0
-    } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN1_
-        lappend legalize_flop_types \$_DFFE_PP_
-        lappend legalize_flop_types \$_DFFE_PN1P_
-    } elseif {
-        [lsearch -exact $feature_set enable] >= 0 &&
-        [lsearch -exact $feature_set async_reset] >= 0
-    } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN0_
-        lappend legalize_flop_types \$_DFFE_PP_
-        lappend legalize_flop_types \$_DFFE_PN0P_
-    } elseif { [lsearch -exact $feature_set enable] >= 0 } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_P??_
-        lappend legalize_flop_types \$_DFFE_PP_
-        lappend legalize_flop_types \$_DFFE_P??P_
-    } elseif {
-        [lsearch -exact $feature_set async_set] >= 0 &&
-        [lsearch -exact $feature_set async_reset] >= 0
-    } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN?_
-        lappend legalize_flop_types \$_DFFSR_PNN_
-    } elseif { [lsearch -exact $feature_set async_set] >= 0 } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN1_
-    } elseif { [lsearch -exact $feature_set async_reset] >= 0 } {
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_PN0_
-    } else {
-        # Choose to legalize to async resets even though they
-        # won't tech map.  Goal is to get the user to fix
-        # their code and put in synchronous resets
-        lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_P??_
-    }
-
-    set legalize_list []
-    foreach flop_type $legalize_flop_types {
-        lappend legalize_list -cell $flop_type 01
-    }
-    yosys log "Legalize list: $legalize_list"
-    yosys dfflegalize {*}$legalize_list
-}
-
-proc get_dsp_options { sc_syn_dsp_options } {
-    set option_text [list]
-    foreach dsp_option $sc_syn_dsp_options {
-        lappend option_text -D $dsp_option
-    }
-    return $option_text
-}
-
 set sc_partname [sc_cfg_get fpga partname]
 set build_dir [sc_cfg_get option builddir]
 set job_name [sc_cfg_get option jobname]
@@ -182,6 +110,25 @@ yosys hierarchy -top $sc_design
 
 if { [string match {ice*} $sc_partname] } {
     yosys synth_ice40 -top $sc_design -json "${sc_design}.netlist.json"
+} elseif {
+    [sc_cfg_exists fpga $sc_partname file yosys_fpga_config] &&
+    [llength [sc_cfg_get fpga $sc_partname file yosys_fpga_config]] != 0 &&
+    [sc_load_plugin yosys-syn]
+} {
+    set synth_fpga_args []
+    if { [lindex [sc_cfg_tool_task_get var synth_fpga_opt_mode] 0] != "none" } {
+        lappend synth_fpga_args \
+            -opt [lindex [sc_cfg_tool_task_get var synth_fpga_opt_mode] 0]
+    }
+    if { [lindex [sc_cfg_tool_task_get var synth_fpga_insert_buffers] 0] == "true" } {
+        lappend synth_fpga_args -insbuf
+    }
+
+    yosys synth_fpga \
+        -config [lindex [sc_cfg_get fpga $sc_partname file yosys_fpga_config] 0] \
+        -show_config \
+        -top $sc_design \
+        {*}$synth_fpga_args
 } else {
     # Pre-processing step:  if DSPs instance are hard-coded into
     # the user's design, we can use a blackbox flow for DSP mapping
@@ -252,7 +199,7 @@ if { [string match {ice*} $sc_partname] } {
             [sc_cfg_get fpga $sc_partname file yosys_dsp_techmap]
 
         yosys log "Run techmap flow for DSP Blocks"
-        set formatted_dsp_options [get_dsp_options $sc_syn_dsp_options]
+        set formatted_dsp_options [sc_fpga_get_dsp_options $sc_syn_dsp_options]
         yosys techmap -map +/mul2dsp.v -map $sc_syn_dsp_library \
             {*}$formatted_dsp_options
 
@@ -290,7 +237,7 @@ if { [string match {ice*} $sc_partname] } {
     yosys demuxmap
     yosys simplemap
 
-    legalize_flops $sc_syn_feature_set
+    sc_fpga_legalize_flops $sc_syn_feature_set
 
     if { [sc_cfg_exists fpga $sc_partname file yosys_flop_techmap] } {
         set sc_syn_flop_library \

siliconcompiler/tools/yosys/syn_fpga.py

@@ -43,6 +43,20 @@ def setup(chip):
              'true/false, if true will attempt to use the slang frontend',
              field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'synth_fpga_opt_mode', 'none',
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'synth_fpga_opt_mode',
+             'optimization mode for the synth_fpga command',
+             field='help')
+
+    chip.set('tool', tool, 'task', task, 'var', 'synth_fpga_insert_buffers', True,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'synth_fpga_insert_buffers',
+             'insert buffers as part of the synth_fpga command',
+             field='help')
+
     # Setup FPGA params
     part_name = chip.get('fpga', 'partname')
 

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "4b729ea474e9bd0a3513579b41a8c96fe20dc75e",
+    "git-commit": "e4f795a39cceb3608a6e755000253af491a69a3f",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "343b93b6336962b2dbcc5b7c7500c01df0367696",
+    "git-commit": "4a32cef237d1feed335e3c6328b5b1f3794909fc",
     "auto-update": true
   },
   "netgen": {
@@ -55,7 +55,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "380c2b978a54e459ac216c9e6b7f1a4e31573a0e",
+    "git-commit": "80a2f0cf685f6d873b4ee37b76e6c18dc60e2555",
     "auto-update": true
   },
   "verilator": {
@@ -76,7 +76,7 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
+    "git-commit": "4bb340af8243b95efdea493d4cb58aed1099151f",
     "auto-update": false
   },
   "icepack": {
@@ -101,7 +101,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.54",
+    "git-commit": "v0.55",
     "version-prefix": "",
     "auto-update": true
   },
@@ -151,7 +151,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "e863336db656b1f0ec82f7af65249b6a4ee3e56c",
+    "git-commit": "f106ae3a68155ee470d51b168c72282a1453171b",
     "docker-depends": "yosys",
     "auto-update": true
   },
@@ -161,13 +161,9 @@
     "docker-depends": "yosys",
     "auto-update": true
   },
-  "yosys-parmys": {
-    "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
-    "docker-depends": [
-      "yosys",
-      "vpr"
-    ],
+  "surfer": {
+    "git-url": "https://gitlab.com/surfer-project/surfer.git",
+    "git-commit": "v0.3.0",
     "auto-update": false
   }
 }

siliconcompiler/toolscripts/rhel9/install-vpr.sh

@@ -24,8 +24,6 @@ git submodule update --init --recursive
 
 sudo dnf config-manager --set-enabled devel || true
 ./install_dnf_packages.sh
-
-sudo yum install -y tbb-devel
 sudo dnf config-manager --set-disabled devel || true
 
 args=

siliconcompiler/toolscripts/ubuntu22/install-surfer.sh

@@ -0,0 +1,33 @@
+#!/bin/sh
+
+set -ex
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+sudo apt-get install -y build-essential curl git libssl-dev openssl pkg-config
+
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
+curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s - -y
+export PATH="$HOME/.cargo/bin:$PATH"
+
+git clone $(python3 ${src_path}/_tools.py --tool surfer --field git-url) surfer
+cd surfer
+git checkout $(python3 ${src_path}/_tools.py --tool surfer --field git-commit)
+git submodule update --init
+
+cargo fetch --locked
+cargo build -j $(nproc) --frozen --release
+
+if [ ! -z ${PREFIX} ]; then
+    $SUDO_INSTALL install -Dm00755 target/release/surfer -t ${PREFIX}/bin
+fi

siliconcompiler/toolscripts/ubuntu24/install-surfer.sh

@@ -0,0 +1,33 @@
+#!/bin/sh
+
+set -ex
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+sudo apt-get install -y build-essential curl git libssl-dev openssl pkg-config
+
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
+curl --proto '=https' --tlsv1.2 -sSf https://sh.rustup.rs | sh -s - -y
+export PATH="$HOME/.cargo/bin:$PATH"
+
+git clone $(python3 ${src_path}/_tools.py --tool surfer --field git-url) surfer
+cd surfer
+git checkout $(python3 ${src_path}/_tools.py --tool surfer --field git-commit)
+git submodule update --init
+
+cargo fetch --locked
+cargo build -j $(nproc) --frozen --release
+
+if [ ! -z ${PREFIX} ]; then
+    $SUDO_INSTALL install -Dm00755 target/release/surfer -t ${PREFIX}/bin
+fi

siliconcompiler/utils/__init__.py

@@ -221,7 +221,8 @@ def default_email_credentials_file():
 
 @contextlib.contextmanager
 def sc_open(path, *args, **kwargs):
-    kwargs['errors'] = 'ignore_with_warning'
+    if 'errors' not in kwargs:
+        kwargs['errors'] = 'ignore'
     fobj = open(path, *args, **kwargs)
     try:
         with contextlib.closing(fobj):

siliconcompiler/utils/flowgraph.py

@@ -16,16 +16,16 @@ def _check_flowgraph_io(chip, nodes=None):
     flow = chip.get('option', 'flow')
 
     runtime_full = RuntimeFlowgraph(
-        chip.schema.get("flowgraph", flow, field='schema'),
+        chip.get("flowgraph", flow, field='schema'),
         to_steps=chip.get('option', 'to'),
         prune_nodes=chip.get('option', 'prune'))
     runtime_flow = RuntimeFlowgraph(
-        chip.schema.get("flowgraph", flow, field='schema'),
+        chip.get("flowgraph", flow, field='schema'),
         args=(chip.get('arg', 'step'), chip.get('arg', 'index')),
         from_steps=chip.get('option', 'from'),
         to_steps=chip.get('option', 'to'),
         prune_nodes=chip.get('option', 'prune'))
-    record = chip.schema.get("record", field='schema')
+    record = chip.get("record", field='schema')
 
     if not nodes:
         nodes = runtime_flow.get_nodes()
@@ -62,25 +62,25 @@ def _check_flowgraph_io(chip, nodes=None):
                 manifest = f'{design}.pkg.json'
                 inputs = [inp for inp in os.listdir(in_step_out_dir) if inp != manifest]
             else:
-                in_tool, _ = get_tool_task(chip, in_step, in_index, flow=flow)
-                task_class = chip.get("tool", in_tool, field="schema")
-                task_class.set_runtime(chip, step=in_step, index=in_index)
+                in_tool, in_task = get_tool_task(chip, in_step, in_index, flow=flow)
+                task_class = chip.get("tool", in_tool, "task", in_task, field="schema")
 
-                inputs = task_class.get_output_files()
+                with task_class.runtime(chip, step=in_step, index=in_index) as task:
+                    inputs = task.get_output_files()
 
             for inp in inputs:
                 node_inp = input_file_node_name(inp, in_step, in_index)
                 if node_inp in requirements:
                     inp = node_inp
                 if inp in all_inputs:
-                    chip.logger.error(f'Invalid flow: {step}{index} '
+                    chip.logger.error(f'Invalid flow: {step}/{index} '
                                       f'receives {inp} from multiple input tasks')
                     return False
                 all_inputs.add(inp)
 
         for requirement in requirements:
             if requirement not in all_inputs:
-                chip.logger.error(f'Invalid flow: {step}{index} will '
+                chip.logger.error(f'Invalid flow: {step}/{index} will '
                                   f'not receive required input {requirement}.')
                 return False
 
@@ -95,7 +95,7 @@ def _get_flowgraph_information(chip, flow, io=True):
     chip.schema = chip.schema.copy()
 
     # Setup nodes
-    node_exec_order = chip.schema.get("flowgraph", flow, field="schema").get_execution_order()
+    node_exec_order = chip.get("flowgraph", flow, field="schema").get_execution_order()
     if io:
         prev_flow = chip.get("option", "flow")
         chip.set("option", "flow", flow)
@@ -107,12 +107,12 @@ def _get_flowgraph_information(chip, flow, io=True):
     node_rank = {}
     for rank, rank_nodes in enumerate(node_exec_order):
         for step, index in rank_nodes:
-            node_rank[f'{step}{index}'] = rank
+            node_rank[f'{step}/{index}'] = rank
 
     graph_inputs = {}
     all_graph_inputs = set()
     if io:
-        for step, index in chip.schema.get("flowgraph", flow, field="schema").get_nodes():
+        for step, index in chip.get("flowgraph", flow, field="schema").get_nodes():
             tool, task = get_tool_task(chip, step, index, flow=flow)
             for keypath in chip.get('tool', tool, 'task', task, 'require', step=step, index=index):
                 key = tuple(keypath.split(','))
@@ -122,7 +122,7 @@ def _get_flowgraph_information(chip, flow, io=True):
         for inputs in graph_inputs.values():
             all_graph_inputs.update(inputs)
 
-    exit_nodes = [f'{step}{index}' for step, index in chip.schema.get(
+    exit_nodes = [f'{step}/{index}' for step, index in chip.get(
         "flowgraph", flow, field="schema").get_exit_nodes()]
 
     nodes = {}
@@ -135,11 +135,11 @@ def _get_flowgraph_information(chip, flow, io=True):
         return label.replace("<", r"\<").replace(">", r"\>")
 
     all_nodes = [(step, index) for step, index in sorted(
-                    chip.schema.get("flowgraph", flow, field="schema").get_nodes())
+                    chip.get("flowgraph", flow, field="schema").get_nodes())
                  if chip.get('record', 'status', step=step, index=index) != NodeStatus.SKIPPED]
 
-    runtime_flow = RuntimeFlowgraph(chip.schema.get("flowgraph", flow, field='schema'))
-    record = chip.schema.get("record", field='schema')
+    runtime_flow = RuntimeFlowgraph(chip.get("flowgraph", flow, field='schema'))
+    record = chip.get("record", field='schema')
 
     for step, index in all_nodes:
         tool, task = get_tool_task(chip, step, index, flow=flow)
@@ -153,7 +153,7 @@ def _get_flowgraph_information(chip, flow, io=True):
             inputs = []
             outputs = []
 
-        node = f'{step}{index}'
+        node = f'{step}/{index}'
         if io and (step, index) in graph_inputs:
             inputs.extend(graph_inputs[(step, index)])
 
@@ -173,11 +173,12 @@ def _get_flowgraph_information(chip, flow, io=True):
 
         rank_diff = {}
         for in_step, in_index in runtime_flow.get_node_inputs(step, index, record=record):
-            rank_diff[f'{in_step}{in_index}'] = node_rank[node] - node_rank[f'{in_step}{in_index}']
+            in_node_name = f'{in_step}/{in_index}'
+            rank_diff[in_node_name] = node_rank[node] - node_rank[in_node_name]
         nodes[node]["rank_diff"] = rank_diff
 
     for step, index in all_nodes:
-        node = f'{step}{index}'
+        node = f'{step}/{index}'
         if io:
             # get inputs
             edge_stats = {}
@@ -189,9 +190,9 @@ def _get_flowgraph_information(chip, flow, io=True):
                         infile = input_file_node_name(infile, in_step, in_index)
                         if infile not in nodes[node]["file_inputs"]:
                             continue
-                    in_node_name = f"{in_step}{in_index}"
+                    in_node_name = f"{in_step}/{in_index}"
                     outlabel = f"{in_node_name}:output-{clean_label(outfile)}"
-                    inlabel = f"{step}{index}:input-{clean_label(infile)}"
+                    inlabel = f"{step}/{index}:input-{clean_label(infile)}"
 
                     if in_node_name not in edge_stats:
                         edge_stats[in_node_name] = {
@@ -229,12 +230,12 @@ def _get_flowgraph_information(chip, flow, io=True):
 
             if (step, index) in graph_inputs:
                 for key in graph_inputs[(step, index)]:
-                    inlabel = f"{step}{index}:input-{clean_label(key)}"
+                    inlabel = f"{step}/{index}:input-{clean_label(key)}"
                     edges.append((key, inlabel, 1))
         else:
             all_inputs = []
             for in_step, in_index in chip.get('flowgraph', flow, step, index, 'input'):
-                all_inputs.append(f'{in_step}{in_index}')
+                all_inputs.append(f'{in_step}/{in_index}')
             for item in all_inputs:
                 edges.append((item, node, 1 if node in exit_nodes else 2))