siliconcompiler 0.33.2__py3-none-any.whl → 0.34.0__py3-none-any.whl

siliconcompiler/tool.py

@@ -61,11 +61,35 @@ class TaskExecutableNotFound(TaskError):
 
 
 class TaskSchema(NamedSchema):
-    def __init__(self, name=None):
-        super().__init__(name=name)
+    def __init__(self, name):
+        super().__init__(name)
 
         schema_task(self)
 
+    def add_parameter(self, name, type, help, defvalue=None):
+        '''
+        Adds a parameter to the task definition.
+
+        Args:
+            name (str): name of parameter
+            type (str): schema type of the parameter
+            help (str): help string for this parameter
+            defvalue (any): default value for the parameter
+        '''
+        help = trim(help)
+        param = Parameter(
+            type,
+            defvalue=defvalue,
+            scope=Scope.JOB,
+            pernode=PerNode.OPTIONAL,
+            shorthelp=help,
+            help=help
+        )
+
+        EditableSchema(self).insert("var", name, param)
+
+        return param
+
 
 class ToolSchema(NamedSchema):
     __parse_version_check_str = r"""
@@ -83,13 +107,13 @@ class ToolSchema(NamedSchema):
         r"^\s*" + __parse_version_check_str + r"\s*$",
         re.VERBOSE | re.IGNORECASE)
 
-    def __init__(self, name=None):
-        super().__init__(name=name)
+    def __init__(self, name):
+        super().__init__(name)
 
         schema_tool(self)
 
         schema = EditableSchema(self)
-        schema.insert("task", "default", TaskSchema())
+        schema.insert("task", "default", TaskSchema(None))
 
         self.set_runtime(None)
 
@@ -359,13 +383,14 @@ class ToolSchema(NamedSchema):
                 envvars[lic_env] = ':'.join(license_file)
 
         if include_path:
-            path_param = self.get('path', field=None, step=self.__step, index=self.__index)
-            if path_param.get(field='package'):
-                raise NotImplementedError
+            path = self.find_files(
+                "path", step=self.__step, index=self.__index,
+                packages=self.__chip.get("package", field="schema").get_resolvers(),
+                cwd=self.__chip.cwd,
+                missing_ok=True)
 
             envvars["PATH"] = os.getenv("PATH", os.defpath)
 
-            path = path_param.get(field=None).resolve_path()  # TODO: needs package search
             if path:
                 envvars["PATH"] = path + os.pathsep + envvars["PATH"]
 
@@ -391,15 +416,6 @@ class ToolSchema(NamedSchema):
         '''
 
         cmdargs = []
-        cmdargs.extend(self.get('task', self.__task, 'option',
-                                step=self.__step, index=self.__index))
-
-        # Add scripts files / TODO:
-        scripts = self.__chip.find_files('tool', self.__tool, 'task', self.__task, 'script',
-                                         step=self.__step, index=self.__index)
-
-        cmdargs.extend(scripts)
-
         try:
             cmdargs.extend(self.runtime_options())
         except Exception as e:
@@ -826,7 +842,17 @@ class ToolSchema(NamedSchema):
         pass
 
     def runtime_options(self):
-        return []
+        cmdargs = []
+        cmdargs.extend(self.get('task', self.__task, 'option',
+                                step=self.__step, index=self.__index))
+
+        # Add scripts files / TODO:
+        scripts = self.__chip.find_files('tool', self.__tool, 'task', self.__task, 'script',
+                                         step=self.__step, index=self.__index)
+
+        cmdargs.extend(scripts)
+
+        return cmdargs
 
     def run(self):
         raise NotImplementedError("must be implemented by the implementation class")
@@ -839,6 +865,9 @@ class ToolSchema(NamedSchema):
 # Migration helper
 ###########################################################################
 class ToolSchemaTmp(ToolSchema):
+    def __init__(self):
+        super().__init__(None)
+
     def __module_func(self, name, modules):
         for module in modules:
             method = getattr(module, name, None)
@@ -874,6 +903,17 @@ class ToolSchemaTmp(ToolSchema):
             return method(version)
         return ToolSchema.normalize_version(self, version)
 
+    def generate_replay_script(self, filepath, workdir, include_path=True):
+        prev_step, prev_index = self._ToolSchema__chip.get('arg', 'step'), \
+            self._ToolSchema__chip.get('arg', 'index')
+        step, index = self.node()
+        self._ToolSchema__chip.set('arg', 'step', step)
+        self._ToolSchema__chip.set('arg', 'index', index)
+        ret = ToolSchema.generate_replay_script(self, filepath, workdir, include_path=include_path)
+        self._ToolSchema__chip.set('arg', 'step', prev_step)
+        self._ToolSchema__chip.set('arg', 'index', prev_index)
+        return ret
+
     def setup(self):
         _, task = self.__tool_task_modules()
         method = self.__module_func("setup", [task])
@@ -928,7 +968,8 @@ class ToolSchemaTmp(ToolSchema):
             step, index = self.node()
             self._ToolSchema__chip.set('arg', 'step', step)
             self._ToolSchema__chip.set('arg', 'index', index)
-            ret = method(self._ToolSchema__chip)
+            ret = ToolSchema.runtime_options(self)
+            ret.extend(method(self._ToolSchema__chip))
             self._ToolSchema__chip.set('arg', 'step', prev_step)
             self._ToolSchema__chip.set('arg', 'index', prev_index)
             return ret

siliconcompiler/tools/builtin/concatenate.py

@@ -3,7 +3,7 @@ import os
 from siliconcompiler import sc_open, SiliconCompilerError
 from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
-from siliconcompiler import scheduler
+from siliconcompiler.scheduler.schedulernode import SchedulerNode
 
 
 def make_docs(chip):
@@ -12,7 +12,7 @@ def make_docs(chip):
     chip.set('option', 'flow', 'asicflow')
 
     for step, index in chip.schema.get("flowgraph", "asicflow", field="schema").get_entry_nodes():
-        scheduler._setup_node(chip, step, index)
+        SchedulerNode(chip, step, index).setup()
 
     chip.set('arg', 'step', 'import.combine')
     chip.set('arg', 'index', '0')

siliconcompiler/tools/builtin/verify.py

@@ -1,6 +1,5 @@
 from siliconcompiler.tools.builtin import _common
 from siliconcompiler.schema.parametertype import NodeType
-from siliconcompiler.scheduler import _haltstep
 from siliconcompiler.tools.builtin.builtin import set_io_files
 from siliconcompiler import utils, SiliconCompilerError
 from siliconcompiler.tools._common import get_tool_task
@@ -59,7 +58,7 @@ def _select_inputs(chip, step, index):
             chip.error(f"{step}{index} fails '{metric}' metric: {value}{op}{goal}")
 
     if not passes:
-        _haltstep(chip, flow, step, index)
+        return []
 
     return inputs
 

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -634,36 +634,38 @@ proc sc_setup_sta { } {
         set_timing_derate -late $sta_late_timing_derate
     }
 
-    # Create path groups
-    if {
-        [lindex [sc_cfg_tool_task_get var sta_define_path_groups] 0] == "true" &&
-        [llength [sta::path_group_names]] == 0
-    } {
-        sc_path_group -name in2out -from [all_inputs -no_clocks] -to [all_outputs]
-
+    if { [sc_check_version 19370] } {
+        # Create path groups
         if {
-            [llength [all_clocks]] == 1 ||
-            [lindex [sc_cfg_tool_task_get var sta_unique_path_groups_per_clock] 0] == "false"
+            [lindex [sc_cfg_tool_task_get var sta_define_path_groups] 0] == "true" &&
+            [llength [sta::path_group_names]] == 0
         } {
-            sc_path_group -name in2reg -from [all_inputs -no_clocks] -to [all_registers]
-            sc_path_group -name reg2reg -from [all_registers] -to [all_registers]
-            sc_path_group -name reg2out -from [all_registers] -to [all_outputs]
-        } else {
-            foreach clock [all_clocks] {
-                set clk_name [get_property $clock name]
-                sc_path_group -name in2reg.${clk_name} \
-                    -from [all_inputs -no_clocks] \
-                    -to [all_registers -clock $clock]
-                sc_path_group -name reg2reg.${clk_name} \
-                    -from [all_registers -clock $clock] \
-                    -to [all_registers -clock $clock]
-                sc_path_group -name reg2out.${clk_name} \
-                    -from [all_registers -clock $clock] \
-                    -to [all_outputs]
+            sc_path_group -name in2out -from [all_inputs -no_clocks] -to [all_outputs]
+
+            if {
+                [llength [all_clocks]] == 1 ||
+                [lindex [sc_cfg_tool_task_get var sta_unique_path_groups_per_clock] 0] == "false"
+            } {
+                sc_path_group -name in2reg -from [all_inputs -no_clocks] -to [all_registers]
+                sc_path_group -name reg2reg -from [all_registers] -to [all_registers]
+                sc_path_group -name reg2out -from [all_registers] -to [all_outputs]
+            } else {
+                foreach clock [all_clocks] {
+                    set clk_name [get_property $clock name]
+                    sc_path_group -name in2reg.${clk_name} \
+                        -from [all_inputs -no_clocks] \
+                        -to [all_registers -clock $clock]
+                    sc_path_group -name reg2reg.${clk_name} \
+                        -from [all_registers -clock $clock] \
+                        -to [all_registers -clock $clock]
+                    sc_path_group -name reg2out.${clk_name} \
+                        -from [all_registers -clock $clock] \
+                        -to [all_outputs]
+                }
             }
         }
+        utl::info FLW 1 "Timing path groups: [sta::path_group_names]"
     }
-    utl::info FLW 1 "Timing path groups: [sta::path_group_names]"
 
     # Check timing setup
     if { [sc_cfg_tool_task_check_in_list check_setup var reports] } {

siliconcompiler/tools/vpr/route.py

@@ -44,6 +44,45 @@ def setup(chip, clobber=True):
     chip.add('tool', tool, 'task', task, 'output', design + '.net', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.place', step=step, index=index)
 
+    # Add a parameter for generating a post-implementation netlist for external
+    # static timing analysis.
+    chip.set('tool', tool, 'task', task, 'var', 'gen_post_implementation_netlist',
+             False, step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'gen_post_implementation_netlist',
+             'set to true to have VPR generate a post-implementation netlist',
+             field='help')
+
+    chip.set('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'gen_post_implementation_netlist']),
+             step=step, index=index)
+
+    # Add a parameter to control the timing corner used when generating SDF files.
+    chip.set('tool', tool, 'task', task, 'var', 'timing_corner', 'typical',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'timing_corner',
+             'set the timing corner for files generated by the post-implementation netlist',
+             field='help')
+
+    chip.set('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'timing_corner']),
+             step=step, index=index)
+
+    # Add the post-implementation timing netlist outputs if requested.
+    gen_post_implementation_netlist = chip.get('tool', tool, 'task', task, 'var',
+                                               'gen_post_implementation_netlist',
+                                               step=step, index=index)[0]
+    timing_corner = chip.get('tool', tool, 'task', task, 'var', 'timing_corner',
+                             step=step, index=index)[0]
+    if gen_post_implementation_netlist == 'true':
+        chip.add('tool', tool, 'task', task, 'output', f'{design}.vg',
+                 step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'output', f'{design}.sdc',
+                 step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'output', f'{design}.{timing_corner}.sdf',
+                 step=step, index=index)
+
 
 def runtime_options(chip):
     '''Command line options to vpr for the route step
@@ -104,6 +143,21 @@ def runtime_options(chip):
         options.append("--graphics_commands")
         options.append(graphics_command_str)
 
+    # Generate a post-implementation netlist for use in external timing analysis
+    # if requested.
+    gen_post_implementation_netlist = chip.get('tool', tool, 'task', task, 'var',
+                                               'gen_post_implementation_netlist',
+                                               step=step, index=index)[0]
+    if gen_post_implementation_netlist == 'true':
+        # Generate the netlist.
+        options.extend(["--gen_post_synthesis_netlist", "on"])
+        # Generate the SDC file.
+        options.extend(["--gen_post_implementation_sdc", "on"])
+        # Create undriven nets for unconnected inputs.
+        options.extend(["--post_synth_netlist_unconn_inputs", "nets"])
+        # Turn off module parameters.
+        options.extend(["--post_synth_netlist_module_parameters", "off"])
+
     return options
 
 
@@ -122,3 +176,18 @@ def post_process(chip):
     shutil.copy2(f'inputs/{design}.blif', 'outputs')
     shutil.copy2(f'inputs/{design}.net', 'outputs')
     shutil.copy2(f'inputs/{design}.place', 'outputs')
+
+    # Copy and rename the post-implementation netlist results into the output
+    # directory to be used in external timing analysis.
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    gen_post_implementation_netlist = chip.get('tool', tool, 'task', task, 'var',
+                                               'gen_post_implementation_netlist',
+                                               step=step, index=index)[0]
+    timing_corner = chip.get('tool', tool, 'task', task, 'var', 'timing_corner',
+                             step=step, index=index)[0]
+    if gen_post_implementation_netlist == 'true':
+        shutil.move(f'{design}_post_synthesis.v', f'outputs/{design}.vg')
+        shutil.move(f'{design}_post_synthesis.sdc', f'outputs/{design}.sdc')
+        shutil.move(f'{design}_post_synthesis.sdf', f'outputs/{design}.{timing_corner}.sdf')

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "cd121c095a6f77a501166e0961b2e93763c51b17",
+    "git-commit": "4b729ea474e9bd0a3513579b41a8c96fe20dc75e",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "0b59461bddb4ebc2228a20f17c9089be1f8c19da",
+    "git-commit": "343b93b6336962b2dbcc5b7c7500c01df0367696",
     "auto-update": true
   },
   "netgen": {
@@ -101,7 +101,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.53",
+    "git-commit": "v0.54",
     "version-prefix": "",
     "auto-update": true
   },
@@ -151,7 +151,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "7da40107a513f0094d209ab3b0899f64e8dbeb0e",
+    "git-commit": "e863336db656b1f0ec82f7af65249b6a4ee3e56c",
     "docker-depends": "yosys",
     "auto-update": true
   },

siliconcompiler/utils/__init__.py

@@ -329,29 +329,6 @@ def grep(chip, args, line):
         return line
 
 
-#######################################
-def get_env_vars(chip, step, index):
-    '''
-    Returns a dictionary of environmental variables from the manifest
-    '''
-
-    schema_env = {}
-    for env in chip.getkeys('option', 'env'):
-        schema_env[env] = chip.get('option', 'env', env)
-
-    flow = chip.get('option', 'flow')
-    if step is not None and index is not None and flow:
-        tool = chip.get('flowgraph', flow, step, str(index), 'tool')
-        task = chip.get('flowgraph', flow, step, str(index), 'task')
-
-        if chip.valid('tool', tool, 'task', task, 'env'):
-            for env in chip.getkeys('tool', tool, 'task', task, 'env'):
-                schema_env[env] = chip.get('tool', tool, 'task', task, 'env', env,
-                                           step=step, index=index)
-
-    return schema_env
-
-
 def get_plugins(system, name=None):
     '''
     Search for python modules with a specific function
@@ -370,6 +347,8 @@ def get_plugins(system, name=None):
 
 
 def truncate_text(text, width):
+    width = max(width, 5)
+
     if len(text) <= width:
         return text
 

siliconcompiler/utils/flowgraph.py

@@ -4,6 +4,7 @@ from siliconcompiler import NodeStatus
 from siliconcompiler.tools._common import input_file_node_name, get_tool_task
 
 from siliconcompiler.flowgraph import RuntimeFlowgraph
+from siliconcompiler.scheduler.schedulernode import SchedulerNode
 
 
 ###########################################################################
@@ -87,7 +88,6 @@ def _check_flowgraph_io(chip, nodes=None):
 
 
 def _get_flowgraph_information(chip, flow, io=True):
-    from siliconcompiler.scheduler import _setup_node
     from siliconcompiler.tools._common import input_provides, input_file_node_name
 
     # Save schema to avoid making permanent changes
@@ -97,12 +97,12 @@ def _get_flowgraph_information(chip, flow, io=True):
     # Setup nodes
     node_exec_order = chip.schema.get("flowgraph", flow, field="schema").get_execution_order()
     if io:
-        # try:
+        prev_flow = chip.get("option", "flow")
+        chip.set("option", "flow", flow)
         for layer_nodes in node_exec_order:
             for step, index in layer_nodes:
-                _setup_node(chip, step, index, flow=flow)
-        # except:  # noqa E722
-        #     io = False
+                SchedulerNode(chip, step, index).setup()
+        chip.set("option", "flow", prev_flow)
 
     node_rank = {}
     for rank, rank_nodes in enumerate(node_exec_order):

siliconcompiler/utils/logging.py

@@ -1,6 +1,5 @@
 import logging
 import sys
-from siliconcompiler.remote import client
 from siliconcompiler import utils
 
 
@@ -38,6 +37,8 @@ class SCInRunLoggerFormatter(logging.Formatter):
 
     @staticmethod
     def configure_format(fmt, chip, step, index):
+        from siliconcompiler.remote import client
+
         max_width = 20
 
         flow = chip.get('option', 'flow')

{siliconcompiler-0.33.2.dist-info → siliconcompiler-0.34.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: siliconcompiler
-Version: 0.33.2
+Version: 0.34.0
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -27,7 +27,7 @@ Description-Content-Type: text/markdown
 License-File: LICENSE
 Requires-Dist: aiohttp==3.10.11; python_version <= "3.8"
 Requires-Dist: aiohttp<3.13.0,>=3.10.11; python_version >= "3.9"
-Requires-Dist: requests==2.32.3
+Requires-Dist: requests==2.32.4
 Requires-Dist: PyYAML==6.0.2
 Requires-Dist: pandas>=1.1.5
 Requires-Dist: Jinja2>=2.11.3
@@ -57,7 +57,8 @@ Requires-Dist: streamlit-autorefresh==1.0.1; python_full_version != "3.9.7"
 Requires-Dist: rich==13.9.4; python_version <= "3.8"
 Requires-Dist: rich<15.0.0,>=14.0.0; python_version >= "3.9"
 Provides-Extra: test
-Requires-Dist: pytest==8.3.5; extra == "test"
+Requires-Dist: pytest==8.3.5; python_version <= "3.8" and extra == "test"
+Requires-Dist: pytest==8.4.0; python_version >= "3.9" and extra == "test"
 Requires-Dist: pytest-xdist==3.6.1; python_version <= "3.8" and extra == "test"
 Requires-Dist: pytest-xdist==3.7.0; python_version >= "3.9" and extra == "test"
 Requires-Dist: pytest-timeout==2.4.0; extra == "test"