siliconcompiler 0.33.0__py3-none-any.whl → 0.33.2__py3-none-any.whl

siliconcompiler/tools/klayout/klayout_utils.py

@@ -84,12 +84,12 @@ def technology(design, schema):
         lefs.extend(schema.get('library', lib, 'output', sc_stackup, 'lef',
                                step=sc_step, index=sc_index))
 
-    layoutOptions = tech.load_layout_options
+    layout_options = tech.load_layout_options
 
-    layoutOptions.lefdef_config.macro_resolution_mode = 1
-    layoutOptions.lefdef_config.via_cellname_prefix = "VIA_"
+    layout_options.lefdef_config.macro_resolution_mode = 1
+    layout_options.lefdef_config.via_cellname_prefix = "VIA_"
     pathed_files = set()
-    for lef_file in layoutOptions.lefdef_config.lef_files:
+    for lef_file in layout_options.lefdef_config.lef_files:
         if foundry_lef and not os.path.isabs(lef_file):
             lef_file = os.path.join(os.path.dirname(foundry_lef), lef_file)
         lef_file = os.path.abspath(lef_file)
@@ -99,13 +99,13 @@ def technology(design, schema):
     for lef in lefs:
         pathed_files.add(os.path.abspath(lef))
 
-    layoutOptions.lefdef_config.lef_files = list(pathed_files)
-    layoutOptions.lefdef_config.read_lef_with_def = False
-    layoutOptions.lefdef_config.dbu = tech.dbu
+    layout_options.lefdef_config.lef_files = list(pathed_files)
+    layout_options.lefdef_config.read_lef_with_def = False
+    layout_options.lefdef_config.dbu = tech.dbu
 
-    layoutOptions.lefdef_config.produce_fills = True
+    layout_options.lefdef_config.produce_fills = True
 
-    for lef_file in layoutOptions.lefdef_config.lef_files:
+    for lef_file in layout_options.lefdef_config.lef_files:
         print(f"[INFO] LEF file: {lef_file}")
 
     # Set layer properties
@@ -127,7 +127,7 @@ def technology(design, schema):
         print(f"[INFO] Layer properties: {layer_properties}")
 
     # Set layer map
-    map_file = layoutOptions.lefdef_config.map_file
+    map_file = layout_options.lefdef_config.map_file
     if map_file:
         map_file = map_file[0]
         if not os.path.isabs(map_file):
@@ -141,10 +141,10 @@ def technology(design, schema):
                 break
 
     if map_file and os.path.exists(map_file):
-        layoutOptions.lefdef_config.map_file = map_file
+        layout_options.lefdef_config.map_file = map_file
         print(f"[INFO] Layer map: {map_file}")
 
-    tech.load_layout_options = layoutOptions
+    tech.load_layout_options = layout_options
 
     return tech
 

siliconcompiler/tools/netgen/count_lvs.py

@@ -34,7 +34,7 @@ import argparse
 from siliconcompiler import sc_open
 
 
-def count_LVS_failures(filename):
+def count_lvs_failures(filename):
     with sc_open(filename) as cfile:
         lvsdata = json.load(cfile)
 
@@ -114,7 +114,7 @@ if __name__ == '__main__':
     parser = argparse.ArgumentParser(description='Parses netgen lvs')
     parser.add_argument('--file', '-f', required=True)
     args = parser.parse_args()
-    failures = count_LVS_failures(args.file)
+    failures = count_lvs_failures(args.file)
     total = failures[0]
     if total > 0:
         failed = True

siliconcompiler/tools/netgen/lvs.py

@@ -79,7 +79,7 @@ def post_process(chip):
         chip.logger.warning('No LVS report generated. Netgen may have encountered errors.')
         return
 
-    lvs_failures = count_lvs.count_LVS_failures(lvs_report)
+    lvs_failures = count_lvs.count_lvs_failures(lvs_report)
 
     # We don't count top-level pin mismatches as errors b/c we seem to get
     # false positives for disconnected pins. Report them as warnings

siliconcompiler/tools/openroad/_apr.py

@@ -402,7 +402,7 @@ def _generate_cell_area_report(design, ord_metrics):
         if stdcell_info_area:
             stdcellarea = sum(stdcell_info_area)
 
-        cellarea_report.addCell(
+        cellarea_report.add_cell(
             name=cell_name,
             module=cell_type,
             cellarea=cellarea,
@@ -420,7 +420,7 @@ def _generate_cell_area_report(design, ord_metrics):
         process_cell(module)
 
     if cellarea_report.size() > 0:
-        cellarea_report.writeReport("reports/hierarchical_cell_area.json")
+        cellarea_report.write_report("reports/hierarchical_cell_area.json")
 
 
 def define_tapcell_params(chip):

siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl

@@ -19,13 +19,7 @@ source "$sc_refdir/apr/preamble.tcl"
 # Setup Global Connections
 ###############################
 
-if { [sc_cfg_tool_task_exists {file} global_connect] } {
-    foreach global_connect [sc_cfg_tool_task_get {file} global_connect] {
-        puts "Sourcing global connect configuration: ${global_connect}"
-        source $global_connect
-    }
-}
-tee -file reports/global_connections.rpt {report_global_connect}
+sc_global_connections
 
 ###############################
 # Initialize floorplan

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -874,3 +874,21 @@ proc sc_report_args { args } {
 
     puts "$keys(-command) siliconcompiler arguments: $keys(-args)"
 }
+
+proc sc_global_connections { args } {
+    sta::check_argc_eq0 "sc_global_connections" $args
+
+    if { [sc_cfg_tool_task_exists {file} global_connect] } {
+        set global_connect_files []
+        foreach global_connect [sc_cfg_tool_task_get {file} global_connect] {
+            if { [lsearch -exact $global_connect_files $global_connect] != -1 } {
+                continue
+            }
+            puts "Loading global connect configuration: ${global_connect}"
+            source $global_connect
+
+            lappend global_connect_files $global_connect
+        }
+    }
+    tee -file reports/global_connections.rpt {report_global_connect}
+}

siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl

@@ -50,11 +50,5 @@ if { [sc_has_input_files odb "input layout odb"] } {
     }
 
     # Handle global connect setup
-    if { [sc_cfg_tool_task_exists {file} global_connect] } {
-        foreach global_connect [sc_cfg_tool_task_get {file} global_connect] {
-            puts "Loading global connect configuration: ${global_connect}"
-            source $global_connect
-        }
-    }
-    tee -file reports/global_connections.rpt {report_global_connect}
+    sc_global_connections
 }

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -150,6 +150,16 @@ foreach corner $sc_scenarios {
     }
 }
 
+foreach corner $sc_scenarios {
+    set pex_corner [sc_cfg_get constraint timing $corner pexcorner]
+
+    set input_sdf_file "inputs/${sc_design}.${pex_corner}.sdf"
+    if { [file exists $input_sdf_file] } {
+        puts "Reading SDF ($corner): $input_sdf_file"
+        read_sdf -corner $corner $input_sdf_file
+    }
+}
+
 ###############################
 # Report Metrics
 ###############################

siliconcompiler/tools/opensta/timing.py

@@ -70,6 +70,17 @@ def setup(chip):
             chip.add('tool', tool, 'task', task, 'require', f'constraint,timing,{scenario},file',
                      step=step, index=index)
 
+    # Add the SPEF or SDF files as inputs if provided.
+    spef_files = [f for f in input_provides(chip, step, index) if f.endswith(".spef")]
+    sdf_files = [f for f in input_provides(chip, step, index) if f.endswith(".sdf")]
+    if spef_files and sdf_files:
+        # If both SPEF and SDF files are provided, only use the SPEF files.
+        chip.add('tool', tool, 'task', task, 'input', spef_files, step=step, index=index)
+    elif spef_files:
+        chip.add('tool', tool, 'task', task, 'input', spef_files, step=step, index=index)
+    elif sdf_files:
+        chip.add('tool', tool, 'task', task, 'input', sdf_files, step=step, index=index)
+
     add_common_file(chip, 'opensta_generic_sdc', 'sdc/sc_constraints.sdc')
 
 

siliconcompiler/tools/slang/__init__.py

@@ -11,6 +11,7 @@ Sources: https://github.com/MikePopoloski/slang
 Installation: https://sv-lang.com/building.html
 '''
 import os
+import shlex
 
 try:
     import pyslang
@@ -121,7 +122,6 @@ def common_runtime_options(chip):
     ###############################
     # Set up user-provided parameters to ensure we elaborate the correct modules
     for param, value in opts['param']:
-        value = value.replace('"', '\\"')
         options.extend(['-G', f'{param}={value}'])
 
     return options
@@ -133,11 +133,12 @@ def _get_driver(chip, options_func, ignored_diagnotics=None):
 
     options = options_func(chip)
 
-    parseOpts = pyslang.CommandLineOptions()
-    parseOpts.ignoreProgramName = True
-    opts = " ".join(options)
+    parse_options = pyslang.CommandLineOptions()
+    parse_options.ignoreProgramName = True
+    opts = shlex.join(options)
+    chip.logger.info(f"runtime arguments: {opts}")
     code = 0
-    if not driver.parseCommandLine(opts, parseOpts):
+    if not driver.parseCommandLine(opts, parse_options):
         code = 1
 
     if code == 0 and not driver.processOptions():

siliconcompiler/tools/slang/elaborate.py

@@ -50,16 +50,16 @@ def __get_files(manager, tree):
     nodes = Queue(maxsize=0)
     nodes.put(tree.root)
 
-    def procRange(range):
+    def proc_range(range):
         files.add(manager.getFileName(range.start))
         files.add(manager.getFileName(range.end))
 
     while not nodes.empty():
         node = nodes.get()
-        procRange(node.sourceRange)
+        proc_range(node.sourceRange)
         for token in node:
             if isinstance(token, pyslang.Token):
-                procRange(token.range)
+                proc_range(token.range)
             else:
                 nodes.put(token)
 
@@ -103,7 +103,7 @@ def run(chip):
     add_source = chip.get('tool', tool, 'task', task, 'var', 'include_source_paths',
                           step=step, index=index)[0] == 'true'
 
-    def printFiles(out, files):
+    def print_files(out, files):
         for src_file in files:
             out.write(f'//   File: {src_file}\n')
 
@@ -126,12 +126,12 @@ def run(chip):
 
             out.write("////////////////////////////////////////////////////////////////\n")
             out.write("// Start:\n")
-            printFiles(out, files)
+            print_files(out, files)
 
             out.write(writer.print(tree).str() + '\n')
 
             out.write("// End:\n")
-            printFiles(out, files)
+            print_files(out, files)
             out.write("////////////////////////////////////////////////////////////////\n")
 
     if ok:

siliconcompiler/tools/slang/lint.py

@@ -37,9 +37,7 @@ def run(chip):
 def runtime_options(chip):
     options = slang.common_runtime_options(chip)
     options.extend([
-        "--lint-only",
-        "-Weverything",
-        "-Werror"
+        "-Weverything"
     ])
 
     return options

siliconcompiler/tools/vpr/_xml_constraint.py

@@ -1,4 +1,4 @@
-import xml.etree.ElementTree as ET
+from xml.etree import ElementTree
 import xml.dom.minidom
 
 
@@ -10,7 +10,7 @@ def generate_vpr_constraints_xml_file(pin_map, filename):
 
 def generate_vpr_constraints_xml(pin_map):
 
-    constraints_xml = ET.Element("vpr_constraints")
+    constraints_xml = ElementTree.Element("vpr_constraints")
 
     # Generate partition list section
     partition_list = generate_partition_list_xml(pin_map)
@@ -22,7 +22,7 @@ def generate_vpr_constraints_xml(pin_map):
 
 def generate_partition_list_xml(pin_map):
 
-    partition_list = ET.Element("partition_list")
+    partition_list = ElementTree.Element("partition_list")
 
     # ***ASSUMPTION:  pin map is a dictionary of block names
     #                 and tuples, where the tuples specify the
@@ -38,7 +38,7 @@ def generate_partition_list_xml(pin_map):
 
 def generate_partition_xml(pin, pin_region):
 
-    partition = ET.Element("partition")
+    partition = ElementTree.Element("partition")
 
     partition_name = generate_partition_name(pin)
     partition.set("name", partition_name)
@@ -80,7 +80,7 @@ def generate_partition_name(pin):
 
 def generate_add_atom_xml(pin_name):
 
-    atom_xml = ET.Element("add_atom")
+    atom_xml = ElementTree.Element("add_atom")
 
     atom_xml.set("name_pattern", str(pin_name))
 
@@ -89,7 +89,7 @@ def generate_add_atom_xml(pin_name):
 
 def generate_add_region_xml(x_low, x_high, y_low, y_high, subtile):
 
-    region_xml = ET.Element("add_region")
+    region_xml = ElementTree.Element("add_region")
 
     region_xml.set("x_low", str(x_low))
     region_xml.set("y_low", str(y_low))
@@ -100,9 +100,9 @@ def generate_add_region_xml(x_low, x_high, y_low, y_high, subtile):
     return region_xml
 
 
-def write_vpr_constraints_xml_file(constraints: ET.Element, filename: str):
+def write_vpr_constraints_xml_file(constraints: ElementTree.Element, filename: str):
 
-    dom = xml.dom.minidom.parseString(ET.tostring(constraints))
+    dom = xml.dom.minidom.parseString(ElementTree.tostring(constraints))
     xml_string = dom.toprettyxml()
 
     with open(filename, 'w') as xfile:

siliconcompiler/tools/yosys/prepareLib.py

@@ -6,7 +6,7 @@ import gzip
 import argparse  # argument parsing
 
 
-def processLibertyFile(input_file, logger=None):
+def process_liberty_file(input_file, logger=None):
     # Read input file
     if logger:
         logger.info(f"Opening file for replace: {input_file}")
@@ -56,4 +56,4 @@ if __name__ == "__main__":
                         help='Output File')
     args = parser.parse_args()
 
-    processLibertyFile(args.inputFile, args.outputFile, args.patterns)
+    process_liberty_file(args.inputFile, args.outputFile, args.patterns)

siliconcompiler/tools/yosys/sc_synth_asic.tcl

@@ -75,7 +75,9 @@ if { [sc_cfg_tool_task_exists file memory_techmap] } {
 ########################################################
 
 foreach lib_file "$sc_libraries $sc_macro_libraries" {
-    yosys read_liberty -setattr liberty_cell -lib $lib_file
+    yosys read_liberty -overwrite -setattr liberty_cell -lib $lib_file
+    yosys read_liberty -overwrite -setattr liberty_cell \
+        -unit_delay -wb -ignore_miss_func -ignore_buses $lib_file
 }
 foreach bb_file $sc_blackboxes {
     yosys log "Reading blackbox model file: $bb_file"
@@ -118,10 +120,6 @@ if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugi
     set slang_params []
     if { [sc_cfg_exists option param] } {
         dict for {key value} [sc_cfg_get option param] {
-            if { ![string is integer $value] } {
-                set value [concat \"$value\"]
-            }
-
             lappend slang_params -G "${key}=${value}"
         }
     }
@@ -187,6 +185,45 @@ proc get_modules { { find "*" } } {
     return [lsort $modules]
 }
 
+proc sc_annotate_gate_cost_equivalent { } {
+    yosys cellmatch -derive_luts =A:liberty_cell
+    # find a reference nand2 gate
+    set found_cell ""
+    set found_cell_area ""
+    # iterate over all cells with a nand2 signature
+    yosys echo off
+    set nand2_cells [yosys tee -q -s result.string select -list-mod =*/a:lut=4'b0111 %m]
+    yosys echo on
+    foreach cell $nand2_cells {
+        if { ![rtlil::has_attr -mod $cell area] } {
+            puts "WARNING: Cell $cell missing area information"
+            continue
+        }
+        set area [rtlil::get_attr -string -mod $cell area]
+        if { $found_cell == "" || $area < $found_cell_area } {
+            set found_cell $cell
+            set found_cell_area $area
+        }
+    }
+    if { $found_cell == "" } {
+        set found_cell_area 1
+        puts "WARNING: reference nand2 cell not found, using $found_cell_area as area"
+    } else {
+        puts "Using nand2 reference cell ($found_cell) with area: $found_cell_area"
+    }
+
+    # convert the area on all Liberty cells to a gate number equivalent
+    yosys echo off
+    set cells [yosys tee -q -s result.string select -list-mod =A:area =A:liberty_cell %i]
+    yosys echo on
+    foreach cell $cells {
+        set area [rtlil::get_attr -mod -string $cell area]
+        set gate_eq [expr { int(max(1, ceil($area / $found_cell_area))) }]
+        puts "Setting gate_cost_equivalent for $cell as $gate_eq"
+        rtlil::set_attr -mod -uint $cell gate_cost_equivalent $gate_eq
+    }
+}
+
 #########################
 # Schema helper functions
 #########################
@@ -296,6 +333,7 @@ if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "
     set sc_hier_threshold \
         [lindex [sc_cfg_tool_task_get var hier_threshold] 0]
 
+    sc_annotate_gate_cost_equivalent
     yosys keep_hierarchy -min_cost $sc_hier_threshold
 
     yosys synth -flatten {*}$synth_args -top $sc_design -run coarse:fine

siliconcompiler/tools/yosys/screenshot.py

@@ -75,7 +75,7 @@ def prepare_asic_libraries(chip):
                     lib_file_name = f'{lib_file_name_base}_{unique_ident}'
                     unique_ident += 1
 
-                lib_content[lib_file_name] = prepareLib.processLibertyFile(
+                lib_content[lib_file_name] = prepareLib.process_liberty_file(
                         lib_file,
                         logger=None if chip.get('option', 'quiet',
                                                 step=step, index=index) else chip.logger)

siliconcompiler/tools/yosys/syn_asic.py

@@ -2,7 +2,7 @@ from siliconcompiler.tools.yosys import synth_post_process, setup as tool_setup
 import os
 import json
 import re
-from siliconcompiler.tools.yosys.prepareLib import processLibertyFile
+from siliconcompiler.tools.yosys.prepareLib import process_liberty_file
 from siliconcompiler import sc_open
 from siliconcompiler import utils
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
@@ -322,7 +322,7 @@ def prepare_synthesis_libraries(chip):
                     lib_file_name = f'{lib_file_name_base}_{unique_ident}'
                     unique_ident += 1
 
-                lib_content[lib_file_name] = processLibertyFile(
+                lib_content[lib_file_name] = process_liberty_file(
                     lib_file,
                     logger=logger
                 )
@@ -583,7 +583,7 @@ def _generate_cell_area_report(chip):
             cell_type = level_info["cells"][cell]["type"]
             if cell_type in modules:
                 area, count = get_area_count(cell_type)
-                cellarea_report.addCell(
+                cellarea_report.add_cell(
                     name=f"{prefix}{cell}",
                     module=cell_type,
                     cellcount=count,
@@ -594,7 +594,7 @@ def _generate_cell_area_report(chip):
     area = 0.0
     if "area" in stat["design"]:
         area = stat["design"]["area"]
-    cellarea_report.addCell(
+    cellarea_report.add_cell(
         name=design,
         module=design,
         cellarea=area,
@@ -604,4 +604,4 @@ def _generate_cell_area_report(chip):
     handle_heir(netlist["modules"][design], "")
 
     if cellarea_report.size() > 0:
-        cellarea_report.writeReport("reports/hierarchical_cell_area.json")
+        cellarea_report.write_report("reports/hierarchical_cell_area.json")

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "ce617810e4dc11b3cdb5a267ef3454788f81aaf0",
+    "git-commit": "cd121c095a6f77a501166e0961b2e93763c51b17",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -17,7 +17,7 @@
   },
   "opensta": {
     "git-url": "https://github.com/parallaxsw/OpenSTA.git",
-    "git-commit": "b32eed9a849381172a5d3208cc7798a8a11c4c9b",
+    "git-commit": "0b59461bddb4ebc2228a20f17c9089be1f8c19da",
     "auto-update": true
   },
   "netgen": {
@@ -41,16 +41,21 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.30.1",
+    "version": "0.30.2",
     "git-url": "https://github.com/KLayout/klayout.git",
-    "docker-skip": true,
     "auto-update": true,
     "run-version": "source version.sh && echo $KLAYOUT_VERSION",
-    "release-notes": "https://www.klayout.de/development.html"
+    "release-notes": "https://www.klayout.de/development.html",
+    "docker-cmds": [
+      "RUN echo \"#!/bin/bash\" > $SC_PREFIX/install-klayout.sh",
+      "RUN echo \"sudo apt-get install -y $SC_PREFIX/klayout.deb\" >> $SC_PREFIX/install-klayout.sh",
+      "RUN echo \"sudo rm $SC_PREFIX/klayout.deb\" >> $SC_PREFIX/install-klayout.sh",
+      "RUN chmod +x $SC_PREFIX/install-klayout.sh"
+    ]
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "d30c7e7f4e9018b9d4a565207ff752460c81eeb4",
+    "git-commit": "380c2b978a54e459ac216c9e6b7f1a4e31573a0e",
     "auto-update": true
   },
   "verilator": {
@@ -101,8 +106,10 @@
     "auto-update": true
   },
   "xyce": {
-    "version": "7.8",
-    "auto-update": false
+    "git-url": "https://github.com/Xyce/Xyce.git",
+    "git-commit": "Release-7.9.0",
+    "version-prefix": "Release-",
+    "auto-update": true
   },
   "xdm": {
     "git-url": "https://github.com/Xyce/XDM.git",
@@ -133,7 +140,7 @@
     "auto-update": false
   },
   "slang": {
-    "git-commit": "v8.0",
+    "git-commit": "v8.1",
     "git-url": "https://github.com/MikePopoloski/slang.git",
     "auto-update": true
   },
@@ -144,7 +151,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "7d4959430442ac1d7e3bf7b3e55d648293a5ac7b",
+    "git-commit": "7da40107a513f0094d209ab3b0899f64e8dbeb0e",
     "docker-depends": "yosys",
     "auto-update": true
   },

siliconcompiler/toolscripts/rhel8/install-chisel.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum install -y wget
 
 mkdir -p deps
@@ -19,7 +26,7 @@ if [ ! -z ${PREFIX} ]; then
     args="-C $PREFIX --strip-components 1"
 fi
 
-tar xvf sbt.tgz $args
+$SUDO_INSTALL tar xvf sbt.tgz $args
 
 cd -
 

siliconcompiler/toolscripts/rhel8/install-icarus.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum group install -y "Development Tools"
 sudo yum install -y wget git
 
@@ -21,7 +28,7 @@ tar xvf gperf-3.1.tar.gz
 cd gperf-3.1
 ./configure $args
 make -j$(nproc)
-sudo make install
+$SUDO_INSTALL make install
 cd ..
 
 if [ ! -z ${PREFIX} ]; then
@@ -36,6 +43,6 @@ git checkout $(python3 ${src_path}/_tools.py --tool icarus --field git-commit)
 sh autoconf.sh
 ./configure $args
 make -j$(nproc)
-sudo make install
+$SUDO_INSTALL make install
 
 cd -

siliconcompiler/toolscripts/rhel8/install-klayout.sh

@@ -1,10 +1,17 @@
 #!/bin/sh
 
-set -e
+set -ex
 
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+USE_SUDO_INSTALL="${USE_SUDO_INSTALL:-yes}"
+if [ "${USE_SUDO_INSTALL:-yes}" = "yes" ]; then
+    SUDO_INSTALL=sudo
+else
+    SUDO_INSTALL=""
+fi
+
 sudo yum install -y wget
 
 mkdir -p deps