siliconcompiler 0.32.2__py3-none-any.whl → 0.32.3__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -28,7 +28,7 @@ if { [sc_cfg_tool_task_check_in_list setup var reports] } {
         "report_tns"
     report_tns_metric -setup
 
-    if { [sc_check_version 19519] } {
+    if { [sc_check_version 19519] && [llength [all_clocks]] > 0 } {
         tee -quiet -file reports/timing/setup.histogram.rpt \
             "report_timing_histogram -num_bins 20 -setup"
     }
@@ -48,7 +48,7 @@ if { [sc_cfg_tool_task_check_in_list hold var reports] } {
 
     report_tns_metric -hold
 
-    if { [sc_check_version 19519] } {
+    if { [sc_check_version 19519] && [llength [all_clocks]] > 0 } {
         tee -quiet -file reports/timing/hold.histogram.rpt \
             "report_timing_histogram -num_bins 20 -hold"
     }

siliconcompiler/tools/openroad/scripts/sc_rcx.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Helper functions

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter

siliconcompiler/tools/openroad/scripts/sc_show.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter

siliconcompiler/tools/opensta/__init__.py

@@ -32,7 +32,7 @@ def setup(chip):
 
     chip.set('tool', tool, 'exe', 'sta')
     chip.set('tool', tool, 'vswitch', '-version')
-    chip.set('tool', tool, 'version', '>=v2.5.0', clobber=False)
+    chip.set('tool', tool, 'version', '>=v2.6.2', clobber=False)
     chip.set('tool', tool, 'format', 'tcl')
 
     targetlibs = get_libraries(chip, 'logic')

siliconcompiler/tools/opensta/scripts/sc_check_library.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter

siliconcompiler/tools/opensta/scripts/sc_procs.tcl

@@ -44,3 +44,19 @@ proc sc_display_report { report } {
     close $fid
     puts $report_content
 }
+
+proc sc_path_group { args } {
+    sta::parse_key_args "sc_path_group" args \
+        keys {-name -to -from} \
+        flags {}
+
+    sta::check_argc_eq0 "sc_path_group" $args
+
+    if { [llength $keys(-from)] == 0 } {
+        return
+    }
+    if { [llength $keys(-to)] == 0 } {
+        return
+    }
+    group_path -name $keys(-name) -from $keys(-from) -to $keys(-to)
+}

siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter
@@ -38,6 +38,12 @@ foreach corner [dict keys [sc_cfg_get constraint timing]] {
 # MACROS
 set sc_macrolibs [sc_get_asic_libraries macro]
 
+###############################
+# Source helper functions
+###############################
+
+source "$sc_refdir/sc_procs.tcl"
+
 ###############################
 # Read Files
 ###############################
@@ -104,6 +110,34 @@ if { [file exists "inputs/${sc_design}.sdc"] } {
     read_sdc "${sdc}"
 }
 
+# Create path groups
+if { [llength [sta::path_group_names]] == 0 } {
+    sc_path_group -name in2out -from [all_inputs -no_clocks] -to [all_outputs]
+
+    if {
+        [llength [all_clocks]] == 1 ||
+        [lindex [sc_cfg_tool_task_get var unique_path_groups_per_clock] 0] == "false"
+    } {
+        sc_path_group -name in2reg -from [all_inputs -no_clocks] -to [all_registers]
+        sc_path_group -name reg2reg -from [all_registers] -to [all_registers]
+        sc_path_group -name reg2out -from [all_registers] -to [all_outputs]
+    } else {
+        foreach clock [all_clocks] {
+            set clk_name [get_property $clock name]
+            sc_path_group -name in2reg.${clk_name} \
+                -from [all_inputs -no_clocks] \
+                -to [all_registers -clock $clock]
+            sc_path_group -name reg2reg.${clk_name} \
+                -from [all_registers -clock $clock] \
+                -to [all_registers -clock $clock]
+            sc_path_group -name reg2out.${clk_name} \
+                -from [all_registers -clock $clock] \
+                -to [all_outputs]
+        }
+    }
+}
+puts "Timing path groups: [sta::path_group_names]"
+
 ###############################
 
 foreach corner $sc_scenarios {
@@ -116,12 +150,6 @@ foreach corner $sc_scenarios {
     }
 }
 
-###############################
-# Source helper functions
-###############################
-
-source "$sc_refdir/sc_procs.tcl"
-
 ###############################
 # Report Metrics
 ###############################

siliconcompiler/tools/opensta/timing.py

@@ -45,6 +45,10 @@ def setup(chip):
     set_tool_task_var(chip, param_key='top_n_paths',
                       default_value='10',
                       schelp='number of paths to report timing for')
+    set_tool_task_var(chip, param_key='unique_path_groups_per_clock',
+                      default_value=False,
+                      skip=['pdk', 'lib'],
+                      schelp='true/false, if true will generate separate path groups per clock')
 
     modes = get_timing_modes(chip)
 
@@ -165,13 +169,13 @@ def post_process(chip):
                     metric = None
                 elif metric in ('holdslack', 'setupslack'):
                     if slack:
-                        record_metric(chip, step, index, metric, float(slack.group(1)),
+                        record_metric(chip, step, index, metric, float(slack.group(1).split()[-1]),
                                       __report_map(chip, metric, logfile),
                                       source_unit=timescale)
                         metric = None
                 elif metric in ('setuptns', 'holdtns'):
                     if tns:
-                        record_metric(chip, step, index, metric, float(tns.group(1)),
+                        record_metric(chip, step, index, metric, float(tns.group(1).split()[-1]),
                                       __report_map(chip, metric, logfile),
                                       source_unit=timescale)
                         metric = None

siliconcompiler/tools/yosys/sc_synth_asic.tcl

@@ -37,38 +37,46 @@ source "$sc_refdir/procs.tcl"
 ########################################################
 
 set input_verilog "inputs/$sc_design.v"
-if { [file exists $input_verilog] } {
-    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
-        # This needs some reordering of loaded to ensure blackboxes are handled
-        # before this
-        set slang_params []
-        if { [sc_cfg_exists option param] } {
-            dict for {key value} [sc_cfg_get option param] {
-                if { ![string is integer $value] } {
-                    set value [concat \"$value\"]
-                }
-
-                lappend slang_params -G "${key}=${value}"
+if { ![file exists $input_verilog] } {
+    set input_verilog []
+    if { [sc_cfg_exists input rtl systemverilog] } {
+        lappend input_verilog {*}[sc_cfg_get input rtl systemverilog]
+    }
+    if { [sc_cfg_exists input rtl verilog] } {
+        lappend input_verilog {*}[sc_cfg_get input rtl verilog]
+    }
+}
+
+if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+    # This needs some reordering of loaded to ensure blackboxes are handled
+    # before this
+    set slang_params []
+    if { [sc_cfg_exists option param] } {
+        dict for {key value} [sc_cfg_get option param] {
+            if { ![string is integer $value] } {
+                set value [concat \"$value\"]
             }
+
+            lappend slang_params -G "${key}=${value}"
         }
-        yosys read_slang \
-            -D SYNTHESIS \
-            --keep-hierarchy \
-            --top $sc_design \
-            {*}$slang_params \
-            $input_verilog
-    } else {
-        # Use -noblackbox to correctly interpret empty modules as empty,
-        # actual black boxes are read in later
-        # https://github.com/YosysHQ/yosys/issues/1468
-        yosys read_verilog -noblackbox -sv $input_verilog
+    }
+    yosys read_slang \
+        -D SYNTHESIS \
+        --keep-hierarchy \
+        --top $sc_design \
+        {*}$slang_params \
+        {*}$input_verilog
+} else {
+    # Use -noblackbox to correctly interpret empty modules as empty,
+    # actual black boxes are read in later
+    # https://github.com/YosysHQ/yosys/issues/1468
+    yosys read_verilog -noblackbox -sv {*}$input_verilog
 
-        ########################################################
-        # Override top level parameters
-        ########################################################
+    ########################################################
+    # Override top level parameters
+    ########################################################
 
-        sc_apply_params
-    }
+    sc_apply_params
 }
 
 ####################

siliconcompiler/tools/yosys/syn_asic.py

@@ -8,7 +8,7 @@ from siliconcompiler import utils
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
     CellArea
 from siliconcompiler.tools._common.asic_clock import get_clock_period
-from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools._common import get_tool_task, input_provides, add_require_input
 
 
 def make_docs(chip):
@@ -34,7 +34,16 @@ def setup(chip):
              step=step, index=index, clobber=False)
 
     # Input/output requirements.
-    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    if f'{design}.v' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    else:
+        added = False
+        added |= add_require_input(chip, 'input', 'rtl', 'systemverilog',
+                                   include_library_files=False)
+        added |= add_require_input(chip, 'input', 'rtl', 'verilog',
+                                   include_library_files=False)
+        if not added:
+            chip.add('tool', tool, 'task', task, 'require', 'input,rtl,verilog')
     chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
 

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "10c0e05959e169ec9740d83e80bb4f2395afcc7b",
+    "git-commit": "e78e29127134a0b95ebcd5661895c6dc4651e641",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -15,6 +15,11 @@
     "git-commit": "v1.84",
     "auto-update": true
   },
+  "opensta": {
+    "git-url": "https://github.com/parallaxsw/OpenSTA.git",
+    "git-commit": "109bc9ab5e35b830db9569f741db09e468704e6b",
+    "auto-update": true
+  },
   "netgen": {
     "git-url": "https://github.com/RTimothyEdwards/netgen.git",
     "git-commit": "fb7876c7a6f9d58a3d88a49e302e682c1d12e00d",
@@ -45,7 +50,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "e5effb5e1ea4e0cf9b4af2c769d364e0ed4b6d84",
+    "git-commit": "d30c7e7f4e9018b9d4a565207ff752460c81eeb4",
     "auto-update": true
   },
   "verilator": {
@@ -91,7 +96,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.51",
+    "git-commit": "v0.52",
     "version-prefix": "",
     "auto-update": true
   },
@@ -139,7 +144,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "e23228f4b4ec5ec0b4b17f1f675debfa29458665",
+    "git-commit": "a95ef24f0307230ae25ea6f2216d2fe8b8ece0be",
     "docker-depends": "yosys",
     "auto-update": true
   },

siliconcompiler/toolscripts/rhel8/install-chisel.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel8/install-icarus.sh

@@ -6,6 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
+sudo yum install -y wget git
 
 args=
 if [ ! -z ${PREFIX} ]; then

siliconcompiler/toolscripts/rhel8/install-klayout.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel8/install-magic.sh

@@ -6,8 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
-sudo yum install -y tcl-devel tk-devel tcsh csh
-# sudo apt-get install -y build-essential m4 tcsh csh libx11-dev tcl-dev tk-dev
+sudo yum install -y tcl-devel tk-devel tcsh csh git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel8/install-netgen.sh

@@ -6,7 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
-sudo yum install -y tcl-devel tk-devel
+sudo yum install -y tcl-devel tk-devel git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel8/install-slang.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y git
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel8/install-surelog.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y git
+
 # These dependencies are up-to-date with instructions from the INSTALL.md from the commit we are pinned to below
 sudo yum install -y gcc-toolset-12
 sudo dnf config-manager --set-enabled devel || true
@@ -17,7 +19,7 @@ cd deps
 python3 -m venv .surelog --clear
 . .surelog/bin/activate
 python3 -m pip install --upgrade pip
-python3 -m pip install cmake
+python3 -m pip install cmake==3.28.4
 python3 -m pip install orderedmultidict
 
 git clone $(python3 ${src_path}/_tools.py --tool surelog --field git-url) surelog

siliconcompiler/toolscripts/rhel8/install-sv2v.sh

@@ -8,6 +8,7 @@ src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 mkdir -p deps
 cd deps
 
+sudo yum install -y git curl
 sudo yum group install -y "Development Tools"
 sudo yum install -y gmp-devel xz
 

siliconcompiler/toolscripts/rhel8/install-verible.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel8/install-verilator.sh

@@ -6,6 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
+sudo yum install -y git wget
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel8/install-xyce.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel9/install-chisel.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel9/install-ghdl.sh

@@ -6,6 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum install -y gcc-gnat zlib-devel diffutils
+sudo yum install -y git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel9/install-gtkwave.sh

@@ -8,6 +8,7 @@ src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 sudo yum group install -y "Development Tools"
 sudo yum install -y gtk3-devel \
     bzip2-devel xz-devel tcl-devel tk-devel
+sudo yum install -y wget git
 sudo dnf config-manager --set-enabled devel || true
 sudo yum install -y Judy-devel
 sudo dnf config-manager --set-disabled devel || true

siliconcompiler/toolscripts/rhel9/install-icarus.sh

@@ -6,6 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
+sudo yum install -y wget git
 
 args=
 if [ ! -z ${PREFIX} ]; then

siliconcompiler/toolscripts/rhel9/install-klayout.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel9/install-magic.sh

@@ -6,8 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
-sudo yum install -y tcl-devel tk-devel tcsh csh
-# sudo apt-get install -y build-essential m4 tcsh csh libx11-dev tcl-dev tk-dev
+sudo yum install -y tcl-devel tk-devel tcsh csh git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel9/install-netgen.sh

@@ -6,7 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
-sudo yum install -y tcl-devel tk-devel
+sudo yum install -y tcl-devel tk-devel git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel9/install-openroad.sh

@@ -4,6 +4,8 @@ set -e
 
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y git
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel9/install-opensta.sh

@@ -0,0 +1,76 @@
+#!/bin/sh
+
+set -e
+
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+sudo yum install -y git gcc-c++ wget
+sudo yum install -y tcl-tclreadline-devel \
+    bison flex zlib-devel automake autoconf
+sudo yum install -y \
+    https://mirror.stream.centos.org/9-stream/AppStream/x86_64/os/Packages/flex-2.6.4-9.el9.x86_64.rpm \
+    https://mirror.stream.centos.org/9-stream/AppStream/x86_64/os/Packages/readline-devel-8.1-4.el9.x86_64.rpm \
+    https://rpmfind.net/linux/centos-stream/9-stream/AppStream/x86_64/os/Packages/tcl-devel-8.6.10-7.el9.x86_64.rpm
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .opensta --clear
+. .opensta/bin/activate
+python3 -m pip install cmake==3.31.6
+
+if [ ! -z ${PREFIX} ]; then
+    cmake_args="-DCMAKE_INSTALL_PREFIX=$PREFIX"
+    config_prefix="--prefix=$PREFIX"
+fi
+
+# eigen
+mkdir -p eigen3
+cd eigen3
+git clone --depth=1 -b 3.4 https://gitlab.com/libeigen/eigen.git
+cd eigen
+mkdir build
+cd build
+cmake $cmake_args ..
+make -j$(nproc)
+sudo make install
+
+cd ../../..
+# cudd
+mkdir -p cudd
+cd cudd
+git clone --depth=1 -b 3.0.0 https://github.com/The-OpenROAD-Project/cudd.git
+cd cudd
+autoreconf
+./configure $config_prefix
+make -j$(nproc)
+sudo make install
+
+cd ../..
+#swig
+wget -O swig.tar.gz https://github.com/swig/swig/archive/v4.1.0.tar.gz
+tar xfz swig.tar.gz
+cd swig-4.1.0
+
+wget https://github.com/PCRE2Project/pcre2/releases/download/pcre2-10.42/pcre2-10.42.tar.gz
+./Tools/pcre-build.sh
+
+./autogen.sh
+./configure $config_prefix
+make -j$(nproc)
+sudo make -j$(nproc) install
+
+cd ../..
+# opensta
+git clone $(python3 ${src_path}/_tools.py --tool opensta --field git-url) opensta
+cd opensta
+git checkout $(python3 ${src_path}/_tools.py --tool opensta --field git-commit)
+git submodule update --init --recursive
+
+mkdir -p build
+cd build
+cmake .. $cmake_args
+make -j$(nproc)
+sudo make install
+
+cd -

siliconcompiler/toolscripts/rhel9/install-slang.sh

@@ -5,13 +5,15 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y git
+
 mkdir -p deps
 cd deps
 
 python3 -m venv .slang --clear
 . .slang/bin/activate
 python3 -m pip install --upgrade pip
-python3 -m pip install cmake
+python3 -m pip install cmake==3.31.6
 
 sudo yum install -y gcc-toolset-12
 

siliconcompiler/toolscripts/rhel9/install-surelog.sh

@@ -10,6 +10,7 @@ sudo yum install -y gcc-toolset-12
 sudo dnf config-manager --set-enabled devel || true
 sudo yum install -y libuuid-devel java-11-openjdk-devel python3 zlib-static openssl-devel 
 sudo dnf config-manager --set-disabled devel || true
+sudo yum install -y git
 
 mkdir -p deps
 cd deps
@@ -17,7 +18,7 @@ cd deps
 python3 -m venv .surelog --clear
 . .surelog/bin/activate
 python3 -m pip install --upgrade pip
-python3 -m pip install cmake
+python3 -m pip install cmake==3.31.6
 python3 -m pip install orderedmultidict
 
 git clone $(python3 ${src_path}/_tools.py --tool surelog --field git-url) surelog