siliconcompiler 0.32.1__py3-none-any.whl → 0.32.2__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl

@@ -15,6 +15,11 @@ source -echo "$sc_refdir/apr/preamble.tcl"
 # Timing Repair
 ###############################
 
+set parasitics_stage -placement
+if { false } {
+    set parasitics_stage -global_routing
+}
+
 set rsz_setup_slack_margin [lindex [sc_cfg_tool_task_get {var} rsz_setup_slack_margin] 0]
 set rsz_hold_slack_margin [lindex [sc_cfg_tool_task_get {var} rsz_hold_slack_margin] 0]
 set rsz_slew_margin [lindex [sc_cfg_tool_task_get {var} rsz_slew_margin] 0]
@@ -30,6 +35,42 @@ if { [lindex [sc_cfg_tool_task_get {var} rsz_skip_gate_cloning] 0] == "true" } {
     lappend repair_timing_args "-skip_gate_cloning"
 }
 
+set repair_design_args []
+set rsz_cap_margin [lindex [sc_cfg_tool_task_get {var} rsz_cap_margin] 0]
+if { $rsz_cap_margin != "false" } {
+    lappend repair_design_args "-cap_margin" $rsz_cap_margin
+}
+set rsz_slew_margin [lindex [sc_cfg_tool_task_get {var} rsz_slew_margin] 0]
+if { $rsz_slew_margin != "false" } {
+    lappend repair_design_args "-slew_margin" $rsz_slew_margin
+}
+
+set total_insts [llength [[ord::get_db_block] getInsts]]
+# Remove filler cells before attempting to repair timing
+remove_fillers
+set removed_fillers [expr { $total_insts - [llength [[ord::get_db_block] getInsts]] }]
+
+if { [lindex [sc_cfg_tool_task_get var rsz_skip_drv_repair] 0] != "true" } {
+    ###############################
+    # DRV Repair
+    ###############################
+
+    # Enable ffs for resizing
+    sc_set_dont_use -scanchain -multibit -report dont_use.repair_timing.drv
+
+    estimate_parasitics $parasitics_stage
+
+    sc_report_args -command repair_design -args $repair_design_args
+    repair_design \
+        -verbose \
+        {*}$repair_design_args
+
+    sc_detailed_placement -congestion_report reports/congestion.drv.rpt
+
+    # Restore dont use
+    sc_set_dont_use
+}
+
 if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
     ###############################
     # Setup Repair
@@ -38,7 +79,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
     # Enable ffs for resizing
     sc_set_dont_use -scanchain -multibit -report dont_use.repair_timing.setup
 
-    estimate_parasitics -placement
+    estimate_parasitics $parasitics_stage
 
     sc_report_args -command repair_timing -args $repair_timing_args
     repair_timing \
@@ -49,7 +90,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
         -repair_tns $rsz_repair_tns \
         {*}$repair_timing_args
 
-    sc_detailed_placement
+    sc_detailed_placement -congestion_report reports/congestion.setup_repair.rpt
 
     # Restore dont use
     sc_set_dont_use
@@ -60,7 +101,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
     # Hold Repair
     ###############################
 
-    estimate_parasitics -placement
+    estimate_parasitics $parasitics_stage
 
     # Enable hold cells
     sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.hold
@@ -74,7 +115,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
         -repair_tns $rsz_repair_tns \
         {*}$repair_timing_args
 
-    sc_detailed_placement
+    sc_detailed_placement -congestion_report reports/congestion.hold_repair.rpt
 
     # Restore dont use
     sc_set_dont_use
@@ -85,7 +126,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_recover_power] 0] != "true" } {
     # Recover power
     ###############################
 
-    estimate_parasitics -placement
+    estimate_parasitics $parasitics_stage
 
     # Enable cells
     sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.power
@@ -98,16 +139,21 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_recover_power] 0] != "true" } {
         -hold_margin $rsz_hold_slack_margin \
         {*}$repair_timing_args
 
-    sc_detailed_placement
+    sc_detailed_placement -congestion_report reports/congestion.power_recovery.rpt
 
     # Restore dont use
     sc_set_dont_use
 }
 
+if { $removed_fillers > 0 } {
+    # Add filler cells back
+    sc_insert_fillers
+}
+
 global_connect
 
 # estimate for metrics
-estimate_parasitics -placement
+estimate_parasitics $parasitics_stage
 
 ###############################
 # Task Postamble

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -97,7 +97,12 @@ proc sc_global_placement { args } {
 # Detailed Placement
 ###########################
 
-proc sc_detailed_placement { } {
+proc sc_detailed_placement { args } {
+    sta::parse_key_args "sc_detailed_placement" args \
+        keys {-congestion_report} \
+        flags {}
+    sta::check_argc_eq0 "sc_detailed_placement" $args
+
     set dpl_padding [lindex [sc_cfg_tool_task_get var pad_detail_place] 0]
     set dpl_disallow_one_site [lindex [sc_cfg_tool_task_get var dpl_disallow_one_site] 0]
     set dpl_max_displacement [lindex [sc_cfg_tool_task_get var dpl_max_displacement] 0]
@@ -111,10 +116,23 @@ proc sc_detailed_placement { } {
         lappend dpl_args "-disallow_one_site_gaps"
     }
 
+    set incremental_route false
+
+    if { $incremental_route } {
+        global_route -start_incremental
+    }
+
     sc_report_args -command detailed_placement -args $dpl_args
+
     detailed_placement \
         -max_displacement $dpl_max_displacement \
         {*}$dpl_args
+
+    if { $incremental_route } {
+        global_route -end_incremental \
+            -congestion_report_file $keys(-congestion_report)
+    }
+
     check_placement -verbose
 }
 

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -112,13 +112,24 @@ if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
     }
     if { $fmax_metric == 0 } {
         # attempt to compute based on combinatorial path
+        set fmax_valid true
         set max_path [find_timing_paths -unconstrained -path_delay max]
-        set max_path_delay [$max_path data_arrival_time]
+        if { $max_path == "" } {
+            set fmax_valid false
+        } else {
+            set max_path_delay [$max_path data_arrival_time]
+        }
         set min_path [find_timing_paths -unconstrained -path_delay min]
-        set min_path_delay [$min_path data_arrival_time]
-        set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
-        if { $path_delay > 0 } {
-            set fmax_metric [expr { 1.0 / $path_delay }]
+        if { $min_path == "" } {
+            set fmax_valid false
+        } else {
+            set min_path_delay [$min_path data_arrival_time]
+        }
+        if { $fmax_valid } {
+            set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
+            if { $path_delay > 0 } {
+                set fmax_metric [expr { 1.0 / $path_delay }]
+            }
         }
     }
     if { $fmax_metric > 0 } {

siliconcompiler/tools/slang/__init__.py

@@ -151,7 +151,7 @@ def _get_driver(chip, options_func, ignored_diagnotics=None):
             driver.diagEngine.setSeverity(
                 getattr(pyslang.Diags, warning),
                 pyslang.DiagnosticSeverity.Ignored)
-        elif not chip.get('option', 'quiet', step=step, index=index):
+        else:
             chip.logger.warning(f'{warning} is not a valid slang category')
 
     if not ignored_diagnotics:
@@ -200,13 +200,12 @@ def _diagnostics(chip, driver, compilation):
 
                     report[report_level].append(line)
 
-    if not chip.get('option', 'quiet', step=step, index=index):
-        if report["warning"]:
-            for line in report["warning"]:
-                chip.logger.warning(line)
-        if report["error"]:
-            for line in report["error"]:
-                chip.logger.error(line)
+    if report["warning"]:
+        for line in report["warning"]:
+            chip.logger.warning(line)
+    if report["error"]:
+        for line in report["error"]:
+            chip.logger.error(line)
 
     diags.clearCounts()
     for diag in compilation.getAllDiagnostics():

siliconcompiler/tools/sv2v/sv2v.py

@@ -26,7 +26,10 @@ def make_docs(chip):
 
 def parse_version(stdout):
     # 0.0.7-130-g1aa30ea
-    return '-'.join(stdout.split('-')[:-1])
+    stdout = stdout.strip()
+    if '-' in stdout:
+        return '-'.join(stdout.split('-')[:-1])
+    return stdout
 
 
 ##################################################

siliconcompiler/tools/yosys/__init__.py

@@ -34,12 +34,9 @@ def setup(chip):
     ''' Tool specific function to run before step execution
     '''
 
-    # If the 'lock' bit is set, don't reconfigure.
-    tool = 'yosys'
-    refdir = 'tools/' + tool
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
     # Standard Setup
     chip.set('tool', tool, 'exe', 'yosys')
@@ -54,7 +51,8 @@ def setup(chip):
         option.append('-C')
     option.append('-c')
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
-    chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
+    chip.set('tool', tool, 'task', task, 'refdir', os.path.join('tools', tool),
+             step=step, index=index,
              package='siliconcompiler', clobber=False)
     chip.set('tool', tool, 'task', task, 'regex', 'warnings', "Warning:",
              step=step, index=index, clobber=False)
@@ -76,38 +74,8 @@ def normalize_version(version):
     return version.replace('+', '-')
 
 
-def syn_setup(chip):
-    ''' Helper method for configs specific to synthesis tasks.
-    '''
-
-    # Generic tool setup.
-    setup(chip)
-
-    tool = 'yosys'
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
-    design = chip.top()
-
-    # Set yosys script path.
-    chip.set('tool', tool, 'task', task, 'script', 'sc_syn.tcl',
-             step=step, index=index, clobber=False)
-
-    # Input/output requirements.
-    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
-    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
-
-    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
-             step=step, index=index,
-             clobber=False)
-    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
-             'true/false, if true will attempt to use the slang frontend',
-             field='help')
-
-
 ##################################################
-def syn_post_process(chip):
+def synth_post_process(chip):
     ''' Tool specific function to run after step execution
     '''
 

siliconcompiler/tools/yosys/lec.py

@@ -1,7 +1,7 @@
 import re
 
 from siliconcompiler.tools.yosys import setup as setup_tool
-from siliconcompiler.tools.yosys.syn_asic import setup_asic, prepare_synthesis_libraries
+from siliconcompiler.tools.yosys.syn_asic import prepare_synthesis_libraries, setup_asic
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric, input_provides
 
@@ -14,13 +14,12 @@ def setup(chip):
     # Generic tool setup.
     setup_tool(chip)
 
-    # Generic setup.
+    # Setup for asic
     setup_asic(chip)
 
-    tool = 'yosys'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
     design = chip.top()
 
     # Set yosys script path.

siliconcompiler/tools/yosys/{syn_asic.tcl → sc_synth_asic.tcl}

@@ -1,3 +1,76 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+yosys echo on
+
+###############################
+# Schema Adapter
+###############################
+
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_design [sc_top]
+set sc_flow [sc_cfg_get option flow]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
+
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
+########################################################
+# Design Inputs
+########################################################
+
+set input_verilog "inputs/$sc_design.v"
+if { [file exists $input_verilog] } {
+    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+        # This needs some reordering of loaded to ensure blackboxes are handled
+        # before this
+        set slang_params []
+        if { [sc_cfg_exists option param] } {
+            dict for {key value} [sc_cfg_get option param] {
+                if { ![string is integer $value] } {
+                    set value [concat \"$value\"]
+                }
+
+                lappend slang_params -G "${key}=${value}"
+            }
+        }
+        yosys read_slang \
+            -D SYNTHESIS \
+            --keep-hierarchy \
+            --top $sc_design \
+            {*}$slang_params \
+            $input_verilog
+    } else {
+        # Use -noblackbox to correctly interpret empty modules as empty,
+        # actual black boxes are read in later
+        # https://github.com/YosysHQ/yosys/issues/1468
+        yosys read_verilog -noblackbox -sv $input_verilog
+
+        ########################################################
+        # Override top level parameters
+        ########################################################
+
+        sc_apply_params
+    }
+}
+
 ####################
 # Helper functions
 ####################
@@ -416,3 +489,9 @@ foreach lib_file "$sc_libraries $sc_macro_libraries" {
 yosys echo off
 yosys tee -o ./reports/stat.json stat -json -top $sc_design {*}$stat_libs
 yosys echo on
+
+########################################################
+# Write Netlist
+########################################################
+yosys write_verilog -noexpr -nohex -nodec "outputs/${sc_design}.vg"
+yosys write_json "outputs/${sc_design}.netlist.json"

siliconcompiler/tools/yosys/{syn_fpga.tcl → sc_synth_fpga.tcl}

@@ -1,3 +1,79 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+yosys echo on
+
+###############################
+# Schema Adapter
+###############################
+
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_design [sc_top]
+set sc_flow [sc_cfg_get option flow]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
+
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
+########################################################
+# Design Inputs
+########################################################
+
+# TODO: the original OpenFPGA synth script used read_verilog with -nolatches. Is
+# that a flag we might want here?
+
+set input_verilog "inputs/$sc_design.v"
+if { [file exists $input_verilog] } {
+    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+        # This needs some reordering of loaded to ensure blackboxes are handled
+        # before this
+        set slang_params []
+        if { [sc_cfg_exists option param] } {
+            dict for {key value} [sc_cfg_get option param] {
+                if { ![string is integer $value] } {
+                    set value [concat \"$value\"]
+                }
+
+                lappend slang_params -G "${key}=${value}"
+            }
+        }
+        yosys read_slang \
+            -D SYNTHESIS \
+            --keep-hierarchy \
+            --top $sc_design \
+            {*}$slang_params \
+            $input_verilog
+    } else {
+        # Use -noblackbox to correctly interpret empty modules as empty,
+        # actual black boxes are read in later
+        # https://github.com/YosysHQ/yosys/issues/1468
+        yosys read_verilog -noblackbox -sv $input_verilog
+
+        ########################################################
+        # Override top level parameters
+        ########################################################
+
+        sc_apply_params
+    }
+}
+
 ####################
 # Helper functions
 ####################
@@ -241,4 +317,6 @@ yosys echo on
 ########################################################
 # Write Netlist
 ########################################################
+yosys write_verilog -noexpr -nohex -nodec "outputs/${sc_design}.vg"
+yosys write_json "outputs/${sc_design}.netlist.json"
 yosys write_blif "outputs/${sc_design}.blif"

siliconcompiler/tools/yosys/syn_asic.py

@@ -1,5 +1,4 @@
-
-from siliconcompiler.tools.yosys import syn_setup, syn_post_process
+from siliconcompiler.tools.yosys import synth_post_process, setup as tool_setup
 import os
 import json
 import re
@@ -22,22 +21,39 @@ def setup(chip):
     Perform ASIC synthesis
     '''
 
+    tool_setup(chip)
+
     # Generic synthesis task setup.
-    syn_setup(chip)
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    # Set yosys script path.
+    chip.set('tool', tool, 'task', task, 'script', 'sc_synth_asic.tcl',
+             step=step, index=index, clobber=False)
+
+    # Input/output requirements.
+    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
+             'true/false, if true will attempt to use the slang frontend',
+             field='help')
 
-    # ASIC-specific setup.
     setup_asic(chip)
 
 
 def setup_asic(chip):
-    ''' Helper method for configs specific to ASIC steps (both syn and lec).
-    '''
-
-    tool = 'yosys'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
+    # Setup ASIC params
     chip.add('tool', tool, 'task', task, 'require',
              ",".join(['asic', 'logiclib']),
              step=step, index=index)
@@ -506,7 +522,7 @@ def pre_process(chip):
 
 
 def post_process(chip):
-    syn_post_process(chip)
+    synth_post_process(chip)
     _generate_cell_area_report(chip)
 
 

siliconcompiler/tools/yosys/syn_fpga.py

@@ -1,4 +1,4 @@
-from siliconcompiler.tools.yosys import syn_setup, syn_post_process
+from siliconcompiler.tools.yosys import synth_post_process, setup as tool_setup
 import json
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
@@ -18,23 +18,32 @@ def setup(chip):
     Perform FPGA synthesis
     '''
 
-    # Generic synthesis task setup.
-    syn_setup(chip)
-
-    # FPGA-specific setup.
-    setup_fpga(chip)
-
+    tool_setup(chip)
 
-def setup_fpga(chip):
-    ''' Helper method for configs specific to FPGA steps (both syn and lec).
-    '''
-
-    tool = 'yosys'
+    # Generic synthesis task setup.
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
     design = chip.top()
 
+    # Set yosys script path.
+    chip.set('tool', tool, 'task', task, 'script', 'sc_synth_fpga.tcl',
+             step=step, index=index, clobber=False)
+
+    # Input/output requirements.
+    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.blif', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
+             'true/false, if true will attempt to use the slang frontend',
+             field='help')
+
+    # Setup FPGA params
     part_name = chip.get('fpga', 'partname')
 
     # Require that a lut size is set for FPGA scripts.
@@ -93,8 +102,6 @@ def setup_fpga(chip):
                  ",".join(['fpga', part_name, 'file', 'yosys_memory_techmap']),
                  step=step, index=index)
 
-    chip.add('tool', tool, 'task', task, 'output', design + '.blif', step=step, index=index)
-
 
 ##################################################
 def post_process(chip):
@@ -102,7 +109,7 @@ def post_process(chip):
     index = chip.get('arg', 'index')
     part_name = chip.get('fpga', 'partname')
 
-    syn_post_process(chip)
+    synth_post_process(chip)
 
     with sc_open("reports/stat.json") as f:
         metrics = json.load(f)