siliconcompiler 0.32.0__py3-none-any.whl → 0.32.2__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -112,13 +112,24 @@ if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
     }
     if { $fmax_metric == 0 } {
         # attempt to compute based on combinatorial path
+        set fmax_valid true
         set max_path [find_timing_paths -unconstrained -path_delay max]
-        set max_path_delay [$max_path data_arrival_time]
+        if { $max_path == "" } {
+            set fmax_valid false
+        } else {
+            set max_path_delay [$max_path data_arrival_time]
+        }
         set min_path [find_timing_paths -unconstrained -path_delay min]
-        set min_path_delay [$min_path data_arrival_time]
-        set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
-        if { $path_delay > 0 } {
-            set fmax_metric [expr { 1.0 / $path_delay }]
+        if { $min_path == "" } {
+            set fmax_valid false
+        } else {
+            set min_path_delay [$min_path data_arrival_time]
+        }
+        if { $fmax_valid } {
+            set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
+            if { $path_delay > 0 } {
+                set fmax_metric [expr { 1.0 / $path_delay }]
+            }
         }
     }
     if { $fmax_metric > 0 } {

siliconcompiler/tools/slang/__init__.py

@@ -151,7 +151,7 @@ def _get_driver(chip, options_func, ignored_diagnotics=None):
             driver.diagEngine.setSeverity(
                 getattr(pyslang.Diags, warning),
                 pyslang.DiagnosticSeverity.Ignored)
-        elif not chip.get('option', 'quiet', step=step, index=index):
+        else:
             chip.logger.warning(f'{warning} is not a valid slang category')
 
     if not ignored_diagnotics:
@@ -200,13 +200,12 @@ def _diagnostics(chip, driver, compilation):
 
                     report[report_level].append(line)
 
-    if not chip.get('option', 'quiet', step=step, index=index):
-        if report["warning"]:
-            for line in report["warning"]:
-                chip.logger.warning(line)
-        if report["error"]:
-            for line in report["error"]:
-                chip.logger.error(line)
+    if report["warning"]:
+        for line in report["warning"]:
+            chip.logger.warning(line)
+    if report["error"]:
+        for line in report["error"]:
+            chip.logger.error(line)
 
     diags.clearCounts()
     for diag in compilation.getAllDiagnostics():

siliconcompiler/tools/sv2v/sv2v.py

@@ -26,7 +26,10 @@ def make_docs(chip):
 
 def parse_version(stdout):
     # 0.0.7-130-g1aa30ea
-    return '-'.join(stdout.split('-')[:-1])
+    stdout = stdout.strip()
+    if '-' in stdout:
+        return '-'.join(stdout.split('-')[:-1])
+    return stdout
 
 
 ##################################################

siliconcompiler/tools/yosys/__init__.py

@@ -34,12 +34,9 @@ def setup(chip):
     ''' Tool specific function to run before step execution
     '''
 
-    # If the 'lock' bit is set, don't reconfigure.
-    tool = 'yosys'
-    refdir = 'tools/' + tool
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
     # Standard Setup
     chip.set('tool', tool, 'exe', 'yosys')
@@ -54,7 +51,8 @@ def setup(chip):
         option.append('-C')
     option.append('-c')
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
-    chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
+    chip.set('tool', tool, 'task', task, 'refdir', os.path.join('tools', tool),
+             step=step, index=index,
              package='siliconcompiler', clobber=False)
     chip.set('tool', tool, 'task', task, 'regex', 'warnings', "Warning:",
              step=step, index=index, clobber=False)
@@ -76,38 +74,8 @@ def normalize_version(version):
     return version.replace('+', '-')
 
 
-def syn_setup(chip):
-    ''' Helper method for configs specific to synthesis tasks.
-    '''
-
-    # Generic tool setup.
-    setup(chip)
-
-    tool = 'yosys'
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
-    design = chip.top()
-
-    # Set yosys script path.
-    chip.set('tool', tool, 'task', task, 'script', 'sc_syn.tcl',
-             step=step, index=index, clobber=False)
-
-    # Input/output requirements.
-    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
-    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
-
-    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
-             step=step, index=index,
-             clobber=False)
-    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
-             'true/false, if true will attempt to use the slang frontend',
-             field='help')
-
-
 ##################################################
-def syn_post_process(chip):
+def synth_post_process(chip):
     ''' Tool specific function to run after step execution
     '''
 

siliconcompiler/tools/yosys/lec.py

@@ -1,7 +1,7 @@
 import re
 
 from siliconcompiler.tools.yosys import setup as setup_tool
-from siliconcompiler.tools.yosys.syn_asic import setup_asic, prepare_synthesis_libraries
+from siliconcompiler.tools.yosys.syn_asic import prepare_synthesis_libraries, setup_asic
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric, input_provides
 
@@ -14,13 +14,12 @@ def setup(chip):
     # Generic tool setup.
     setup_tool(chip)
 
-    # Generic setup.
+    # Setup for asic
     setup_asic(chip)
 
-    tool = 'yosys'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
     design = chip.top()
 
     # Set yosys script path.

siliconcompiler/tools/yosys/{syn_asic.tcl → sc_synth_asic.tcl}

@@ -1,3 +1,76 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+yosys echo on
+
+###############################
+# Schema Adapter
+###############################
+
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_design [sc_top]
+set sc_flow [sc_cfg_get option flow]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
+
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
+########################################################
+# Design Inputs
+########################################################
+
+set input_verilog "inputs/$sc_design.v"
+if { [file exists $input_verilog] } {
+    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+        # This needs some reordering of loaded to ensure blackboxes are handled
+        # before this
+        set slang_params []
+        if { [sc_cfg_exists option param] } {
+            dict for {key value} [sc_cfg_get option param] {
+                if { ![string is integer $value] } {
+                    set value [concat \"$value\"]
+                }
+
+                lappend slang_params -G "${key}=${value}"
+            }
+        }
+        yosys read_slang \
+            -D SYNTHESIS \
+            --keep-hierarchy \
+            --top $sc_design \
+            {*}$slang_params \
+            $input_verilog
+    } else {
+        # Use -noblackbox to correctly interpret empty modules as empty,
+        # actual black boxes are read in later
+        # https://github.com/YosysHQ/yosys/issues/1468
+        yosys read_verilog -noblackbox -sv $input_verilog
+
+        ########################################################
+        # Override top level parameters
+        ########################################################
+
+        sc_apply_params
+    }
+}
+
 ####################
 # Helper functions
 ####################
@@ -416,3 +489,9 @@ foreach lib_file "$sc_libraries $sc_macro_libraries" {
 yosys echo off
 yosys tee -o ./reports/stat.json stat -json -top $sc_design {*}$stat_libs
 yosys echo on
+
+########################################################
+# Write Netlist
+########################################################
+yosys write_verilog -noexpr -nohex -nodec "outputs/${sc_design}.vg"
+yosys write_json "outputs/${sc_design}.netlist.json"

siliconcompiler/tools/yosys/{syn_fpga.tcl → sc_synth_fpga.tcl}

@@ -1,3 +1,79 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+yosys echo on
+
+###############################
+# Schema Adapter
+###############################
+
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_design [sc_top]
+set sc_flow [sc_cfg_get option flow]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
+
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
+########################################################
+# Design Inputs
+########################################################
+
+# TODO: the original OpenFPGA synth script used read_verilog with -nolatches. Is
+# that a flag we might want here?
+
+set input_verilog "inputs/$sc_design.v"
+if { [file exists $input_verilog] } {
+    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+        # This needs some reordering of loaded to ensure blackboxes are handled
+        # before this
+        set slang_params []
+        if { [sc_cfg_exists option param] } {
+            dict for {key value} [sc_cfg_get option param] {
+                if { ![string is integer $value] } {
+                    set value [concat \"$value\"]
+                }
+
+                lappend slang_params -G "${key}=${value}"
+            }
+        }
+        yosys read_slang \
+            -D SYNTHESIS \
+            --keep-hierarchy \
+            --top $sc_design \
+            {*}$slang_params \
+            $input_verilog
+    } else {
+        # Use -noblackbox to correctly interpret empty modules as empty,
+        # actual black boxes are read in later
+        # https://github.com/YosysHQ/yosys/issues/1468
+        yosys read_verilog -noblackbox -sv $input_verilog
+
+        ########################################################
+        # Override top level parameters
+        ########################################################
+
+        sc_apply_params
+    }
+}
+
 ####################
 # Helper functions
 ####################
@@ -241,4 +317,6 @@ yosys echo on
 ########################################################
 # Write Netlist
 ########################################################
+yosys write_verilog -noexpr -nohex -nodec "outputs/${sc_design}.vg"
+yosys write_json "outputs/${sc_design}.netlist.json"
 yosys write_blif "outputs/${sc_design}.blif"

siliconcompiler/tools/yosys/syn_asic.py

@@ -1,5 +1,4 @@
-
-from siliconcompiler.tools.yosys import syn_setup, syn_post_process
+from siliconcompiler.tools.yosys import synth_post_process, setup as tool_setup
 import os
 import json
 import re
@@ -22,22 +21,39 @@ def setup(chip):
     Perform ASIC synthesis
     '''
 
+    tool_setup(chip)
+
     # Generic synthesis task setup.
-    syn_setup(chip)
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    # Set yosys script path.
+    chip.set('tool', tool, 'task', task, 'script', 'sc_synth_asic.tcl',
+             step=step, index=index, clobber=False)
+
+    # Input/output requirements.
+    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
+             'true/false, if true will attempt to use the slang frontend',
+             field='help')
 
-    # ASIC-specific setup.
     setup_asic(chip)
 
 
 def setup_asic(chip):
-    ''' Helper method for configs specific to ASIC steps (both syn and lec).
-    '''
-
-    tool = 'yosys'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
+    # Setup ASIC params
     chip.add('tool', tool, 'task', task, 'require',
              ",".join(['asic', 'logiclib']),
              step=step, index=index)
@@ -506,7 +522,7 @@ def pre_process(chip):
 
 
 def post_process(chip):
-    syn_post_process(chip)
+    synth_post_process(chip)
     _generate_cell_area_report(chip)
 
 

siliconcompiler/tools/yosys/syn_fpga.py

@@ -1,4 +1,4 @@
-from siliconcompiler.tools.yosys import syn_setup, syn_post_process
+from siliconcompiler.tools.yosys import synth_post_process, setup as tool_setup
 import json
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
@@ -18,23 +18,32 @@ def setup(chip):
     Perform FPGA synthesis
     '''
 
-    # Generic synthesis task setup.
-    syn_setup(chip)
-
-    # FPGA-specific setup.
-    setup_fpga(chip)
-
+    tool_setup(chip)
 
-def setup_fpga(chip):
-    ''' Helper method for configs specific to FPGA steps (both syn and lec).
-    '''
-
-    tool = 'yosys'
+    # Generic synthesis task setup.
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
     design = chip.top()
 
+    # Set yosys script path.
+    chip.set('tool', tool, 'task', task, 'script', 'sc_synth_fpga.tcl',
+             step=step, index=index, clobber=False)
+
+    # Input/output requirements.
+    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.blif', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
+             'true/false, if true will attempt to use the slang frontend',
+             field='help')
+
+    # Setup FPGA params
     part_name = chip.get('fpga', 'partname')
 
     # Require that a lut size is set for FPGA scripts.
@@ -93,8 +102,6 @@ def setup_fpga(chip):
                  ",".join(['fpga', part_name, 'file', 'yosys_memory_techmap']),
                  step=step, index=index)
 
-    chip.add('tool', tool, 'task', task, 'output', design + '.blif', step=step, index=index)
-
 
 ##################################################
 def post_process(chip):
@@ -102,7 +109,7 @@ def post_process(chip):
     index = chip.get('arg', 'index')
     part_name = chip.get('fpga', 'partname')
 
-    syn_post_process(chip)
+    synth_post_process(chip)
 
     with sc_open("reports/stat.json") as f:
         metrics = json.load(f)

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "0fbd4d94c81ef070249ad9d9037a740d0c6e58fa",
+    "git-commit": "10c0e05959e169ec9740d83e80bb4f2395afcc7b",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -22,7 +22,7 @@
   },
   "ghdl": {
     "git-url": "https://github.com/ghdl/ghdl.git",
-    "git-commit": "v4.1.0",
+    "git-commit": "v5.0.1",
     "auto-update": false
   },
   "magic": {
@@ -36,7 +36,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.29.12",
+    "version": "0.30.0",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -45,7 +45,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "5d5723f65dd4501d17004736d7d048bea7ef2339",
+    "git-commit": "e5effb5e1ea4e0cf9b4af2c769d364e0ed4b6d84",
     "auto-update": true
   },
   "verilator": {
@@ -66,17 +66,17 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "v9.0.0",
+    "git-commit": "2a4e92181280a235315621253d1dc9eb8826bc53",
     "auto-update": false
   },
   "icepack": {
     "git-url": "https://github.com/YosysHQ/icestorm.git",
-    "git-commit": "d20a5e9001f46262bf0cef220f1a6943946e421d",
+    "git-commit": "7fbf8c0afbcf7665c45499b090409859b1815184",
     "auto-update": false
   },
   "nextpnr": {
     "git-url": "https://github.com/YosysHQ/nextpnr.git",
-    "git-commit": "f89b959b5f56ba8d91e1e7f8a645b267a5a7bb89",
+    "git-commit": "nextpnr-0.7",
     "docker-depends": "icepack"
   },
   "chisel": {
@@ -91,7 +91,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.50",
+    "git-commit": "v0.51",
     "version-prefix": "",
     "auto-update": true
   },
@@ -139,7 +139,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "8f2239b2b12dac43f8f47f56deef1095d5262fa2",
+    "git-commit": "e23228f4b4ec5ec0b4b17f1f675debfa29458665",
     "docker-depends": "yosys",
     "auto-update": true
   },
@@ -148,5 +148,14 @@
     "git-commit": "5dd1d8a60d0cc7228be856350bb90faad24dae9e",
     "docker-depends": "yosys",
     "auto-update": true
+  },
+  "yosys-parmys": {
+    "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
+    "git-commit": "2a4e92181280a235315621253d1dc9eb8826bc53",
+    "docker-depends": [
+      "yosys",
+      "vpr"
+    ],
+    "auto-update": false
   }
 }

siliconcompiler/toolscripts/rhel9/install-gtkwave.sh

@@ -35,6 +35,6 @@ git checkout $(python3 ${src_path}/_tools.py --tool gtkwave --field git-commit)
 cd gtkwave3-gtk3
 
 ./autogen.sh
-./configure --enable-gtk3 $args
+LDFLAGS="-ltcl -ltk" ./configure --enable-gtk3 $args
 make -j$(nproc)
 sudo make install

siliconcompiler/toolscripts/rhel9/install-vpr.sh

@@ -0,0 +1,29 @@
+#!/bin/sh
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool vpr --field git-url) vpr
+cd vpr
+git checkout $(python3 ${src_path}/_tools.py --tool vpr --field git-commit)
+git submodule update --init --recursive
+
+sudo dnf config-manager --set-enabled devel || true
+./install_dnf_packages.sh
+
+sudo yum install -y tbb-devel
+sudo dnf config-manager --set-disabled devel || true
+
+args=
+if [ ! -z ${PREFIX} ]; then
+    args="-DCMAKE_INSTALL_PREFIX=$PREFIX"
+fi
+
+make CMAKE_PARAMS="$args -DWITH_PARMYS=OFF -DWITH_ABC=OFF -DYOSYS_F4PGA_PLUGINS=OFF" -j$(nproc)
+cd build
+sudo make install

siliconcompiler/toolscripts/rhel9/install-yosys-parmys.sh

@@ -0,0 +1,59 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-parmys --field git-url) yosys-parmys
+cd yosys-parmys
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-parmys --field git-commit)
+git submodule update --init --recursive
+
+# apply patch
+cat > build_patch <<EOF
+diff --git a/parmys/parmys-plugin/Makefile b/parmys/parmys-plugin/Makefile
+index dbb3eb11e..cb85631bc 100644
+--- a/parmys/parmys-plugin/Makefile
++++ b/parmys/parmys-plugin/Makefile
+@@ -49,7 +49,7 @@ VTR_INSTALL_DIR ?= /usr/local
+ 
+ include ../Makefile_plugin.common
+ 
+-CXXFLAGS += -std=c++14 -Wall -W -Wextra \\
++CXXFLAGS += -std=c++17 -Wall -W -Wextra \\
+             -Wno-deprecated-declarations \\
+             -Wno-unused-parameter \\
+             -I. \\
+diff --git a/parmys/parmys-plugin/parmys_update.cc b/parmys/parmys-plugin/parmys_update.cc
+index ef55213c5..4e4d6dd15 100644
+--- a/parmys/parmys-plugin/parmys_update.cc
++++ b/parmys/parmys-plugin/parmys_update.cc
+@@ -506,9 +506,9 @@ void define_logical_function_yosys(nnode_t *node, Module *module)
+         lutptr = &cell->parameters.at(ID::LUT);
+         for (int i = 0; i < (1 << node->num_input_pins); i++) {
+             if (i == 3 || i == 5 || i == 6 || i == 7) //"011 1\n101 1\n110 1\n111 1\n"
+-                lutptr->bits.at(i) = RTLIL::State::S1;
++                lutptr->bits().at(i) = RTLIL::State::S1;
+             else
+-                lutptr->bits.at(i) = RTLIL::State::S0;
++                lutptr->bits().at(i) = RTLIL::State::S0;
+         }
+     } else {
+         cell->parameters[ID::A_WIDTH] = RTLIL::Const(int(node->num_input_pins));
+EOF
+
+git apply build_patch
+
+export VTR_INSTALL_DIR=$(dirname $(which vpr))/..
+YOSYS_PLUGIN=$(yosys-config --datdir)/plugins/
+
+cd parmys
+
+make -j$(nproc)
+sudo mkdir -p $YOSYS_PLUGIN
+sudo cp parmys-plugin/build/parmys.so $YOSYS_PLUGIN
+cd -