siliconcompiler 0.31.0__py3-none-any.whl → 0.32.0__py3-none-any.whl

siliconcompiler/tools/slang/__init__.py

@@ -10,55 +10,56 @@ Sources: https://github.com/MikePopoloski/slang
 
 Installation: https://sv-lang.com/building.html
 '''
-import re
-from siliconcompiler import sc_open
-from siliconcompiler.tools._common import record_metric
+import os
+
+try:
+    import pyslang
+except ModuleNotFoundError:
+    pyslang = None
+
 from siliconcompiler.tools._common import \
-    get_frontend_options, get_input_files, get_tool_task
+    add_require_input, add_frontend_requires, get_frontend_options, get_input_files, \
+    get_tool_task, record_metric
 
 
-################################
-# Setup Tool (pre executable)
-################################
-def setup(chip):
-    tool = 'slang'
+def has_pyslang():
+    return pyslang is not None
 
-    # Standard Setup
-    chip.set('tool', tool, 'exe', 'slang')
-    chip.set('tool', tool, 'vswitch', '--version')
-    chip.set('tool', tool, 'version', '>=6.0', clobber=False)
 
+def test_version():
+    if not has_pyslang():
+        return "pyslang is not installed"
 
-def parse_version(stdout):
-    # slang --version output looks like:
-    # slang version 6.0.121+c2c478cf
+    version = pyslang.VersionInfo
+    if version.getMajor() >= 7 and version.getMinor() >= 0:
+        return None
 
-    # grab version # by splitting on whitespace
-    return stdout.strip().split()[-1].split('+')[0]
+    ver = f"{version.getMajor()}.{version.getMinor()}.{version.getPatch()}"
 
+    return f"incorrect pyslang version: {ver}"
 
-def post_process(chip):
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
 
-    log = f'{step}.log'
-    with sc_open(log) as f:
-        for line in f:
-            match = re.search(r'(\d+) errors, (\d+) warnings', line)
-            if match:
-                record_metric(chip, step, index, 'errors', match.group(1), log)
-                record_metric(chip, step, index, 'warnings', match.group(2), log)
+################################
+# Setup Tool (pre executable)
+################################
+def setup(chip):
+    add_require_input(chip, 'input', 'rtl', 'verilog')
+    add_require_input(chip, 'input', 'rtl', 'systemverilog')
+    add_require_input(chip, 'input', 'cmdfile', 'f')
+    add_frontend_requires(chip, ['ydir', 'idir', 'vlib', 'libext', 'define', 'param'])
 
 
 def common_runtime_options(chip):
-    options = []
-
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
 
-    options.extend(['-j', str(chip.get('tool', tool, 'task', task, 'threads',
-                              step=step, index=index))])
+    options = chip.get('tool', tool, 'task', task, 'option', step=step, index=index)
+
+    options.append('--single-unit')
+
+    options.extend(['--threads', str(chip.get('tool', tool, 'task', task, 'threads',
+                                              step=step, index=index))])
 
     opts = get_frontend_options(chip,
                                 ['ydir',
@@ -113,7 +114,7 @@ def common_runtime_options(chip):
     #######################
     # Top Module
     #######################
-    options.append('--top ' + chip.top())
+    options.append('--top ' + chip.top(step, index))
 
     ###############################
     # Parameters (top module only)
@@ -124,3 +125,92 @@ def common_runtime_options(chip):
         options.append(f'-G {param}={value}')
 
     return options
+
+
+def _get_driver(chip, options_func, ignored_diagnotics=None):
+    driver = pyslang.Driver()
+    driver.addStandardArgs()
+
+    options = options_func(chip)
+
+    parseOpts = pyslang.CommandLineOptions()
+    parseOpts.ignoreProgramName = True
+    opts = " ".join(options)
+    code = 0
+    if not driver.parseCommandLine(opts, parseOpts):
+        code = 1
+
+    if code == 0 and not driver.processOptions():
+        code = 2
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    for warning in chip.get('tool', tool, 'task', task, 'warningoff', step=step, index=index):
+        if hasattr(pyslang.Diags, warning):
+            driver.diagEngine.setSeverity(
+                getattr(pyslang.Diags, warning),
+                pyslang.DiagnosticSeverity.Ignored)
+        elif not chip.get('option', 'quiet', step=step, index=index):
+            chip.logger.warning(f'{warning} is not a valid slang category')
+
+    if not ignored_diagnotics:
+        ignored_diagnotics = []
+    for ignore in ignored_diagnotics:
+        driver.diagEngine.setSeverity(
+            ignore,
+            pyslang.DiagnosticSeverity.Ignored)
+
+    return driver, code
+
+
+def _compile(chip, driver):
+    ok = driver.parseAllSources()
+    compilation = driver.createCompilation()
+    return compilation, ok
+
+
+def _diagnostics(chip, driver, compilation):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    report = {
+        "error": [],
+        "warning": [],
+    }
+    diags = driver.diagEngine
+    for diag in compilation.getAllDiagnostics():
+        severity = diags.getSeverity(diag.code, diag.location)
+        report_level = None
+        if severity == pyslang.DiagnosticSeverity.Warning:
+            report_level = "warning"
+        elif severity == pyslang.DiagnosticSeverity.Error:
+            report_level = "error"
+        elif severity == pyslang.DiagnosticSeverity.Fatal:
+            report_level = "error"
+
+        if report_level:
+            for n, line in enumerate(diags.reportAll(driver.sourceManager, [diag]).splitlines()):
+                if line.strip():
+                    if n == 0:
+                        line_parts = line.split(":")
+                        if os.path.exists(line_parts[0]):
+                            line_parts[0] = os.path.abspath(line_parts[0])
+                        line = ":".join(line_parts)
+
+                    report[report_level].append(line)
+
+    if not chip.get('option', 'quiet', step=step, index=index):
+        if report["warning"]:
+            for line in report["warning"]:
+                chip.logger.warning(line)
+        if report["error"]:
+            for line in report["error"]:
+                chip.logger.error(line)
+
+    diags.clearCounts()
+    for diag in compilation.getAllDiagnostics():
+        diags.issue(diag)
+
+    record_metric(chip, step, index, 'errors', diags.numErrors, [])
+    record_metric(chip, step, index, 'warnings', diags.numWarnings, [])

siliconcompiler/tools/slang/elaborate.py

@@ -1,13 +1,21 @@
 from siliconcompiler import utils
 from siliconcompiler.tools import slang
-from siliconcompiler.tools._common import \
-    add_require_input, add_frontend_requires, get_tool_task, has_input_files
+import os
+from siliconcompiler.tools._common import get_tool_task, has_input_files
+from siliconcompiler.tools.slang import pyslang
 
 
 def setup(chip):
     '''
     Elaborate verilog design files and generate a unified file.
     '''
+    if slang.test_version():
+        return slang.test_version()
+
+    if not has_input_files(chip, 'input', 'rtl', 'verilog') and \
+       not has_input_files(chip, 'input', 'rtl', 'systemverilog'):
+        return "no files in [input,rtl,systemverilog] or [input,rtl,verilog]"
+
     slang.setup(chip)
 
     step = chip.get('arg', 'step')
@@ -17,30 +25,127 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              clobber=False, step=step, index=index)
 
-    add_require_input(chip, 'input', 'rtl', 'verilog')
-    add_require_input(chip, 'input', 'rtl', 'systemverilog')
-    add_frontend_requires(chip, ['ydir', 'idir', 'vlib', 'libext', 'define', 'param'])
-
-    chip.set('tool', tool, 'task', task, 'stdout', 'destination', 'output', step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'stdout', 'suffix', 'v', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'stdout', 'destination', 'log', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'stderr', 'destination', 'log', step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'output', __outputfile(chip), step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'include_source_paths', True,
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'include_source_paths',
+             "true/false, if true add the source file path information", field="help")
+
+
+def __outputfile(chip):
+    is_systemverilog = has_input_files(chip, 'input', 'rtl', 'systemverilog')
+    if is_systemverilog:
+        return f'{chip.top()}.sv'
+    return f'{chip.top()}.v'
+
+
+def __get_files(manager, tree):
+    files = set()
+
+    from queue import Queue
+    nodes = Queue(maxsize=0)
+    nodes.put(tree.root)
+
+    def procRange(range):
+        files.add(manager.getFileName(range.start))
+        files.add(manager.getFileName(range.end))
+
+    while not nodes.empty():
+        node = nodes.get()
+        procRange(node.sourceRange)
+        for token in node:
+            if isinstance(token, pyslang.Token):
+                procRange(token.range)
+            else:
+                nodes.put(token)
+
+    return sorted([os.path.abspath(f) for f in files if os.path.isfile(f)])
+
+
+def run(chip):
+    # Override default errors
+    ignored = [
+        pyslang.Diags.MissingTimeScale,
+        pyslang.Diags.UsedBeforeDeclared,
+        pyslang.Diags.UnusedParameter,
+        pyslang.Diags.UnusedDefinition,
+        pyslang.Diags.UnusedVariable,
+        pyslang.Diags.UnusedPort,
+        pyslang.Diags.UnusedButSetNet,
+        pyslang.Diags.UnusedImplicitNet,
+        pyslang.Diags.UnusedButSetVariable,
+        pyslang.Diags.UnusedButSetPort,
+        pyslang.Diags.UnusedTypedef,
+        pyslang.Diags.UnusedGenvar,
+        pyslang.Diags.UnusedAssertionDecl
+    ]
+
+    driver, exitcode = slang._get_driver(
+        chip,
+        runtime_options,
+        ignored_diagnotics=ignored)
+    if exitcode:
+        return exitcode
+
+    compilation, ok = slang._compile(chip, driver)
+
+    slang._diagnostics(chip, driver, compilation)
+
+    manager = compilation.sourceManager
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    add_source = chip.get('tool', tool, 'task', task, 'var', 'include_source_paths',
+                          step=step, index=index)[0] == 'true'
+
+    def printFiles(out, files):
+        for src_file in files:
+            out.write(f'//   File: {src_file}\n')
+
+    with open(f'outputs/{__outputfile(chip)}', 'w') as out:
+        for tree in compilation.getSyntaxTrees():
+            files = []
+            if add_source:
+                files = __get_files(manager, tree)
+
+            writer = pyslang.SyntaxPrinter(manager)
+
+            writer.setIncludeMissing(False)
+            writer.setIncludeSkipped(False)
+            writer.setIncludeDirectives(False)
+
+            writer.setIncludePreprocessed(True)
+            writer.setIncludeTrivia(True)
+            writer.setIncludeComments(True)
+            writer.setSquashNewlines(True)
+
+            out.write("////////////////////////////////////////////////////////////////\n")
+            out.write("// Start:\n")
+            printFiles(out, files)
+
+            out.write(writer.print(tree).str() + '\n')
+
+            out.write("// End:\n")
+            printFiles(out, files)
+            out.write("////////////////////////////////////////////////////////////////\n")
+
+    if ok:
+        return 0
+    else:
+        return 1
+
 
 def runtime_options(chip):
     options = slang.common_runtime_options(chip)
     options.extend([
-        "--preprocess",
-        "--comments",
+        "--allow-use-before-declare",
         "--ignore-unknown-modules",
-        "--allow-use-before-declare"
+        "-Weverything"
     ])
 
     return options
-
-
-def __outputfile(chip):
-    is_systemverilog = has_input_files(chip, 'input', 'rtl', 'systemverilog')
-    if is_systemverilog:
-        return f'{chip.top()}.sv'
-    return f'{chip.top()}.v'

siliconcompiler/tools/slang/lint.py

@@ -1,13 +1,15 @@
 from siliconcompiler import utils
 from siliconcompiler.tools import slang
-from siliconcompiler.tools._common import \
-    add_require_input, add_frontend_requires, get_tool_task
+from siliconcompiler.tools._common import get_tool_task
 
 
 def setup(chip):
     '''
     Lint system verilog
     '''
+    if slang.test_version():
+        return slang.test_version()
+
     slang.setup(chip)
 
     step = chip.get('arg', 'step')
@@ -17,19 +19,27 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              clobber=False, step=step, index=index)
 
-    add_require_input(chip, 'input', 'rtl', 'verilog')
-    add_require_input(chip, 'input', 'rtl', 'systemverilog')
-    add_frontend_requires(chip, ['ydir', 'idir', 'vlib', 'libext', 'define', 'param'])
+
+def run(chip):
+    driver, exitcode = slang._get_driver(chip, runtime_options)
+    if exitcode:
+        return exitcode
+
+    compilation, ok = slang._compile(chip, driver)
+    slang._diagnostics(chip, driver, compilation)
+
+    if ok:
+        return 0
+    else:
+        return 1
 
 
 def runtime_options(chip):
     options = slang.common_runtime_options(chip)
     options.extend([
-        "--lint-only"
+        "--lint-only",
+        "-Weverything",
+        "-Werror"
     ])
 
     return options
-
-
-def post_process(chip):
-    slang.post_process(chip)

siliconcompiler/tools/surelog/__init__.py

@@ -10,7 +10,12 @@ Sources: https://github.com/chipsalliance/Surelog
 Installation: https://github.com/chipsalliance/Surelog
 '''
 
-import surelog
+import sys
+try:
+    import surelog
+except ModuleNotFoundError:
+    surelog = None
+
 from siliconcompiler.tools._common import get_tool_task
 
 
@@ -31,9 +36,17 @@ def setup(chip):
 
     is_docker = chip.get('option', 'scheduler', 'name', step=step, index=index) == 'docker'
     if not is_docker:
-        exe = surelog.get_bin()
+        if surelog:
+            exe = surelog.get_bin()
+        else:
+            exe = 'surelog'
+            if sys.platform.startswith("win32"):
+                exe = f"{exe}.exe"
     else:
-        exe = surelog.get_bin('linux')
+        if surelog:
+            exe = surelog.get_bin('linux')
+        else:
+            exe = 'surelog'
 
     # Standard Setup
     chip.set('tool', tool, 'exe', exe)
@@ -43,7 +56,7 @@ def setup(chip):
     # We package SC wheels with a precompiled copy of Surelog installed to
     # tools/surelog/bin. If the user doesn't have Surelog installed on their
     # system path, set the path to the bundled copy in the schema.
-    if not surelog.has_system_surelog() and not is_docker:
+    if surelog and not surelog.has_system_surelog() and not is_docker:
         chip.set('tool', tool, 'path', surelog.get_path(), clobber=False)
 
     # Log file parsing

siliconcompiler/tools/vpr/vpr.py

@@ -16,6 +16,7 @@ Sources: https://github.com/verilog-to-routing/vtr-verilog-to-routing
 Installation: https://github.com/verilog-to-routing/vtr-verilog-to-routing
 '''
 
+import glob
 import os
 import shutil
 import json
@@ -42,7 +43,7 @@ def setup_tool(chip, clobber=True):
 
     chip.set('tool', 'vpr', 'exe', 'vpr', clobber=clobber)
     chip.set('tool', 'vpr', 'vswitch', '--version')
-    chip.set('tool', 'vpr', 'version', '>=8.1.0', clobber=clobber)
+    chip.set('tool', 'vpr', 'version', '>=9.0.0', clobber=clobber)
 
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
@@ -80,6 +81,16 @@ def add_tool_requirements(chip):
     chip.add('tool', tool, 'task', task, 'require', f'fpga,{part_name},var,vpr_device_code',
              step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'timing_paths',
+             'number of timing paths to report', field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'timing_paths', '20',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'timing_report_type',
+             'type of timing report', field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'timing_report_type', 'aggregated',
+             step=step, index=index, clobber=False)
+
 
 def runtime_options(chip):
 
@@ -163,13 +174,22 @@ def runtime_options(chip):
                 'vpr_clock model must be set to ideal, route, or dedicated_clock_network',
                 chip=chip)
 
+    sdc_file = None
     if chip.valid('input', 'constraint', 'sdc'):
         sdc_file = find_single_file(chip, 'input', 'constraint', 'sdc',
                                     step=step, index=index,
                                     file_not_found_msg="SDC file not found")
-        if (sdc_file is not None):
-            sdc_arg = f"--sdc_file {sdc_file}"
-            options.append(sdc_arg)
+
+    if sdc_file:
+        sdc_arg = f"--sdc_file {sdc_file}"
+        options.append(sdc_arg)
+
+        report_type = chip.get('tool', tool, 'task', task, 'var', 'timing_report_type',
+                               step=step, index=index)[0]
+        options.append(f'--timing_report_detail {report_type}')
+        report_paths = chip.get('tool', tool, 'task', task, 'var', 'timing_paths',
+                                step=step, index=index)[0]
+        options.append(f'--timing_report_npaths {report_paths}')
     else:
         options.append("--timing_analysis off")
 
@@ -295,8 +315,8 @@ def vpr_post_process(chip):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
 
-    if os.path.exists('packing_pin_util.rpt'):
-        shutil.move('packing_pin_util.rpt', 'reports')
+    for report in glob.glob("*.rpt"):
+        shutil.move(report, 'reports')
 
     part_name = chip.get('fpga', 'partname')
     dff_cells = []
@@ -379,6 +399,66 @@ def vpr_post_process(chip):
 
             record_metric(chip, step, index, "pins", io, __block_file)
 
+    for setup_report in ("reports/report_timing.setup.rpt",
+                         "reports/pre_pack.report_timing.setup.rpt"):
+        if not os.path.exists(setup_report):
+            continue
+
+        slack = _parse_timing_report(setup_report)
+        if slack is not None:
+            wns = min([slack, 0])
+            record_metric(chip, step, index, "setupslack", slack, setup_report, source_unit="ns")
+            record_metric(chip, step, index, "setupwns", wns, setup_report, source_unit="ns")
+            break
+
+    for hold_report in ("reports/report_timing.hold.rpt", ):
+        if not os.path.exists(hold_report):
+            continue
+
+        slack = _parse_timing_report(hold_report)
+        if slack is not None:
+            wns = min([slack, 0])
+            record_metric(chip, step, index, "holdslack", slack, hold_report, source_unit="ns")
+            record_metric(chip, step, index, "holdwns", wns, hold_report, source_unit="ns")
+            break
+
+    unconstrained = None
+    unconstrained_reports = []
+    for unconstrained_report in ("reports/report_unconstrained_timing.hold.rpt",
+                                 "reports/report_unconstrained_timing.setup.rpt"):
+        if not os.path.exists(unconstrained_report):
+            continue
+
+        paths = _parse_unconstrained_report(unconstrained_report)
+        if unconstrained is None:
+            unconstrained = paths
+
+        unconstrained = max([paths, unconstrained])
+        unconstrained_reports.append(unconstrained_report)
+
+    if unconstrained is not None:
+        record_metric(chip, step, index, "unconstrained", unconstrained, unconstrained_reports)
+
+
+def _parse_timing_report(report):
+    slack = re.compile(r"slack \(.*\)\s+(-?\d+\.?\d*)")
+    with sc_open(report) as f:
+        for line in f:
+            match_slack = slack.findall(line)
+            if match_slack:
+                return float(match_slack[0])
+    return None
+
+
+def _parse_unconstrained_report(report):
+    path = re.compile(r"\d+ .*")
+    count = 0
+    with sc_open(report) as f:
+        for line in f:
+            if path.match(line):
+                count += 1
+    return count
+
 
 ##################################################
 if __name__ == "__main__":

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "6e6fccbbe0ffbe683a51de3ecac2a24958a53fa1",
+    "git-commit": "0fbd4d94c81ef070249ad9d9037a740d0c6e58fa",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -36,7 +36,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.29.11",
+    "version": "0.29.12",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -66,7 +66,7 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "de31f094aa4f894a5e6e0dc32c66365f4b341190",
+    "git-commit": "v9.0.0",
     "auto-update": false
   },
   "icepack": {
@@ -139,7 +139,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "0adba99ea43331235506b9b154c78a401f4fe9b6",
+    "git-commit": "8f2239b2b12dac43f8f47f56deef1095d5262fa2",
     "docker-depends": "yosys",
     "auto-update": true
   },

siliconcompiler/units.py

@@ -41,7 +41,7 @@ SI_TYPES = (
     'V',
     'W',
     'ohm',
-    'C',
+    'C'
 )
 
 
@@ -107,8 +107,6 @@ def get_si_prefix(unit):
         if matches:
             return matches[0][0]
 
-    return ''
-
 
 def get_si_power(unit):
     '''
@@ -164,6 +162,11 @@ def format_si(value, unit, margin=3, digits=3):
         digits (int): number of digits to print after .
     '''
     scaled_value, prefix = scale_si(value, unit, margin=margin, digits=digits)
+
+    if digits < 0:
+        # Default to 1
+        digits = 1
+
     # need to do this in case float shortens scaled_value
     return f'{scaled_value:.{digits}f}{prefix}'
 
@@ -179,14 +182,14 @@ def scale_si(value, unit, margin=3, digits=3):
             when picking the right magnitude
         digits (int): number of digits to print after .
     '''
+    if digits < 0:
+        # Default to 1
+        digits = 1
+
     if unit and is_base_si_unit(unit):
         value = float(value)
         log_value = math.log10(value) - margin
 
-        if digits < 0:
-            # Default to 0
-            digits = 0
-
         for prefix, scale in SI_UNITS:
             if log_value <= scale:
                 value /= 10**scale