siliconcompiler 0.30.0__py3-none-any.whl → 0.31.1__py3-none-any.whl

siliconcompiler/tools/openroad/detailed_route.py

@@ -52,6 +52,14 @@ def setup(chip):
         'clock_trees'
     ])
 
+    chip.set('tool', tool, 'task', task, 'var', 'drt_end_iteration',
+             'end iteration for detail routing',
+             field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'drt_end_iteration', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'drt_end_iteration']),
+                 step=step, index=index)
+
 
 def pre_process(chip):
     define_ord_files(chip)

siliconcompiler/tools/openroad/fillercell_insertion.py

@@ -45,7 +45,8 @@ def setup(chip):
         # Images
         'placement_density',
         'routing_congestion',
-        'power_density'
+        'power_density',
+        'module_view'
     ])
 
 

siliconcompiler/tools/openroad/global_placement.py

@@ -48,7 +48,8 @@ def setup(chip):
         # Images
         'placement_density',
         'routing_congestion',
-        'power_density'
+        'power_density',
+        'module_view'
     ])
 
     set_tool_task_var(chip, param_key='enable_multibit_clustering',

siliconcompiler/tools/openroad/pin_placement.py

@@ -42,7 +42,8 @@ def setup(chip):
         # Images
         'placement_density',
         'routing_congestion',
-        'power_density'
+        'power_density',
+        'module_view'
     ])
 
 

siliconcompiler/tools/openroad/rdlroute.py

@@ -75,6 +75,10 @@ def setup(chip):
                              'if enabled by the PDK, to the design',
                       skip='lib')
 
+    chip.set('tool', tool, 'task', task, 'var', 'debug_level',
+             'list of "tool key level" to enable debugging of OpenROAD',
+             field='help')
+
     if f'{design}.v' in input_provides(chip, step, index):
         chip.add('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
     elif f'{design}.vg' in input_provides(chip, step, index):

siliconcompiler/tools/openroad/repair_design.py

@@ -46,7 +46,8 @@ def setup(chip):
         'placement_density',
         'routing_congestion',
         'power_density',
-        'optimization_placement'
+        'optimization_placement',
+        'module_view'
     ])
 
 

siliconcompiler/tools/openroad/repair_timing.py

@@ -50,7 +50,8 @@ def setup(chip):
         'power_density',
         'optimization_placement',
         'clock_placement',
-        'clock_trees'
+        'clock_trees',
+        'module_view'
     ])
 
 

siliconcompiler/tools/openroad/scripts/apr/preamble.tcl

@@ -65,6 +65,12 @@ sc_set_dont_use
 
 sc_setup_global_routing
 
+# Store incoming markers to avoid rewriting them
+set sc_starting_markers []
+foreach markerdb [[ord::get_db_block] getMarkerCategories] {
+    lappend sc_starting_markers [$markerdb getName]
+}
+
 ###############################
 # Source Step Script
 ###############################

siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl

@@ -36,6 +36,7 @@ if { [llength [all_clocks]] > 0 } {
 
     set cts_distance_between_buffers \
         [lindex [sc_cfg_tool_task_get var cts_distance_between_buffers] 0]
+    sc_report_args -command clock_tree_synthesis -args $sc_cts_arguments
     clock_tree_synthesis \
         -sink_clustering_enable \
         -sink_clustering_size [lindex [sc_cfg_tool_task_get var cts_cluster_size] 0] \

siliconcompiler/tools/openroad/scripts/apr/sc_detailed_route.tcl

@@ -40,12 +40,20 @@ set drt_repair_pdn_vias \
 if { $drt_repair_pdn_vias != "" } {
     lappend drt_arguments "-repair_pdn_vias" $drt_repair_pdn_vias
 }
+set drt_end_iteration [lindex [sc_cfg_tool_task_get {var} drt_end_iteration] 0]
+if { $drt_end_iteration != "" } {
+    lappend drt_arguments "-droute_end_iter" $drt_end_iteration
+}
+lappend drt_arguments \
+    -drc_report_iter_step \
+    [lindex [sc_cfg_tool_task_get {var} drt_report_interval] 0]
 
 set sc_minmetal [sc_cfg_get pdk $sc_pdk minlayer $sc_stackup]
 set sc_minmetal [sc_get_layer_name $sc_minmetal]
 set sc_maxmetal [sc_cfg_get pdk $sc_pdk maxlayer $sc_stackup]
 set sc_maxmetal [sc_get_layer_name $sc_maxmetal]
 
+sc_report_args -command detailed_route -args $drt_arguments
 detailed_route \
     -save_guide_updates \
     -output_drc "reports/${sc_design}_drc.rpt" \

siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl

@@ -41,6 +41,7 @@ if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
             [lindex [sc_cfg_tool_task_get var scan_enable_port_pattern] 0]
     }
 
+    sc_report_args -command set_dft_config -args $dft_args
     set_dft_config -clock_mixing clock_mix {*}$dft_args
     tee -file reports/scan_chain_config.rpt {report_dft_config}
     scan_replace

siliconcompiler/tools/openroad/scripts/apr/sc_global_route.tcl

@@ -29,6 +29,7 @@ if { [lindex [sc_cfg_tool_task_get {var} grt_use_pin_access] 0] == "true" } {
             [lindex [sc_cfg_tool_task_get {var} drt_process_node] 0]
     }
 
+    sc_report_args -command pin_access -args $pin_access_args
     pin_access \
         -bottom_routing_layer $sc_minmetal \
         -top_routing_layer $sc_maxmetal \
@@ -47,6 +48,7 @@ if { [lindex [sc_cfg_tool_task_get {var} grt_allow_overflow] 0] == "true" } {
     lappend sc_grt_arguments "-allow_overflow"
 }
 
+sc_report_args -command global_route -args $sc_grt_arguments
 if {
     [catch {
         global_route -guide_file "reports/route.guide" \

siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl

@@ -121,11 +121,11 @@ if { [sc_cfg_exists constraint pin] } {
         global sc_vpinmetal
 
         set layer [sc_cfg_get constraint pin $pin layer]
-        if { [llength $layer] != 0 } {
-            return [sc_get_layer_name [lindex $layer 0]]
+        if { $layer != {} } {
+            return [sc_get_layer_name $layer]
         }
         set side [sc_cfg_get constraint pin $pin side]
-        if { [llength $side] != 0 } {
+        if { $side != {} } {
             switch -regexp $side {
                 "1|3" {
                     return [lindex $sc_hpinmetal 0]

siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl

@@ -85,6 +85,10 @@ if { [sc_design_has_unplaced_macros] } {
     if { $rtlmp_guidance_weight != "" } {
         lappend rtlmp_args -guidance_weight $rtlmp_guidance_weight
     }
+    set rtlmp_boundary_weight [lindex [sc_cfg_tool_task_get var rtlmp_boundary_weight] 0]
+    if { $rtlmp_boundary_weight != "" } {
+        lappend rtlmp_args -boundary_weight $rtlmp_boundary_weight
+    }
     set rtlmp_fence_weight [lindex [sc_cfg_tool_task_get var rtlmp_fence_weight] 0]
     if { $rtlmp_fence_weight != "" } {
         lappend rtlmp_args -fence_weight $rtlmp_fence_weight
@@ -98,6 +102,7 @@ if { [sc_design_has_unplaced_macros] } {
         lappend rtlmp_args -blockage_weight $rtlmp_blockage_weight
     }
 
+    sc_report_args -command rtl_macro_placer -args $rtlmp_args
     rtl_macro_placer \
         -report_directory reports/rtlmp \
         -halo_width $halo_x \

siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl

@@ -99,6 +99,7 @@ foreach net [sc_psm_check_nets] {
         lappend check_args -dont_require_terminals
     }
 
+    sc_report_args -command check_power_grid -args $check_args
     check_power_grid \
         -floorplanning \
         -error_file "reports/power_grid_${net}.rpt" \

siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl

@@ -41,6 +41,7 @@ if { $rsz_slew_margin != "false" } {
     lappend repair_design_args "-slew_margin" $rsz_slew_margin
 }
 
+sc_report_args -command repair_design -args $repair_design_args
 repair_design \
     -verbose \
     {*}$repair_design_args

siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl

@@ -40,6 +40,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
 
     estimate_parasitics -placement
 
+    sc_report_args -command repair_timing -args $repair_timing_args
     repair_timing \
         -setup \
         -verbose \
@@ -64,6 +65,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
     # Enable hold cells
     sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.hold
 
+    sc_report_args -command repair_timing -args $repair_timing_args
     repair_timing \
         -hold \
         -verbose \
@@ -88,6 +90,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_recover_power] 0] != "true" } {
     # Enable cells
     sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.power
 
+    sc_report_args -command repair_timing -args $repair_timing_args
     repair_timing \
         -recover_power $rsz_recover_power \
         -verbose \

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -86,6 +86,7 @@ proc sc_global_placement { args } {
 
     set density [sc_global_placement_density]
 
+    sc_report_args -command global_placement -args $gpl_args
     global_placement {*}$gpl_args \
         -density $density \
         -pad_left $gpl_padding \
@@ -110,6 +111,7 @@ proc sc_detailed_placement { } {
         lappend dpl_args "-disallow_one_site_gaps"
     }
 
+    sc_report_args -command detailed_placement -args $dpl_args
     detailed_placement \
         -max_displacement $dpl_max_displacement \
         {*}$dpl_args
@@ -126,15 +128,6 @@ proc sc_pin_placement { args } {
         flags {-random}
     sta::check_argc_eq0 "sc_pin_placement" $args
 
-    global sc_pdk
-    global sc_stackup
-    global sc_tool
-
-    set sc_hpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_horizontal $sc_stackup]
-    set sc_hpinmetal [sc_get_layer_name $sc_hpinmetal]
-    set sc_vpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_vertical $sc_stackup]
-    set sc_vpinmetal [sc_get_layer_name $sc_vpinmetal]
-
     if { [sc_cfg_tool_task_exists var pin_thickness_h] } {
         set h_mult [lindex [sc_cfg_tool_task_get var pin_thickness_h] 0]
         set_pin_thick_multiplier -hor_multiplier $h_mult
@@ -155,9 +148,19 @@ proc sc_pin_placement { args } {
         lappend ppl_args "-random"
     }
 
-    place_pins -hor_layers $sc_hpinmetal \
-        -ver_layers $sc_vpinmetal \
-        {*}[sc_cfg_tool_task_get {var} ppl_arguments] \
+    lappend ppl_args {*}[sc_cfg_tool_task_get {var} ppl_arguments]
+
+    global sc_pdk
+    global sc_stackup
+    global sc_tool
+
+    set sc_hpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_horizontal $sc_stackup]
+    set sc_vpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_vertical $sc_stackup]
+
+    sc_report_args -command place_pins -args $ppl_args
+    place_pins \
+        -hor_layers [sc_get_layer_name $sc_hpinmetal] \
+        -ver_layers [sc_get_layer_name $sc_vpinmetal] \
         {*}$ppl_args
 }
 
@@ -783,3 +786,17 @@ proc sc_setup_detailed_route { } {
         detailed_route_set_unidirectional_layer $layer
     }
 }
+
+proc sc_report_args { args } {
+    sta::parse_key_args "sc_report_args" args \
+        keys {-command -args} \
+        flags {}
+
+    sta::check_argc_eq0 "sc_report_args" $args
+
+    if { [llength $keys(-args)] == 0 } {
+        return
+    }
+
+    puts "$keys(-command) siliconcompiler arguments: $keys(-args)"
+}

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -100,6 +100,17 @@ if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
         puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
         set fmax_metric [expr { max($fmax_metric, $fmax) }]
     }
+    if { $fmax_metric == 0 } {
+        # attempt to compute based on combinatorial path
+        set max_path [find_timing_paths -unconstrained -path_delay max]
+        set max_path_delay [$max_path data_arrival_time]
+        set min_path [find_timing_paths -unconstrained -path_delay min]
+        set min_path_delay [$min_path data_arrival_time]
+        set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
+        if { $path_delay > 0 } {
+            set fmax_metric [expr { 1.0 / $path_delay }]
+        }
+    }
     if { $fmax_metric > 0 } {
         utl::metric_float "timing__fmax" $fmax_metric
     }
@@ -169,6 +180,10 @@ foreach markerdb [[ord::get_db_block] getMarkerCategories] {
         continue
     }
 
+    if { [lsearch -exact $sc_starting_markers [$markerdb getName]] != -1 } {
+        continue
+    }
+
     $markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
     $markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
 }

siliconcompiler/tools/openroad/scripts/common/write_images.tcl

@@ -210,6 +210,24 @@ proc sc_image_placement_density { } {
         "placement density"
 }
 
+proc sc_image_module_view { } {
+    if { ![sc_has_placed_instances] } {
+        return
+    }
+
+    if { [llength [[ord::get_db_block] getModInsts]] < 1 } {
+        return
+    }
+
+    global sc_design
+    sc_image_setup_default
+
+    gui::set_display_controls "Misc/Module view" visible true
+    gui::set_display_controls "Nets/*" visible false
+
+    sc_save_image "module view" reports/images/${sc_design}.modules.png
+}
+
 proc sc_image_clocks { } {
     if { ![sc_has_placed_instances] } {
         return
@@ -333,12 +351,18 @@ proc sc_image_markers { } {
     global sc_design
     sc_image_setup_default
 
+    global sc_starting_markers
+
     file mkdir reports/images/markers
     foreach markerdb [[ord::get_db_block] getMarkerCategories] {
         if { [$markerdb getMarkerCount] == 0 } {
             continue
         }
 
+        if { [lsearch -exact $sc_starting_markers [$markerdb getName]] != -1 } {
+            continue
+        }
+
         gui::select_marker_category $markerdb
 
         sc_save_image \
@@ -359,6 +383,10 @@ sc_image_everything
 sc_image_placement
 sc_image_routing
 
+if { [sc_cfg_tool_task_check_in_list module_view var reports] } {
+    sc_image_module_view
+}
+
 # Markers
 sc_image_markers
 

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -35,21 +35,11 @@ set sc_threads [sc_cfg_tool_task_get threads]
 # MACROS
 set sc_macrolibs [sc_get_asic_libraries macro]
 
-###############################
-# Suppress messages if requested
+##############################
+# Setup debugging
 ###############################
 
-foreach msg [sc_cfg_tool_task_get warningoff] {
-    set or_msg [split $msg "-"]
-    if { [llength $or_msg] != 2 } {
-        utl::warn FLW 1 "$msg is not a valid message id"
-    } else {
-        set or_tool [lindex $or_msg 0]
-        set or_msg_id [expr { int([lindex $or_msg 1]) }]
-        utl::info FLW 1 "Suppressing $msg messages"
-        suppress_message $or_tool $or_msg_id
-    }
-}
+source -echo "$sc_refdir/common/debugging.tcl"
 
 ###############################
 # Source helper functions

siliconcompiler/tools/vpr/vpr.py

@@ -16,6 +16,7 @@ Sources: https://github.com/verilog-to-routing/vtr-verilog-to-routing
 Installation: https://github.com/verilog-to-routing/vtr-verilog-to-routing
 '''
 
+import glob
 import os
 import shutil
 import json
@@ -42,7 +43,7 @@ def setup_tool(chip, clobber=True):
 
     chip.set('tool', 'vpr', 'exe', 'vpr', clobber=clobber)
     chip.set('tool', 'vpr', 'vswitch', '--version')
-    chip.set('tool', 'vpr', 'version', '>=8.1.0', clobber=clobber)
+    chip.set('tool', 'vpr', 'version', '>=9.0.0', clobber=clobber)
 
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
@@ -80,6 +81,16 @@ def add_tool_requirements(chip):
     chip.add('tool', tool, 'task', task, 'require', f'fpga,{part_name},var,vpr_device_code',
              step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'timing_paths',
+             'number of timing paths to report', field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'timing_paths', '20',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'timing_report_type',
+             'type of timing report', field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'timing_report_type', 'aggregated',
+             step=step, index=index, clobber=False)
+
 
 def runtime_options(chip):
 
@@ -163,13 +174,22 @@ def runtime_options(chip):
                 'vpr_clock model must be set to ideal, route, or dedicated_clock_network',
                 chip=chip)
 
+    sdc_file = None
     if chip.valid('input', 'constraint', 'sdc'):
         sdc_file = find_single_file(chip, 'input', 'constraint', 'sdc',
                                     step=step, index=index,
                                     file_not_found_msg="SDC file not found")
-        if (sdc_file is not None):
-            sdc_arg = f"--sdc_file {sdc_file}"
-            options.append(sdc_arg)
+
+    if sdc_file:
+        sdc_arg = f"--sdc_file {sdc_file}"
+        options.append(sdc_arg)
+
+        report_type = chip.get('tool', tool, 'task', task, 'var', 'timing_report_type',
+                               step=step, index=index)[0]
+        options.append(f'--timing_report_detail {report_type}')
+        report_paths = chip.get('tool', tool, 'task', task, 'var', 'timing_paths',
+                                step=step, index=index)[0]
+        options.append(f'--timing_report_npaths {report_paths}')
     else:
         options.append("--timing_analysis off")
 
@@ -295,8 +315,8 @@ def vpr_post_process(chip):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
 
-    if os.path.exists('packing_pin_util.rpt'):
-        shutil.move('packing_pin_util.rpt', 'reports')
+    for report in glob.glob("*.rpt"):
+        shutil.move(report, 'reports')
 
     part_name = chip.get('fpga', 'partname')
     dff_cells = []
@@ -379,6 +399,66 @@ def vpr_post_process(chip):
 
             record_metric(chip, step, index, "pins", io, __block_file)
 
+    for setup_report in ("reports/report_timing.setup.rpt",
+                         "reports/pre_pack.report_timing.setup.rpt"):
+        if not os.path.exists(setup_report):
+            continue
+
+        slack = _parse_timing_report(setup_report)
+        if slack is not None:
+            wns = min([slack, 0])
+            record_metric(chip, step, index, "setupslack", slack, setup_report, source_unit="ns")
+            record_metric(chip, step, index, "setupwns", wns, setup_report, source_unit="ns")
+            break
+
+    for hold_report in ("reports/report_timing.hold.rpt", ):
+        if not os.path.exists(hold_report):
+            continue
+
+        slack = _parse_timing_report(hold_report)
+        if slack is not None:
+            wns = min([slack, 0])
+            record_metric(chip, step, index, "holdslack", slack, hold_report, source_unit="ns")
+            record_metric(chip, step, index, "holdwns", wns, hold_report, source_unit="ns")
+            break
+
+    unconstrained = None
+    unconstrained_reports = []
+    for unconstrained_report in ("reports/report_unconstrained_timing.hold.rpt",
+                                 "reports/report_unconstrained_timing.setup.rpt"):
+        if not os.path.exists(unconstrained_report):
+            continue
+
+        paths = _parse_unconstrained_report(unconstrained_report)
+        if unconstrained is None:
+            unconstrained = paths
+
+        unconstrained = max([paths, unconstrained])
+        unconstrained_reports.append(unconstrained_report)
+
+    if unconstrained is not None:
+        record_metric(chip, step, index, "unconstrained", unconstrained, unconstrained_reports)
+
+
+def _parse_timing_report(report):
+    slack = re.compile(r"slack \(.*\)\s+(-?\d+\.?\d*)")
+    with sc_open(report) as f:
+        for line in f:
+            match_slack = slack.findall(line)
+            if match_slack:
+                return float(match_slack[0])
+    return None
+
+
+def _parse_unconstrained_report(report):
+    path = re.compile(r"\d+ .*")
+    count = 0
+    with sc_open(report) as f:
+        for line in f:
+            if path.match(line):
+                count += 1
+    return count
+
 
 ##################################################
 if __name__ == "__main__":

siliconcompiler/tools/yosys/__init__.py

@@ -98,6 +98,13 @@ def syn_setup(chip):
     chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
+             'true/false, if true will attempt to use the slang frontend',
+             field='help')
+
 
 ##################################################
 def syn_post_process(chip):

siliconcompiler/tools/yosys/sc_syn.tcl

@@ -39,32 +39,41 @@ source "$sc_refdir/procs.tcl"
 # TODO: the original OpenFPGA synth script used read_verilog with -nolatches. Is
 # that a flag we might want here?
 
-# If UHDM, ilang, or Verilog inputs exist, read them in (this allows mixed
-# inputs in designs). UHDM requires a version of Yosys built with this support.
-
-if { [file exists "inputs/$sc_design.uhdm"] } {
-    set input_uhdm "inputs/$sc_design.uhdm"
-    yosys read_uhdm $input_uhdm
-}
-if { [file exists "inputs/$sc_design.ilang"] } {
-    set input_ilang "inputs/$sc_design.ilang"
-    yosys read_ilang $input_ilang
-}
-
-if { [file exists "inputs/$sc_design.v"] } {
-    set input_verilog "inputs/$sc_design.v"
-    # Use -noblackbox to correctly interpret empty modules as empty,
-    # actual black boxes are read in later
-    # https://github.com/YosysHQ/yosys/issues/1468
-    yosys read_verilog -noblackbox -sv $input_verilog
+set input_verilog "inputs/$sc_design.v"
+if { [file exists $input_verilog] } {
+    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+        # This needs some reordering of loaded to ensure blackboxes are handled
+        # before this
+        set slang_params []
+        if { [sc_cfg_exists option param] } {
+            dict for {key value} [sc_cfg_get option param] {
+                if { ![string is integer $value] } {
+                    set value [concat \"$value\"]
+                }
+
+                lappend slang_params -G "${key}=${value}"
+            }
+        }
+        yosys read_slang \
+            -D SYNTHESIS \
+            --keep-hierarchy \
+            --top $sc_design \
+            {*}$slang_params \
+            $input_verilog
+    } else {
+        # Use -noblackbox to correctly interpret empty modules as empty,
+        # actual black boxes are read in later
+        # https://github.com/YosysHQ/yosys/issues/1468
+        yosys read_verilog -noblackbox -sv $input_verilog
+
+        ########################################################
+        # Override top level parameters
+        ########################################################
+
+        sc_apply_params
+    }
 }
 
-########################################################
-# Override top level parameters
-########################################################
-
-sc_apply_params
-
 ########################################################
 # Synthesis based on mode
 ########################################################