siliconcompiler 0.30.0__py3-none-any.whl → 0.31.0__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl

@@ -36,6 +36,7 @@ if { [llength [all_clocks]] > 0 } {
 
     set cts_distance_between_buffers \
         [lindex [sc_cfg_tool_task_get var cts_distance_between_buffers] 0]
+    sc_report_args -command clock_tree_synthesis -args $sc_cts_arguments
     clock_tree_synthesis \
         -sink_clustering_enable \
         -sink_clustering_size [lindex [sc_cfg_tool_task_get var cts_cluster_size] 0] \

siliconcompiler/tools/openroad/scripts/apr/sc_detailed_route.tcl

@@ -40,12 +40,20 @@ set drt_repair_pdn_vias \
 if { $drt_repair_pdn_vias != "" } {
     lappend drt_arguments "-repair_pdn_vias" $drt_repair_pdn_vias
 }
+set drt_end_iteration [lindex [sc_cfg_tool_task_get {var} drt_end_iteration] 0]
+if { $drt_end_iteration != "" } {
+    lappend drt_arguments "-droute_end_iter" $drt_end_iteration
+}
+lappend drt_arguments \
+    -drc_report_iter_step \
+    [lindex [sc_cfg_tool_task_get {var} drt_report_interval] 0]
 
 set sc_minmetal [sc_cfg_get pdk $sc_pdk minlayer $sc_stackup]
 set sc_minmetal [sc_get_layer_name $sc_minmetal]
 set sc_maxmetal [sc_cfg_get pdk $sc_pdk maxlayer $sc_stackup]
 set sc_maxmetal [sc_get_layer_name $sc_maxmetal]
 
+sc_report_args -command detailed_route -args $drt_arguments
 detailed_route \
     -save_guide_updates \
     -output_drc "reports/${sc_design}_drc.rpt" \

siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl

@@ -41,6 +41,7 @@ if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
             [lindex [sc_cfg_tool_task_get var scan_enable_port_pattern] 0]
     }
 
+    sc_report_args -command set_dft_config -args $dft_args
     set_dft_config -clock_mixing clock_mix {*}$dft_args
     tee -file reports/scan_chain_config.rpt {report_dft_config}
     scan_replace

siliconcompiler/tools/openroad/scripts/apr/sc_global_route.tcl

@@ -29,6 +29,7 @@ if { [lindex [sc_cfg_tool_task_get {var} grt_use_pin_access] 0] == "true" } {
             [lindex [sc_cfg_tool_task_get {var} drt_process_node] 0]
     }
 
+    sc_report_args -command pin_access -args $pin_access_args
     pin_access \
         -bottom_routing_layer $sc_minmetal \
         -top_routing_layer $sc_maxmetal \
@@ -47,6 +48,7 @@ if { [lindex [sc_cfg_tool_task_get {var} grt_allow_overflow] 0] == "true" } {
     lappend sc_grt_arguments "-allow_overflow"
 }
 
+sc_report_args -command global_route -args $sc_grt_arguments
 if {
     [catch {
         global_route -guide_file "reports/route.guide" \

siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl

@@ -85,6 +85,10 @@ if { [sc_design_has_unplaced_macros] } {
     if { $rtlmp_guidance_weight != "" } {
         lappend rtlmp_args -guidance_weight $rtlmp_guidance_weight
     }
+    set rtlmp_boundary_weight [lindex [sc_cfg_tool_task_get var rtlmp_boundary_weight] 0]
+    if { $rtlmp_boundary_weight != "" } {
+        lappend rtlmp_args -boundary_weight $rtlmp_boundary_weight
+    }
     set rtlmp_fence_weight [lindex [sc_cfg_tool_task_get var rtlmp_fence_weight] 0]
     if { $rtlmp_fence_weight != "" } {
         lappend rtlmp_args -fence_weight $rtlmp_fence_weight
@@ -98,6 +102,7 @@ if { [sc_design_has_unplaced_macros] } {
         lappend rtlmp_args -blockage_weight $rtlmp_blockage_weight
     }
 
+    sc_report_args -command rtl_macro_placer -args $rtlmp_args
     rtl_macro_placer \
         -report_directory reports/rtlmp \
         -halo_width $halo_x \

siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl

@@ -99,6 +99,7 @@ foreach net [sc_psm_check_nets] {
         lappend check_args -dont_require_terminals
     }
 
+    sc_report_args -command check_power_grid -args $check_args
     check_power_grid \
         -floorplanning \
         -error_file "reports/power_grid_${net}.rpt" \

siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl

@@ -41,6 +41,7 @@ if { $rsz_slew_margin != "false" } {
     lappend repair_design_args "-slew_margin" $rsz_slew_margin
 }
 
+sc_report_args -command repair_design -args $repair_design_args
 repair_design \
     -verbose \
     {*}$repair_design_args

siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl

@@ -40,6 +40,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
 
     estimate_parasitics -placement
 
+    sc_report_args -command repair_timing -args $repair_timing_args
     repair_timing \
         -setup \
         -verbose \
@@ -64,6 +65,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
     # Enable hold cells
     sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.hold
 
+    sc_report_args -command repair_timing -args $repair_timing_args
     repair_timing \
         -hold \
         -verbose \
@@ -88,6 +90,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_recover_power] 0] != "true" } {
     # Enable cells
     sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.power
 
+    sc_report_args -command repair_timing -args $repair_timing_args
     repair_timing \
         -recover_power $rsz_recover_power \
         -verbose \

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -86,6 +86,7 @@ proc sc_global_placement { args } {
 
     set density [sc_global_placement_density]
 
+    sc_report_args -command global_placement -args $gpl_args
     global_placement {*}$gpl_args \
         -density $density \
         -pad_left $gpl_padding \
@@ -110,6 +111,7 @@ proc sc_detailed_placement { } {
         lappend dpl_args "-disallow_one_site_gaps"
     }
 
+    sc_report_args -command detailed_placement -args $dpl_args
     detailed_placement \
         -max_displacement $dpl_max_displacement \
         {*}$dpl_args
@@ -126,15 +128,6 @@ proc sc_pin_placement { args } {
         flags {-random}
     sta::check_argc_eq0 "sc_pin_placement" $args
 
-    global sc_pdk
-    global sc_stackup
-    global sc_tool
-
-    set sc_hpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_horizontal $sc_stackup]
-    set sc_hpinmetal [sc_get_layer_name $sc_hpinmetal]
-    set sc_vpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_vertical $sc_stackup]
-    set sc_vpinmetal [sc_get_layer_name $sc_vpinmetal]
-
     if { [sc_cfg_tool_task_exists var pin_thickness_h] } {
         set h_mult [lindex [sc_cfg_tool_task_get var pin_thickness_h] 0]
         set_pin_thick_multiplier -hor_multiplier $h_mult
@@ -155,9 +148,19 @@ proc sc_pin_placement { args } {
         lappend ppl_args "-random"
     }
 
-    place_pins -hor_layers $sc_hpinmetal \
-        -ver_layers $sc_vpinmetal \
-        {*}[sc_cfg_tool_task_get {var} ppl_arguments] \
+    lappend ppl_args {*}[sc_cfg_tool_task_get {var} ppl_arguments]
+
+    global sc_pdk
+    global sc_stackup
+    global sc_tool
+
+    set sc_hpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_horizontal $sc_stackup]
+    set sc_vpinmetal [sc_cfg_get pdk $sc_pdk {var} $sc_tool pin_layer_vertical $sc_stackup]
+
+    sc_report_args -command place_pins -args $ppl_args
+    place_pins \
+        -hor_layers [sc_get_layer_name $sc_hpinmetal] \
+        -ver_layers [sc_get_layer_name $sc_vpinmetal] \
         {*}$ppl_args
 }
 
@@ -783,3 +786,17 @@ proc sc_setup_detailed_route { } {
         detailed_route_set_unidirectional_layer $layer
     }
 }
+
+proc sc_report_args { args } {
+    sta::parse_key_args "sc_report_args" args \
+        keys {-command -args} \
+        flags {}
+
+    sta::check_argc_eq0 "sc_report_args" $args
+
+    if { [llength $keys(-args)] == 0 } {
+        return
+    }
+
+    puts "$keys(-command) siliconcompiler arguments: $keys(-args)"
+}

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -100,6 +100,17 @@ if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
         puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
         set fmax_metric [expr { max($fmax_metric, $fmax) }]
     }
+    if { $fmax_metric == 0 } {
+        # attempt to compute based on combinatorial path
+        set max_path [find_timing_paths -unconstrained -path_delay max]
+        set max_path_delay [$max_path data_arrival_time]
+        set min_path [find_timing_paths -unconstrained -path_delay min]
+        set min_path_delay [$min_path data_arrival_time]
+        set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
+        if { $path_delay > 0 } {
+            set fmax_metric [expr { 1.0 / $path_delay }]
+        }
+    }
     if { $fmax_metric > 0 } {
         utl::metric_float "timing__fmax" $fmax_metric
     }
@@ -169,6 +180,10 @@ foreach markerdb [[ord::get_db_block] getMarkerCategories] {
         continue
     }
 
+    if { [lsearch -exact $sc_starting_markers [$markerdb getName]] != -1 } {
+        continue
+    }
+
     $markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
     $markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
 }

siliconcompiler/tools/openroad/scripts/common/write_images.tcl

@@ -210,6 +210,24 @@ proc sc_image_placement_density { } {
         "placement density"
 }
 
+proc sc_image_module_view { } {
+    if { ![sc_has_placed_instances] } {
+        return
+    }
+
+    if { [llength [[ord::get_db_block] getModInsts]] < 1 } {
+        return
+    }
+
+    global sc_design
+    sc_image_setup_default
+
+    gui::set_display_controls "Misc/Module view" visible true
+    gui::set_display_controls "Nets/*" visible false
+
+    sc_save_image "module view" reports/images/${sc_design}.modules.png
+}
+
 proc sc_image_clocks { } {
     if { ![sc_has_placed_instances] } {
         return
@@ -333,12 +351,18 @@ proc sc_image_markers { } {
     global sc_design
     sc_image_setup_default
 
+    global sc_starting_markers
+
     file mkdir reports/images/markers
     foreach markerdb [[ord::get_db_block] getMarkerCategories] {
         if { [$markerdb getMarkerCount] == 0 } {
             continue
         }
 
+        if { [lsearch -exact $sc_starting_markers [$markerdb getName]] != -1 } {
+            continue
+        }
+
         gui::select_marker_category $markerdb
 
         sc_save_image \
@@ -359,6 +383,10 @@ sc_image_everything
 sc_image_placement
 sc_image_routing
 
+if { [sc_cfg_tool_task_check_in_list module_view var reports] } {
+    sc_image_module_view
+}
+
 # Markers
 sc_image_markers
 

siliconcompiler/tools/yosys/__init__.py

@@ -98,6 +98,13 @@ def syn_setup(chip):
     chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
+             'true/false, if true will attempt to use the slang frontend',
+             field='help')
+
 
 ##################################################
 def syn_post_process(chip):

siliconcompiler/tools/yosys/sc_syn.tcl

@@ -39,32 +39,41 @@ source "$sc_refdir/procs.tcl"
 # TODO: the original OpenFPGA synth script used read_verilog with -nolatches. Is
 # that a flag we might want here?
 
-# If UHDM, ilang, or Verilog inputs exist, read them in (this allows mixed
-# inputs in designs). UHDM requires a version of Yosys built with this support.
-
-if { [file exists "inputs/$sc_design.uhdm"] } {
-    set input_uhdm "inputs/$sc_design.uhdm"
-    yosys read_uhdm $input_uhdm
-}
-if { [file exists "inputs/$sc_design.ilang"] } {
-    set input_ilang "inputs/$sc_design.ilang"
-    yosys read_ilang $input_ilang
-}
-
-if { [file exists "inputs/$sc_design.v"] } {
-    set input_verilog "inputs/$sc_design.v"
-    # Use -noblackbox to correctly interpret empty modules as empty,
-    # actual black boxes are read in later
-    # https://github.com/YosysHQ/yosys/issues/1468
-    yosys read_verilog -noblackbox -sv $input_verilog
+set input_verilog "inputs/$sc_design.v"
+if { [file exists $input_verilog] } {
+    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+        # This needs some reordering of loaded to ensure blackboxes are handled
+        # before this
+        set slang_params []
+        if { [sc_cfg_exists option param] } {
+            dict for {key value} [sc_cfg_get option param] {
+                if { ![string is integer $value] } {
+                    set value [concat \"$value\"]
+                }
+
+                lappend slang_params -G "${key}=${value}"
+            }
+        }
+        yosys read_slang \
+            -D SYNTHESIS \
+            --keep-hierarchy \
+            --top $sc_design \
+            {*}$slang_params \
+            $input_verilog
+    } else {
+        # Use -noblackbox to correctly interpret empty modules as empty,
+        # actual black boxes are read in later
+        # https://github.com/YosysHQ/yosys/issues/1468
+        yosys read_verilog -noblackbox -sv $input_verilog
+
+        ########################################################
+        # Override top level parameters
+        ########################################################
+
+        sc_apply_params
+    }
 }
 
-########################################################
-# Override top level parameters
-########################################################
-
-sc_apply_params
-
 ########################################################
 # Synthesis based on mode
 ########################################################

siliconcompiler/tools/yosys/syn_asic.py

@@ -217,6 +217,33 @@ def setup_asic(chip):
     chip.set('tool', tool, 'task', task, 'file', 'synth_extra_map',
              'Files used in synthesis to perform additional techmapping', field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design',
+             'true/false, if true will attempt to lock the design with moosic',
+             field='help')
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'lock_design']),
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design_key',
+             'lock locking key',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design_port', 'moosic_key',
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design_port',
+             'lock locking port name',
+             field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'lock_design', step=step, index=index)[0] == \
+            'true':
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'lock_design_key']),
+                 step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'lock_design_port']),
+                 step=step, index=index)
+
 
 ################################
 # mark cells dont use and format liberty files for yosys and abc

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -217,6 +217,33 @@ if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "
 # Finish synthesis
 yosys synth {*}$synth_args -top $sc_design -run fine:check
 
+# Logic locking
+if { [lindex [sc_cfg_tool_task_get var lock_design] 0] == "true" } {
+    if { [sc_load_plugin moosic] } {
+        # moosic cannot handle hierarchy
+        foreach module [get_modules "*"] {
+            yosys select -module $module
+            yosys setattr -mod -unset keep_hierarchy
+            yosys select -clear
+        }
+        yosys flatten
+        yosys opt -fast
+
+        set ll_port [lindex [sc_cfg_tool_task_get var lock_design_port] 0]
+        set ll_key [lindex [sc_cfg_tool_task_get var lock_design_key] 0]
+        set ll_bits [expr { 4 * [string length $ll_key] }]
+        yosys select -module $sc_design
+        yosys logic_locking \
+            -nb-locked $ll_bits \
+            -key $ll_key \
+            -port-name $ll_port
+        yosys tee -o reports/logic_locking.rpt {ll_show}
+        yosys select -clear
+    } else {
+        puts "ERROR: unable to load moosic"
+    }
+}
+
 # https://github.com/hdl/bazel_rules_hdl/blob/4cca75f32a3869a57c0635bc7426a696a15ec143/synthesis/synth.tcl#L54C1-L58C26
 # Remove $print cells.  These cells represent Verilog $display() tasks.
 # Some place and route tools cannot handle these in the output Verilog,

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "3258b30e2c47d695ff2bb6c14a23c6779ed130bb",
+    "git-commit": "6e6fccbbe0ffbe683a51de3ecac2a24958a53fa1",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -45,7 +45,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "4ec99fcffd2c533c4a2c74ad6f56278f2672f05d",
+    "git-commit": "5d5723f65dd4501d17004736d7d048bea7ef2339",
     "auto-update": true
   },
   "verilator": {
@@ -136,5 +136,17 @@
     "git-commit": "v3.3.116",
     "git-url": "https://github.com/gtkwave/gtkwave.git",
     "auto-update": false
+  },
+  "yosys-slang": {
+    "git-url": "https://github.com/povik/yosys-slang.git",
+    "git-commit": "0adba99ea43331235506b9b154c78a401f4fe9b6",
+    "docker-depends": "yosys",
+    "auto-update": true
+  },
+  "yosys-moosic": {
+    "git-url": "https://github.com/gadfort/moosic-yosys-plugin.git",
+    "git-commit": "5dd1d8a60d0cc7228be856350bb90faad24dae9e",
+    "docker-depends": "yosys",
+    "auto-update": true
   }
 }

siliconcompiler/toolscripts/rhel8/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/rhel8/install-yosys-slang.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .yosys-slang --clear
+. .yosys-slang/bin/activate
+python3 -m pip install cmake
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-url) yosys-slang
+cd yosys-slang
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-commit)
+git submodule update --init --recursive
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/rhel9/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/rhel9/install-yosys-slang.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .yosys-slang --clear
+. .yosys-slang/bin/activate
+python3 -m pip install cmake
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-url) yosys-slang
+cd yosys-slang
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-commit)
+git submodule update --init --recursive
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu20/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu20/install-yosys-slang.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .yosys-slang --clear
+. .yosys-slang/bin/activate
+python3 -m pip install cmake
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-url) yosys-slang
+cd yosys-slang
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-commit)
+git submodule update --init --recursive
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu22/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu22/install-yosys-slang.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .yosys-slang --clear
+. .yosys-slang/bin/activate
+python3 -m pip install cmake
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-url) yosys-slang
+cd yosys-slang
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-commit)
+git submodule update --init --recursive
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu24/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -