siliconcompiler 0.29.3__py3-none-any.whl → 0.29.4__py3-none-any.whl

siliconcompiler/tools/yosys/__init__.py

@@ -12,7 +12,7 @@ Sources: https://github.com/YosysHQ/yosys
 
 Installation: https://github.com/YosysHQ/yosys
 '''
-
+import os
 import re
 import json
 from siliconcompiler import sc_open
@@ -107,28 +107,31 @@ def syn_post_process(chip):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
 
-    with sc_open("reports/stat.json") as f:
-        metrics = json.load(f)
-        if "design" in metrics:
-            metrics = metrics["design"]
-
-        if "area" in metrics:
-            record_metric(chip, step, index, 'cellarea',
-                          float(metrics["area"]),
-                          "reports/stat.json",
-                          source_unit='um^2')
-        if "num_cells" in metrics:
-            record_metric(chip, step, index, 'cells',
-                          metrics["num_cells"],
-                          "reports/stat.json")
-        if "num_wire_bits" in metrics:
-            record_metric(chip, step, index, 'nets',
-                          metrics["num_wire_bits"],
-                          "reports/stat.json")
-        if "num_port_bits" in metrics:
-            record_metric(chip, step, index, 'pins',
-                          metrics["num_port_bits"],
-                          "reports/stat.json")
+    if os.path.exists("reports/stat.json"):
+        with sc_open("reports/stat.json") as f:
+            metrics = json.load(f)
+            if "design" in metrics:
+                metrics = metrics["design"]
+
+            if "area" in metrics:
+                record_metric(chip, step, index, 'cellarea',
+                              float(metrics["area"]),
+                              "reports/stat.json",
+                              source_unit='um^2')
+            if "num_cells" in metrics:
+                record_metric(chip, step, index, 'cells',
+                              metrics["num_cells"],
+                              "reports/stat.json")
+            if "num_wire_bits" in metrics:
+                record_metric(chip, step, index, 'nets',
+                              metrics["num_wire_bits"],
+                              "reports/stat.json")
+            if "num_port_bits" in metrics:
+                record_metric(chip, step, index, 'pins',
+                              metrics["num_port_bits"],
+                              "reports/stat.json")
+    else:
+        chip.logger.warning("Yosys cell statistics are missing")
 
     registers = None
     with sc_open(f"{step}.log") as f:

siliconcompiler/tools/yosys/procs.tcl

@@ -52,3 +52,20 @@ proc sc_apply_params { } {
         }
     }
 }
+
+proc sc_get_scratchpad { name } {
+    yosys echo off
+    set value [yosys tee -q -s result.string scratchpad -get $name]
+    yosys echo on
+
+    return $value
+}
+
+proc sc_load_plugin { name } {
+    catch { yosys tee -q -s sc.load.test plugin -i $name }
+    set load_test [sc_get_scratchpad sc.load.test]
+    if { [string first "ERROR" $load_test] == -1 } {
+        return 1
+    }
+    return 0
+}

siliconcompiler/tools/yosys/syn_asic.py

@@ -8,6 +8,7 @@ from siliconcompiler import sc_open
 from siliconcompiler import utils
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
     CellArea
+from siliconcompiler.tools._common.asic_clock import get_clock_period
 from siliconcompiler.tools._common import get_tool_task
 
 
@@ -75,12 +76,11 @@ def setup_asic(chip):
     # set default control knobs
     mainlib = get_mainlib(chip)
     for option, value in [
-            ('flatten', "true"),
-            ('auto_flatten', "true"),
-            ('hier_iterations', "10"),
-            ('hier_threshold', "1000"),
-            ('autoname', "true"),
-            ('add_buffers', "true")]:
+            ('flatten', True),
+            ('auto_flatten', True),
+            ('hier_threshold', 1000),
+            ('autoname', True),
+            ('add_buffers', True)]:
         chip.set('tool', tool, 'task', task, 'var', option, value,
                  step=step, index=index, clobber=False)
         chip.add('tool', tool, 'task', task, 'require',
@@ -387,11 +387,9 @@ def _get_synthesis_library_key(chip, lib, corners):
 
 
 def get_abc_period(chip):
-
-    tool = 'yosys'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
     mainlib = get_mainlib(chip)
 
@@ -400,67 +398,16 @@ def get_abc_period(chip):
     if abc_clock_period:
         return abc_clock_period[0]
 
-    period = None
-
     abc_clock_multiplier = float(chip.get('library', mainlib, 'option', 'var',
                                           'yosys_abc_clock_multiplier')[0])
 
-    # get clock information from sdc files
-    # TODO: fix for fpga/asic differentiation later
-    if chip.valid('input', 'constraint', 'sdc'):
-        for sdc in chip.find_files('input', 'constraint', 'sdc', step=step, index=index):
-            lines = []
-            with sc_open(sdc) as f:
-                lines = f.read().splitlines()
-
-            # collect simple variables in case clock is specified with a variable
-            re_var = r"[A-Za-z0-9_]+"
-            re_num = r"[0-9\.]+"
-            sdc_vars = {}
-            for line in lines:
-                tcl_variable = re.findall(fr"^\s*set\s+({re_var})\s+({re_num})", line)
-                if tcl_variable:
-                    var_name, var_value = tcl_variable[0]
-                    sdc_vars[f'${var_name}'] = float(var_value)
-
-            # TODO: handle line continuations
-            for line in lines:
-                clock_period = re.findall(fr"create_clock\s.*-period\s+({re_num}|\${re_var})",
-                                          line)
-                if clock_period:
-                    clock_period = clock_period[0]
-                    if clock_period[0] == '$':
-                        if clock_period in sdc_vars:
-                            clock_period = sdc_vars[clock_period]
-                        else:
-                            chip.logger.warning('Unable to identify clock period from '
-                                                f'{clock_period}.')
-                            continue
-                    else:
-                        clock_period = float(clock_period)
-
-                    clock_period = clock_period * abc_clock_multiplier
-
-                    if period is None:
-                        period = clock_period
-                    else:
-                        period = min(period, clock_period)
-
-    if period is None:
-        # get clock information from defined clocks
-        for pin in chip.getkeys('datasheet', 'pin'):
-            for mode in chip.getkeys('datasheet', 'pin', pin, 'type'):
-                if chip.get('datasheet', 'pin', pin, 'type', mode) == 'clock':
-                    clock_period = min(chip.get('datasheet', 'pin', pin, 'tperiod', mode)) * 1e12
-
-                    if period is None:
-                        period = clock_period
-                    else:
-                        period = min(period, clock_period)
-
-    if period is None:
+    _, period = get_clock_period(chip,
+                                 clock_units_multiplier=abc_clock_multiplier / 1000)
+    if not period:
         return None
 
+    period *= 1000
+
     abc_clock_derating = chip.get('tool', tool, 'task', task, 'var', 'abc_clock_derating',
                                   step=step, index=index)
     if abc_clock_derating:

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -38,44 +38,6 @@ proc get_modules { { find "*" } } {
     return [lsort $modules]
 }
 
-proc determine_keep_hierarchy { iter cell_limit } {
-    global sc_design
-
-    # Grab only the modules and not the header and footer
-    set modules [get_modules]
-
-    # Save a copy of the current design so we can do a few optimizations and techmap
-    yosys design -save hierarchy_checkpoint
-    yosys techmap
-    yosys opt -fast -full -purge
-
-    set cell_counts [dict create]
-
-    foreach module $modules {
-        yosys stat -top $module
-        yosys echo off
-        set cells_count [yosys tee -q -s result.string scratchpad -get stat.num_cells]
-        yosys echo on
-        dict set cell_counts $module [expr { int($cells_count) }]
-    }
-
-    # Restore design
-    yosys design -load hierarchy_checkpoint
-    foreach module $modules {
-        yosys select -module $module
-        yosys setattr -mod -set keep_hierarchy \
-            [expr { [dict get $cell_counts $module] > $cell_limit }]
-        yosys select -clear
-    }
-
-    preserve_modules
-
-    # Rerun coarse synth with flatten
-    yosys synth -flatten -top $sc_design -run coarse:fine
-
-    return [expr { [llength $modules] != [llength [get_modules]] }]
-}
-
 ####################
 # DESIGNER's CHOICE
 ####################
@@ -171,11 +133,11 @@ proc get_buffer_cell { } {
 ########################################################
 
 foreach lib_file "$sc_libraries $sc_macro_libraries" {
-    yosys read_liberty -lib $lib_file
+    yosys read_liberty -setattr liberty_cell -lib $lib_file
 }
 foreach bb_file $sc_blackboxes {
     yosys log "Reading blackbox model file: $bb_file"
-    yosys read_verilog -sv $bb_file
+    yosys read_verilog -setattr blackbox -sv $bb_file
 }
 
 ########################################################
@@ -216,7 +178,6 @@ if {
     set sc_tbuf "true"
 
     yosys tribuf
-    yosys stat
 }
 
 set flatten_design [expr {
@@ -245,18 +206,12 @@ sc_map_memory $sc_memory_libmap_files $sc_memory_techmap_files 0
 
 # Perform hierarchy flattening
 if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "true" } {
-    yosys log -push
-    yosys log -header "SC Auto flattening"
-    set sc_hier_iterations \
-        [lindex [sc_cfg_tool_task_get var hier_iterations] 0]
     set sc_hier_threshold \
         [lindex [sc_cfg_tool_task_get var hier_threshold] 0]
-    for { set i 0 } { $i < $sc_hier_iterations } { incr i } {
-        if { [determine_keep_hierarchy $i $sc_hier_threshold] == 0 } {
-            break
-        }
-    }
-    yosys log -pop
+
+    yosys keep_hierarchy -min_cost $sc_hier_threshold
+
+    yosys synth -flatten {*}$synth_args -top $sc_design -run coarse:fine
 }
 
 # Finish synthesis

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "44e36144112da6b2a3bb346ca0d0b692b6d117ca",
+    "git-commit": "6645a5370f109cff49d7a735d81dae239df387c0",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -32,7 +32,7 @@
   },
   "bluespec": {
     "git-url": "https://github.com/B-Lang-org/bsc.git",
-    "git-commit": "4cac6ebae076e8b8378597aba1d2119aa29ec419",
+    "git-commit": "2024.07",
     "auto-update": false
   },
   "klayout": {

siliconcompiler/toolscripts/rhel8/install-yosys.sh

@@ -18,6 +18,6 @@ cd yosys
 git checkout $(python3 ${src_path}/_tools.py --tool yosys --field git-commit)
 git submodule update --init --recursive
 
-make -j$(nproc)
+make -j$(nproc) PREFIX="$PREFIX"
 sudo make install PREFIX="$PREFIX"
 cd -

siliconcompiler/toolscripts/rhel9/install-openroad.sh

@@ -0,0 +1,34 @@
+#!/bin/sh
+
+set -e
+
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool openroad --field git-url) openroad
+cd openroad
+git checkout $(python3 ${src_path}/_tools.py --tool openroad --field git-commit)
+git submodule update --init --recursive
+
+# Install missing dependencies
+sudo yum install -y bison byacc
+
+deps_args=""
+if [ ! -z ${PREFIX} ]; then
+    deps_args="-prefix=$PREFIX"
+fi
+sudo ./etc/DependencyInstaller.sh $deps_args
+
+cmake_args="-DENABLE_TESTS=OFF"
+if [ ! -z ${PREFIX} ]; then
+    cmake_args="$cmake_args -DCMAKE_INSTALL_PREFIX=$PREFIX"
+fi
+
+./etc/Build.sh -cmake="$cmake_args"
+
+cd build
+sudo make install
+
+cd -

siliconcompiler/toolscripts/rhel9/install-yosys.sh

@@ -18,6 +18,6 @@ cd yosys
 git checkout $(python3 ${src_path}/_tools.py --tool yosys --field git-commit)
 git submodule update --init --recursive
 
-make -j$(nproc)
+make -j$(nproc) PREFIX="$PREFIX"
 sudo make install PREFIX="$PREFIX"
 cd -

siliconcompiler/toolscripts/ubuntu20/install-yosys.sh

@@ -19,6 +19,6 @@ cd yosys
 git checkout $(python3 ${src_path}/_tools.py --tool yosys --field git-commit)
 git submodule update --init --recursive
 
-make -j$(nproc)
+make -j$(nproc) PREFIX="$PREFIX"
 sudo make install PREFIX="$PREFIX"
 cd -

siliconcompiler/toolscripts/ubuntu22/install-yosys.sh

@@ -19,6 +19,6 @@ cd yosys
 git checkout $(python3 ${src_path}/_tools.py --tool yosys --field git-commit)
 git submodule update --init --recursive
 
-make -j$(nproc)
+make -j$(nproc) PREFIX="$PREFIX"
 sudo make install PREFIX="$PREFIX"
 cd -

siliconcompiler/toolscripts/ubuntu24/install-yosys.sh

@@ -19,6 +19,6 @@ cd yosys
 git checkout $(python3 ${src_path}/_tools.py --tool yosys --field git-commit)
 git submodule update --init --recursive
 
-make -j$(nproc)
+make -j$(nproc) PREFIX="$PREFIX"
 sudo make install PREFIX="$PREFIX"
 cd -

siliconcompiler/utils/__init__.py

@@ -85,6 +85,7 @@ def get_default_iomap():
 
     # High level languages
     hll_c = ('c', 'cc', 'cpp', 'c++', 'cp', 'cxx', 'hpp', 'h')
+    hll_llvm = ('ll',)
     hll_bsv = ('bsv',)
     hll_scala = ('scala',)
     hll_python = ('py',)
@@ -132,6 +133,7 @@ def get_default_iomap():
     # Build default map with fileset and type
     default_iomap = {}
     default_iomap.update({ext: ('hll', 'c') for ext in hll_c})
+    default_iomap.update({ext: ('hll', 'llvm') for ext in hll_llvm})
     default_iomap.update({ext: ('hll', 'bsv') for ext in hll_bsv})
     default_iomap.update({ext: ('hll', 'scala') for ext in hll_scala})
     default_iomap.update({ext: ('hll', 'python') for ext in hll_python})

{siliconcompiler-0.29.3.dist-info → siliconcompiler-0.29.4.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.2
 Name: siliconcompiler
-Version: 0.29.3
+Version: 0.29.4
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -38,7 +38,7 @@ Requires-Dist: psutil>=5.8.0
 Requires-Dist: Pillow==10.4.0; python_version <= "3.8"
 Requires-Dist: Pillow==11.1.0; python_version >= "3.9"
 Requires-Dist: GitPython==3.1.44
-Requires-Dist: lambdapdk>=0.1.46
+Requires-Dist: lambdapdk>=0.1.47
 Requires-Dist: PyGithub==2.5.0
 Requires-Dist: urllib3>=1.26.0
 Requires-Dist: fasteners==0.19
@@ -58,7 +58,7 @@ Requires-Dist: pytest==8.3.4; extra == "test"
 Requires-Dist: pytest-xdist==3.6.1; extra == "test"
 Requires-Dist: pytest-timeout==2.3.1; extra == "test"
 Requires-Dist: pytest-asyncio==0.24.0; python_version <= "3.8" and extra == "test"
-Requires-Dist: pytest-asyncio==0.25.2; python_version >= "3.9" and extra == "test"
+Requires-Dist: pytest-asyncio==0.25.3; python_version >= "3.9" and extra == "test"
 Requires-Dist: pytest-cov==5.0.0; python_version <= "3.8" and extra == "test"
 Requires-Dist: pytest-cov==6.0.0; python_version >= "3.9" and extra == "test"
 Requires-Dist: responses==0.25.6; extra == "test"
@@ -66,7 +66,7 @@ Requires-Dist: PyVirtualDisplay==3.0; extra == "test"
 Provides-Extra: lint
 Requires-Dist: flake8==7.1.1; extra == "lint"
 Requires-Dist: tclint==0.5.0; extra == "lint"
-Requires-Dist: codespell==2.4.0; extra == "lint"
+Requires-Dist: codespell==2.4.1; extra == "lint"
 Provides-Extra: docs
 Requires-Dist: Sphinx==8.1.3; extra == "docs"
 Requires-Dist: pip-licenses==5.0.0; extra == "docs"
@@ -195,7 +195,7 @@ python3 -m pip install -e .[docs,test]  # Optional install step for generating d
 Installation instructions for all external tools can be found in the
 [External Tools](https://docs.siliconcompiler.com/en/stable/user_guide/installation.html#external-tools) section
 of the user guide. We have included shell setup scripts (Ubuntu) for most of the supported tools.
-See the [./setup](./setup) directory for a complete set of scripts and [./setup/_tools.json](./setup/_tools.json) for the currently recommended tool versions.
+See the [./siliconcompiler/toolscripts](./siliconcompiler/toolscripts) directory for a complete set of scripts and [./siliconcompiler/toolscripts/_tools.json](./siliconcompiler/toolscripts/_tools.json) for the currently recommended tool versions.
 
 # Contributing