siliconcompiler 0.28.7__py3-none-any.whl → 0.28.9__py3-none-any.whl

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (36) hide show
  1. siliconcompiler/_metadata.py +1 -1
  2. siliconcompiler/report/dashboard/components/graph.py +11 -6
  3. siliconcompiler/report/dashboard/layouts/vertical_flowgraph.py +1 -1
  4. siliconcompiler/report/dashboard/layouts/vertical_flowgraph_node_tab.py +1 -1
  5. siliconcompiler/report/dashboard/layouts/vertical_flowgraph_sac_tabs.py +1 -1
  6. siliconcompiler/report/report.py +20 -1
  7. siliconcompiler/scheduler/send_messages.py +37 -33
  8. siliconcompiler/scheduler/validation/email_credentials.json +7 -0
  9. siliconcompiler/targets/fpgaflow_demo.py +6 -7
  10. siliconcompiler/tools/_common/__init__.py +2 -2
  11. siliconcompiler/tools/_common/asic.py +47 -0
  12. siliconcompiler/tools/klayout/klayout_show.py +53 -13
  13. siliconcompiler/tools/openroad/openroad.py +121 -4
  14. siliconcompiler/tools/openroad/scripts/sc_procs.tcl +9 -0
  15. siliconcompiler/tools/openroad/scripts/sc_report.tcl +19 -0
  16. siliconcompiler/tools/vivado/bitstream.py +8 -2
  17. siliconcompiler/tools/vivado/place.py +6 -2
  18. siliconcompiler/tools/vivado/route.py +6 -2
  19. siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl +1 -1
  20. siliconcompiler/tools/vivado/scripts/sc_place.tcl +1 -1
  21. siliconcompiler/tools/vivado/scripts/sc_route.tcl +1 -1
  22. siliconcompiler/tools/vivado/scripts/sc_run.tcl +4 -2
  23. siliconcompiler/tools/vivado/syn_fpga.py +5 -1
  24. siliconcompiler/tools/vivado/vivado.py +26 -10
  25. siliconcompiler/tools/vpr/vpr.py +11 -0
  26. siliconcompiler/tools/yosys/syn_asic.tcl +3 -0
  27. siliconcompiler/toolscripts/_tools.json +2 -2
  28. siliconcompiler/utils/__init__.py +12 -5
  29. siliconcompiler/utils/showtools.py +2 -0
  30. {siliconcompiler-0.28.7.dist-info → siliconcompiler-0.28.9.dist-info}/METADATA +48 -47
  31. {siliconcompiler-0.28.7.dist-info → siliconcompiler-0.28.9.dist-info}/RECORD +35 -36
  32. {siliconcompiler-0.28.7.dist-info → siliconcompiler-0.28.9.dist-info}/WHEEL +1 -1
  33. siliconcompiler/toolscripts/rhel8/install-openroad.sh +0 -31
  34. {siliconcompiler-0.28.7.dist-info → siliconcompiler-0.28.9.dist-info}/LICENSE +0 -0
  35. {siliconcompiler-0.28.7.dist-info → siliconcompiler-0.28.9.dist-info}/entry_points.txt +0 -0
  36. {siliconcompiler-0.28.7.dist-info → siliconcompiler-0.28.9.dist-info}/top_level.txt +0 -0
@@ -1,2 +1,2 @@
1
- open_checkpoint "inputs/${sc_design}_checkpoint.dcp"
1
+ open_checkpoint "inputs/${sc_design}.dcp"
2
2
  place_design
@@ -1,4 +1,4 @@
1
- open_checkpoint "inputs/${sc_design}_checkpoint.dcp"
1
+ open_checkpoint "inputs/${sc_design}.dcp"
2
2
  phys_opt_design
3
3
  power_opt_design
4
4
  route_design
@@ -28,7 +28,9 @@ source $sc_refdir/sc_$sc_task.tcl
28
28
  # Checkpoint
29
29
  ##############################
30
30
 
31
- write_checkpoint -force "outputs/${sc_design}_checkpoint"
31
+ write_checkpoint -force "outputs/${sc_design}"
32
+ write_xdc "outputs/${sc_design}.xdc"
33
+ write_verilog "outputs/${sc_design}.vg"
32
34
 
33
35
  ##############################
34
36
  # Reports / Metrics
@@ -41,4 +43,4 @@ report_clock_utilization -file "reports/clock_utilization.rpt"
41
43
  report_drc -file "reports/drc.rpt"
42
44
  report_cdc -details -file "reports/cdc.rpt"
43
45
 
44
- report_design_analysis -qor_summary -json "qor_summary.json"
46
+ report_design_analysis -qor_summary -json "reports/qor_summary.json"
@@ -12,7 +12,11 @@ def setup(chip):
12
12
 
13
13
  design = chip.top()
14
14
  chip.set('tool', tool, 'task', task, 'input', f'{design}.v', step=step, index=index)
15
- chip.set('tool', tool, 'task', task, 'output', f'{design}_checkpoint.dcp',
15
+ chip.set('tool', tool, 'task', task, 'output', f'{design}.dcp',
16
+ step=step, index=index)
17
+ chip.add('tool', tool, 'task', task, 'output', f'{design}.xdc',
18
+ step=step, index=index)
19
+ chip.add('tool', tool, 'task', task, 'output', f'{design}.vg',
16
20
  step=step, index=index)
17
21
 
18
22
 
@@ -67,36 +67,52 @@ def normalize_version(version):
67
67
 
68
68
 
69
69
  def _parse_qor_summary(chip, step, index):
70
- if not os.path.isfile('qor_summary.json'):
70
+ if not os.path.isfile('reports/qor_summary.json'):
71
71
  return
72
72
 
73
- with sc_open('qor_summary.json') as f:
73
+ with sc_open('reports/qor_summary.json') as f:
74
74
  data = json.load(f)
75
75
 
76
76
  # Data is organized as list of tasks that Vivado has completed, with
77
77
  # metrics associated with each. The tasks appear to be in chronological
78
78
  # order, so we pull metrics from the last one.
79
79
  task = data['Design QoR Summary'][-1]
80
- setup_wns = task['Wns(ns)']
81
- setup_tns = task['Tns(ns)']
82
- hold_wns = task['Whs(ns)']
83
- hold_tns = task['Ths(ns)']
80
+ setup_wns = None
81
+ for metric in ('Wns(ns)', 'WNS(ns)'):
82
+ if metric in task:
83
+ setup_wns = task[metric]
84
+ break
85
+ setup_tns = None
86
+ for metric in ('Tns(ns)', 'TNS(ns)'):
87
+ if metric in task:
88
+ setup_tns = task[metric]
89
+ break
90
+ hold_wns = None
91
+ for metric in ('Whs(ns)', 'WHS(ns)'):
92
+ if metric in task:
93
+ hold_wns = task[metric]
94
+ break
95
+ hold_tns = None
96
+ for metric in ('Ths(ns)', 'THS(ns)'):
97
+ if metric in task:
98
+ hold_tns = task[metric]
99
+ break
84
100
 
85
101
  if setup_wns:
86
102
  record_metric(chip, step, index, 'setupwns', setup_wns,
87
- 'qor_summary.json',
103
+ 'reports/qor_summary.json',
88
104
  source_unit='ns')
89
105
  if setup_tns:
90
106
  record_metric(chip, step, index, 'setuptns', setup_tns,
91
- 'qor_summary.json',
107
+ 'reports/qor_summary.json',
92
108
  source_unit='ns')
93
109
  if hold_wns:
94
110
  record_metric(chip, step, index, 'holdwns', hold_wns,
95
- 'qor_summary.json',
111
+ 'reports/qor_summary.json',
96
112
  source_unit='ns')
97
113
  if hold_tns:
98
114
  record_metric(chip, step, index, 'holdtns', hold_tns,
99
- 'qor_summary.json',
115
+ 'reports/qor_summary.json',
100
116
  source_unit='ns')
101
117
 
102
118
 
@@ -94,6 +94,11 @@ def runtime_options(chip):
94
94
 
95
95
  options.append(f"--device {device_code[0]}")
96
96
 
97
+ # Medium-term solution: VPR performs hash digest checks that
98
+ # fail if file paths are changed between steps. We wish to
99
+ # disable the digest checks to work around this
100
+ options.append("--verify_file_digests off")
101
+
97
102
  options.append(f"--write_block_usage {__block_file}")
98
103
  options.append("--outfile_prefix outputs/")
99
104
 
@@ -128,6 +133,12 @@ def runtime_options(chip):
128
133
  # If we allow VPR to sweep dangling primary I/Os and logic blocks
129
134
  # it can interfere with circuit debugging; so disable that
130
135
  options.append('--sweep_dangling_primary_ios off')
136
+ # If you don't sweep dangling primary I/Os, but sweeping nets
137
+ # VPR can crash:
138
+ options.append('--sweep_dangling_nets off')
139
+ # If you don't sweep dangling nets then the timing engine requires
140
+ # you to set an option allowing dangling nodes
141
+ options.append('--allow_dangling_combinational_nodes on')
131
142
  options.append('--sweep_constant_primary_outputs off')
132
143
  options.append('--sweep_dangling_blocks off')
133
144
 
@@ -231,6 +231,8 @@ sc_map_memory $sc_memory_libmap_files $sc_memory_techmap_files 0
231
231
 
232
232
  # Perform hierarchy flattening
233
233
  if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "true" } {
234
+ yosys log -push
235
+ yosys log -header "SC Auto flattening"
234
236
  set sc_hier_iterations \
235
237
  [lindex [sc_cfg_tool_task_get var hier_iterations] 0]
236
238
  set sc_hier_threshold \
@@ -240,6 +242,7 @@ if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "
240
242
  break
241
243
  }
242
244
  }
245
+ yosys log -pop
243
246
  }
244
247
 
245
248
  # Finish synthesis
@@ -1,7 +1,7 @@
1
1
  {
2
2
  "openroad": {
3
3
  "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
4
- "git-commit": "dcba5786c8e714e3b7682a98d73de40e875699b1",
4
+ "git-commit": "8300b5293dec4c0a0ef26cd2ba7ca6101714e155",
5
5
  "docker-cmds": [
6
6
  "# Remove OR-Tools files",
7
7
  "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -66,7 +66,7 @@
66
66
  },
67
67
  "vpr": {
68
68
  "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
69
- "git-commit": "9dd5ff66e3ab43238f5a4cb14cafe17bc4afe527",
69
+ "git-commit": "de31f094aa4f894a5e6e0dc32c66365f4b341190",
70
70
  "auto-update": false
71
71
  },
72
72
  "icepack": {
@@ -84,7 +84,7 @@ def get_default_iomap():
84
84
  # Record extensions:
85
85
 
86
86
  # High level languages
87
- hll_c = ('c', 'cc', 'cpp', 'c++', 'cp', 'cxx', 'hpp')
87
+ hll_c = ('c', 'cc', 'cpp', 'c++', 'cp', 'cxx', 'hpp', 'h')
88
88
  hll_bsv = ('bsv',)
89
89
  hll_scala = ('scala',)
90
90
  hll_python = ('py',)
@@ -92,8 +92,8 @@ def get_default_iomap():
92
92
  config_chisel = ('sbt',)
93
93
 
94
94
  # Register transfer languages
95
- rtl_verilog = ('v', 'verilog')
96
- rtl_systemverilog = ('sv',)
95
+ rtl_verilog = ('v', 'verilog', 'vh')
96
+ rtl_systemverilog = ('sv', 'svh')
97
97
  rtl_vhdl = ('vhd', 'vhdl')
98
98
 
99
99
  # Timing libraries
@@ -116,8 +116,8 @@ def get_default_iomap():
116
116
  waveform_vcd = ('vcd',)
117
117
 
118
118
  # Constraint
119
- constraint_sdc = ('sdc', )
120
- constraint_upf = ('upf', )
119
+ constraint_sdc = ('sdc',)
120
+ constraint_upf = ('upf',)
121
121
 
122
122
  # FPGA constraints
123
123
  fpga_xdc = ('xdc',)
@@ -125,6 +125,10 @@ def get_default_iomap():
125
125
  fpga_vpr_place = ('place',)
126
126
  fpga_vpr_route = ('route',)
127
127
 
128
+ # Reports
129
+ report_drc = ('lyrdb', 'ascii')
130
+ report_log = ('log',)
131
+
128
132
  # Build default map with fileset and type
129
133
  default_iomap = {}
130
134
  default_iomap.update({ext: ('hll', 'c') for ext in hll_c})
@@ -160,6 +164,9 @@ def get_default_iomap():
160
164
  default_iomap.update({ext: ('fpga', 'vpr_place') for ext in fpga_vpr_place})
161
165
  default_iomap.update({ext: ('fpga', 'vpr_route') for ext in fpga_vpr_route})
162
166
 
167
+ default_iomap.update({ext: ('report', 'drc') for ext in report_drc})
168
+ default_iomap.update({ext: ('report', 'log') for ext in report_log})
169
+
163
170
  return default_iomap
164
171
 
165
172
 
@@ -14,6 +14,8 @@ def setup(chip):
14
14
  chip.register_showtool('oas', klayout_screenshot)
15
15
  chip.register_showtool('lef', klayout_show)
16
16
  chip.register_showtool('lef', klayout_screenshot)
17
+ chip.register_showtool('lyrdb', klayout_show)
18
+ chip.register_showtool('ascii', klayout_show)
17
19
 
18
20
  chip.register_showtool('odb', openroad_show)
19
21
  chip.register_showtool('odb', openroad_screenshot)
@@ -1,6 +1,6 @@
1
1
  Metadata-Version: 2.1
2
2
  Name: siliconcompiler
3
- Version: 0.28.7
3
+ Version: 0.28.9
4
4
  Summary: A compiler framework that automates translation from source code to silicon.
5
5
  Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
6
6
  License: Apache License 2.0
@@ -25,54 +25,55 @@ Classifier: Topic :: Software Development :: Build Tools
25
25
  Requires-Python: >=3.8
26
26
  Description-Content-Type: text/markdown
27
27
  License-File: LICENSE
28
- Requires-Dist: aiohttp ==3.10.10
29
- Requires-Dist: requests ==2.32.3
30
- Requires-Dist: PyYAML ==6.0.2
31
- Requires-Dist: pandas >=1.1.5
32
- Requires-Dist: Jinja2 >=2.11.3
33
- Requires-Dist: graphviz ==0.20.3
34
- Requires-Dist: distro ==1.9.0
35
- Requires-Dist: packaging <24,>=21.3
36
- Requires-Dist: psutil >=5.8.0
37
- Requires-Dist: GitPython ==3.1.43
38
- Requires-Dist: lambdapdk >=0.1.38
39
- Requires-Dist: PyGithub ==2.5.0
40
- Requires-Dist: urllib3 >=1.26.0
41
- Requires-Dist: fasteners ==0.19
42
- Requires-Dist: fastjsonschema ==2.20.0
43
- Requires-Dist: docker ==7.1.0
44
- Requires-Dist: sc-surelog ==1.84.1
45
- Requires-Dist: orjson ==3.10.11
46
- Requires-Dist: streamlit ==1.40.0 ; python_full_version != "3.9.7"
47
- Requires-Dist: streamlit-agraph ==0.0.45 ; python_full_version != "3.9.7"
48
- Requires-Dist: streamlit-antd-components ==0.3.2 ; python_full_version != "3.9.7"
49
- Requires-Dist: streamlit-javascript ==0.1.5 ; python_full_version != "3.9.7"
50
- Requires-Dist: streamlit-autorefresh ==1.0.1 ; python_full_version != "3.9.7"
51
- Requires-Dist: importlib-metadata ; python_version < "3.10"
52
- Requires-Dist: Pillow ==10.4.0 ; python_version <= "3.8"
53
- Requires-Dist: Pillow ==11.0.0 ; python_version >= "3.9"
28
+ Requires-Dist: aiohttp==3.10.11; python_version <= "3.8"
29
+ Requires-Dist: aiohttp==3.11.2; python_version >= "3.9"
30
+ Requires-Dist: requests==2.32.3
31
+ Requires-Dist: PyYAML==6.0.2
32
+ Requires-Dist: pandas>=1.1.5
33
+ Requires-Dist: Jinja2>=2.11.3
34
+ Requires-Dist: graphviz==0.20.3
35
+ Requires-Dist: distro==1.9.0
36
+ Requires-Dist: packaging<24,>=21.3
37
+ Requires-Dist: psutil>=5.8.0
38
+ Requires-Dist: Pillow==10.4.0; python_version <= "3.8"
39
+ Requires-Dist: Pillow==11.0.0; python_version >= "3.9"
40
+ Requires-Dist: GitPython==3.1.43
41
+ Requires-Dist: lambdapdk>=0.1.38
42
+ Requires-Dist: PyGithub==2.5.0
43
+ Requires-Dist: urllib3>=1.26.0
44
+ Requires-Dist: fasteners==0.19
45
+ Requires-Dist: fastjsonschema==2.20.0
46
+ Requires-Dist: docker==7.1.0
47
+ Requires-Dist: importlib_metadata; python_version < "3.10"
48
+ Requires-Dist: sc-surelog==1.84.1
49
+ Requires-Dist: orjson==3.10.11
50
+ Requires-Dist: streamlit==1.40.1; python_full_version != "3.9.7"
51
+ Requires-Dist: streamlit_agraph==0.0.45; python_full_version != "3.9.7"
52
+ Requires-Dist: streamlit-antd-components==0.3.2; python_full_version != "3.9.7"
53
+ Requires-Dist: streamlit_javascript==0.1.5; python_full_version != "3.9.7"
54
+ Requires-Dist: streamlit-autorefresh==1.0.1; python_full_version != "3.9.7"
55
+ Provides-Extra: test
56
+ Requires-Dist: pytest==8.3.3; extra == "test"
57
+ Requires-Dist: pytest-xdist==3.6.1; extra == "test"
58
+ Requires-Dist: pytest-timeout==2.3.1; extra == "test"
59
+ Requires-Dist: pytest-asyncio==0.24.0; extra == "test"
60
+ Requires-Dist: pytest-cov==5.0.0; python_version <= "3.8" and extra == "test"
61
+ Requires-Dist: pytest-cov==6.0.0; python_version >= "3.9" and extra == "test"
62
+ Requires-Dist: responses==0.25.3; extra == "test"
63
+ Requires-Dist: PyVirtualDisplay==3.0; extra == "test"
64
+ Requires-Dist: flake8==7.1.1; extra == "test"
65
+ Requires-Dist: tclint==0.4.2; extra == "test"
66
+ Requires-Dist: codespell==2.3.0; extra == "test"
54
67
  Provides-Extra: docs
55
- Requires-Dist: Sphinx ==8.1.3 ; extra == 'docs'
56
- Requires-Dist: pip-licenses ==5.0.0 ; extra == 'docs'
57
- Requires-Dist: pydata-sphinx-theme ==0.16.0 ; extra == 'docs'
58
- Requires-Dist: sc-leflib >=0.2.0 ; extra == 'docs'
59
- Provides-Extra: examples
60
- Requires-Dist: migen ==0.9.2 ; extra == 'examples'
61
- Requires-Dist: lambdalib ==0.3.1 ; extra == 'examples'
68
+ Requires-Dist: Sphinx==8.1.3; extra == "docs"
69
+ Requires-Dist: pip-licenses==5.0.0; extra == "docs"
70
+ Requires-Dist: pydata-sphinx-theme==0.16.0; extra == "docs"
71
+ Requires-Dist: sc-leflib>=0.2.0; extra == "docs"
62
72
  Provides-Extra: profile
63
- Requires-Dist: gprof2dot ==2024.6.6 ; extra == 'profile'
64
- Provides-Extra: test
65
- Requires-Dist: pytest ==8.3.3 ; extra == 'test'
66
- Requires-Dist: pytest-xdist ==3.6.1 ; extra == 'test'
67
- Requires-Dist: pytest-timeout ==2.3.1 ; extra == 'test'
68
- Requires-Dist: pytest-asyncio ==0.24.0 ; extra == 'test'
69
- Requires-Dist: responses ==0.25.3 ; extra == 'test'
70
- Requires-Dist: PyVirtualDisplay ==3.0 ; extra == 'test'
71
- Requires-Dist: flake8 ==7.1.1 ; extra == 'test'
72
- Requires-Dist: tclint ==0.4.2 ; extra == 'test'
73
- Requires-Dist: codespell ==2.3.0 ; extra == 'test'
74
- Requires-Dist: pytest-cov ==5.0.0 ; (python_version <= "3.8") and extra == 'test'
75
- Requires-Dist: pytest-cov ==6.0.0 ; (python_version >= "3.9") and extra == 'test'
73
+ Requires-Dist: gprof2dot==2024.6.6; extra == "profile"
74
+ Provides-Extra: examples
75
+ Requires-Dist: migen==0.9.2; extra == "examples"
76
+ Requires-Dist: lambdalib==0.3.1; extra == "examples"
76
77
 
77
78
  ![SiliconCompiler](https://raw.githubusercontent.com/siliconcompiler/siliconcompiler/main/docs/_static/sc_logo_with_text.png)
78
79
 
@@ -1,7 +1,7 @@
1
1
  siliconcompiler/__init__.py,sha256=Ke_Bcryj9N6MoUq_5z_IDW3qMrUzR-3-kJVsvUenYzY,511
2
2
  siliconcompiler/__main__.py,sha256=JwWkcvaNngqgMWprEQ1cFy2Wdq9GMvk46UGTHyh_qvM,170
3
3
  siliconcompiler/_common.py,sha256=c6r0SbI2xTpNOZayFsyCDo0riJGNJSPN-0zW8R7rDBI,1488
4
- siliconcompiler/_metadata.py,sha256=uHqTgPki2c0kr5ODJxHpeZjAGsSPLAYzpKQui1WbfCk,1264
4
+ siliconcompiler/_metadata.py,sha256=ISw0dgmSuNTS8xpsds6hA2uMv313WiLdIUnkF-qEI30,1264
5
5
  siliconcompiler/core.py,sha256=_T1eEY7lUsrbaEBUaG1WSAzY2JFxyz5tXEKxvoCGZaI,135718
6
6
  siliconcompiler/flowgraph.py,sha256=WLcbBWFj5DdYRRIxNy_Djm2v4yN9WELQM_ypNPB5QVM,21963
7
7
  siliconcompiler/issue.py,sha256=9ZpdEBh8QB56-bZ1YXRnjqgg9hwnFty2u1o5oI66W7M,11125
@@ -80,7 +80,7 @@ siliconcompiler/remote/server_schema/responses/get_results.json,sha256=h4XraLW4h
80
80
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- siliconcompiler/targets/fpgaflow_demo.py,sha256=-2L8Xi-TIB5FBuIxxB88Y9JagTTOXDHZcNFFwPU-sno,1379
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@@ -138,8 +138,8 @@ siliconcompiler/templates/slurm/run.sh,sha256=uXs91H0vjLB8G8vaezxXSr3XNR2EUiXH1d
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+ siliconcompiler/tools/_common/__init__.py,sha256=tCH4wk6hTQwS19pkVpOiN2MW1GbsFjKkPoarELzq5FQ,14525
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+ siliconcompiler/tools/_common/asic.py,sha256=0-yMpvuMBy2dzN6uRFC96z8mN-7Ndzj7LhiMuR2MKtk,6469
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@@ -188,7 +188,7 @@ siliconcompiler/tools/klayout/klayout.py,sha256=w0iqtdr_tjwH31hgdpCuCZlRByev3c7r
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- siliconcompiler/tools/klayout/klayout_show.py,sha256=jZk_p9D3wZ_VjSmiRh71SQ6AduOkFEMVErKvGzWF1P8,9127
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+ siliconcompiler/tools/klayout/klayout_show.py,sha256=G0buKR41h41VCxlkhFhWdeHiuMJHmnrVFxT8AaGzuA8,11069
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@@ -217,7 +217,7 @@ siliconcompiler/tools/openroad/dfm.py,sha256=RjdOqq7oPVSx5HzYUTSlBh4ZGnVfJqJHR0c
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+ siliconcompiler/tools/openroad/openroad.py,sha256=Tcte1Vk5zV2LyhNi1gycj2hW8IQ9C86GBtUG2_vP_J8,50463
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@@ -235,12 +235,12 @@ siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl,sha256=XufELL8Ys4kUrSSQw
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- siliconcompiler/tools/openroad/scripts/sc_procs.tcl,sha256=1OtBZJiy9zZgCzD6uDqCtFJrSu1n8kO0EoeVVXx0Ctc,12426
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+ siliconcompiler/tools/openroad/scripts/sc_procs.tcl,sha256=ZjLhdb0ddjFMn_ATbVRhGRrgUC1bi4aCfHNjbDosHIQ,12640
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- siliconcompiler/tools/openroad/scripts/sc_report.tcl,sha256=mVZaVB3bEp6DQkdzP3m-uzqAIIbslnA5lCmmkJmHZfw,5477
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+ siliconcompiler/tools/openroad/scripts/sc_report.tcl,sha256=lrMQ5j41xIXA5a6Q_6EejAT2P0dj3gMBwwGNjKdSN2I,6208
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@@ -271,16 +271,16 @@ siliconcompiler/tools/verilator/lint.py,sha256=Lp-PXk6kYtnemN2cMuvCyZxodDIDzLEmK
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- siliconcompiler/tools/vivado/bitstream.py,sha256=eZ0Kb6XuwG0lbT9C1RBoUHC27oTaLcK4YLRgByIAU5Y,669
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- siliconcompiler/tools/vivado/place.py,sha256=L-Z1CAQDQO4zG96rcuqcozCyfPAWvQB-iP2JWk1Kv4U,657
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- siliconcompiler/tools/vivado/route.py,sha256=1lVPJn9zKP4YT1D-YtltcytrYYmHhCdc2SaY4-RBvto,655
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- siliconcompiler/tools/vivado/syn_fpga.py,sha256=3C1CQJs5XibX6FbqzMsUq0Ck0TzQG57PTxzbjECFL9o,636
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- siliconcompiler/tools/vivado/vivado.py,sha256=O59TKyGnokuKKzPcOk7PXfMfEmQFHYOkN6WTcfBPvO4,4960
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+ siliconcompiler/tools/vivado/bitstream.py,sha256=361b51W7S_0umzGx_Q7VaXFRHpmanrJiNZCXTS5sXkg,972
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+ siliconcompiler/tools/vivado/place.py,sha256=tvD4-pPeJ-pjptaytY7jTrbllYyYgsDv59NWPvH-eSU,844
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+ siliconcompiler/tools/vivado/route.py,sha256=OiYWbVxBjlibDla-KTOXVbUtcg8LPsCUtuLhCc7zDfo,842
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+ siliconcompiler/tools/vivado/syn_fpga.py,sha256=MkcB0d7RjfKhyrCtCUlgDdfbFRu1Z3NQsu8Canw74cI,834
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+ siliconcompiler/tools/vivado/vivado.py,sha256=3k3iWV6pGivslG377tVGowOW5KvhoamzX2HXnRa4mYg,5522
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- siliconcompiler/tools/vivado/scripts/sc_place.tcl,sha256=0smyg_IMSoNCbJnlItnQi3JQdmSGwvBe1SJj5U37uJM,66
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- siliconcompiler/tools/vivado/scripts/sc_route.tcl,sha256=GcMHmtYChB66igTmhtIP24xWlQjlVEw5y0Heaq1_NXQ,99
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- siliconcompiler/tools/vivado/scripts/sc_run.tcl,sha256=46nBe16DW16S15VF_fj9T_ktHDFn7BKKXiue6ig3at8,1285
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+ siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl,sha256=77ftp1FdB7KQ9raHYR2Dd66Fs61dwmqXeUiP4tXK_6o,219
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+ siliconcompiler/tools/vivado/scripts/sc_place.tcl,sha256=x-3Tu9ZranEJFrqekyuFB1eru6LomCcw3IQiM0Jl_A4,55
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+ siliconcompiler/tools/vivado/scripts/sc_route.tcl,sha256=yqkSukM7FmDvQVyz5D7xdtSbHyQHQrshHPD-0H_Asww,88
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+ siliconcompiler/tools/vivado/scripts/sc_run.tcl,sha256=ycNYc71Sfw7KUxU4yZ8T6NCypWoRRW4nWX8yE5PZ-Q4,1359
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@@ -289,7 +289,7 @@ siliconcompiler/tools/vpr/place.py,sha256=CwzEmQELZ5IUnQ6lg964icDhmcBOxcNI32Ysdg
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  siliconcompiler/tools/vpr/show.py,sha256=Dm0efQaOa2G6FsDeo6BpNYEp0farqKQOXeF_JLBuSYo,3120
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- siliconcompiler/tools/vpr/vpr.py,sha256=MjHf4J5s1Hz05SG_dOxrnQAR9hTv980339xH67hI5B4,14091
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+ siliconcompiler/tools/vpr/vpr.py,sha256=tg6D_RqZXB7aRGnQInV01v92qnSFTwA7-3vB1x88s54,14641
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  siliconcompiler/tools/xdm/__init__.py,sha256=uEo7uTPRdoARmk0E5U8yQ_MZOntO-cWJfGb6_pPA0ZQ,729
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  siliconcompiler/tools/xyce/__init__.py,sha256=YTSk-XGtviqthGmGHb6RCDEAIMUQ7ElYZjZzpa1aSBg,1297
@@ -303,7 +303,7 @@ siliconcompiler/tools/yosys/sc_screenshot.tcl,sha256=-7Bb-HhJsZjSdSIlYCTZnZgigwB
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  siliconcompiler/tools/yosys/syn_asic.py,sha256=jEYfQTaTIPj4UHY2AKJocW3wMW2Prtgu6t55esNpZ_E,24106
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- siliconcompiler/tools/yosys/syn_asic.tcl,sha256=kws8B7e7_2Z_Bat2_3D9SnKmuNWpuuIAHy02kpGwe5Y,11875
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+ siliconcompiler/tools/yosys/syn_asic.tcl,sha256=MNUmV_qdkHfgDAPDb0urVwRLE65Y5xNodGOW4Zo7nTM,11957
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  siliconcompiler/tools/yosys/syn_strategies.tcl,sha256=YJ5bXCdUNDZZ4EY4wBGS-9m0EeNlANBIO9e5a_6A0KA,5329
@@ -312,7 +312,7 @@ siliconcompiler/tools/yosys/techmaps/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeu
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  siliconcompiler/tools/yosys/templates/abc.const,sha256=TAq9ThdLMYCJGrtToEU0gWcLuEtjE4Gk8huBbTm1v-I,116
315
- siliconcompiler/toolscripts/_tools.json,sha256=wTknmgxxAimBLm0crN_uDsJ40sbt-rUQFEMAbc37qiA,3959
315
+ siliconcompiler/toolscripts/_tools.json,sha256=jeawsNVi9BJWSeMiIxX0_0mDjv0-WddcU5a_Rm5uPIw,3959
316
316
  siliconcompiler/toolscripts/_tools.py,sha256=P30KY_xbbjl8eHGsPAxDcAzWvJJpiL07ZfGZZDQbdR8,7174
317
317
  siliconcompiler/toolscripts/rhel8/install-chisel.sh,sha256=lPORZN7vlBX6sJSv01JOIiDE9-_7GcCZGA7EP5ri3MQ,525
318
318
  siliconcompiler/toolscripts/rhel8/install-ghdl.sh,sha256=xCLeEUuJVI_6PVEvnTwBsTWoEHiQg0TY3x-tJXfg6Zk,459
@@ -321,7 +321,6 @@ siliconcompiler/toolscripts/rhel8/install-klayout.sh,sha256=lUCSc0Yr0NBUMVragNyJ
321
321
  siliconcompiler/toolscripts/rhel8/install-magic.sh,sha256=ugiH7ybdxQggs0ucUHiVtCOO142XOh5OhOmmt_aZXRs,609
322
322
  siliconcompiler/toolscripts/rhel8/install-montage.sh,sha256=pbN01ZSgiueaTfmzGusGO2-fkkZvZrfkXJ677TRRI0s,51
323
323
  siliconcompiler/toolscripts/rhel8/install-netgen.sh,sha256=--stLV3oJXJQhCyhTMZ5xFpXgmUf7lyHyPdvVzfZLWo,507
324
- siliconcompiler/toolscripts/rhel8/install-openroad.sh,sha256=pbhQLUq29Z-mW6Xht9HqvRk2LNcoEMKH_yrWbJIHMj0,641
325
324
  siliconcompiler/toolscripts/rhel8/install-slang.sh,sha256=ACEaxECARXBlLuvflv9DnToi8ShQuycBNwaDyCVB5V8,698
326
325
  siliconcompiler/toolscripts/rhel8/install-surelog.sh,sha256=5Z6yEJWnSjj-2hHUJzFyokmIm04UOKKAAND_U6779qA,955
327
326
  siliconcompiler/toolscripts/rhel8/install-sv2v.sh,sha256=WtLXu7Z2bMFsmjP_G6Dox4VXXx1u96uTBpnJJMXU8lo,549
@@ -410,12 +409,12 @@ siliconcompiler/toolscripts/ubuntu24/install-vpr.sh,sha256=W-zXV8t0BoiXWMDOPaUlt
410
409
  siliconcompiler/toolscripts/ubuntu24/install-xdm.sh,sha256=6xhhCtqqVeFaiSuIzLYMLhPBY685XMejEmcXuU_bXwg,701
411
410
  siliconcompiler/toolscripts/ubuntu24/install-xyce.sh,sha256=33Iq99sLdiVWFl4zpD2hxbK1Cq5qYiXYukbr5p9Yw4k,1805
412
411
  siliconcompiler/toolscripts/ubuntu24/install-yosys.sh,sha256=zpyt0MVI7tY8kGY2GIIZvWlXOXm0T7N9IMIZ18Oe26E,713
413
- siliconcompiler/utils/__init__.py,sha256=fdTd5f6W-45YiVY4lU2lyVWE4Y97-uRUfEXY8SpAFgU,13887
412
+ siliconcompiler/utils/__init__.py,sha256=6u8A5atgPW7cbC1xrerU67rlOM0FitCgxFIu5F_n5zo,14126
414
413
  siliconcompiler/utils/asic.py,sha256=cMLs7dneSmh5BlHS0-bZ1tLUpvghTw__gNaUCMpyBds,4986
415
- siliconcompiler/utils/showtools.py,sha256=QPlS42bkJM3EPKDcoxA0oATSFJM2TFpz-ZVCBV_7Ts4,1306
416
- siliconcompiler-0.28.7.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
417
- siliconcompiler-0.28.7.dist-info/METADATA,sha256=1w3SlTr_7Lwc6Mu0j0DkPXC-7zkI-aA9b6-CR48UdRo,10823
418
- siliconcompiler-0.28.7.dist-info/WHEEL,sha256=a7TGlA-5DaHMRrarXjVbQagU3Man_dCnGIWMJr5kRWo,91
419
- siliconcompiler-0.28.7.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
420
- siliconcompiler-0.28.7.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
421
- siliconcompiler-0.28.7.dist-info/RECORD,,
414
+ siliconcompiler/utils/showtools.py,sha256=qc5HLqCQxUITdhp9rESf0w_blAkKVYL6JpkXQdrew00,1406
415
+ siliconcompiler-0.28.9.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
416
+ siliconcompiler-0.28.9.dist-info/METADATA,sha256=cIK1Z_MCUEI3Zz4VBwApsmfv94-s7Y23x6jvoZ-zKUY,10831
417
+ siliconcompiler-0.28.9.dist-info/WHEEL,sha256=PZUExdf71Ui_so67QXpySuHtCi3-J3wvF4ORK6k_S8U,91
418
+ siliconcompiler-0.28.9.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
419
+ siliconcompiler-0.28.9.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
420
+ siliconcompiler-0.28.9.dist-info/RECORD,,
@@ -1,5 +1,5 @@
1
1
  Wheel-Version: 1.0
2
- Generator: setuptools (75.4.0)
2
+ Generator: setuptools (75.6.0)
3
3
  Root-Is-Purelib: true
4
4
  Tag: py3-none-any
5
5
 
@@ -1,31 +0,0 @@
1
- #!/bin/sh
2
-
3
- set -e
4
-
5
- src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
6
-
7
- mkdir -p deps
8
- cd deps
9
-
10
- git clone $(python3 ${src_path}/_tools.py --tool openroad --field git-url) openroad
11
- cd openroad
12
- git checkout $(python3 ${src_path}/_tools.py --tool openroad --field git-commit)
13
- git submodule update --init --recursive
14
-
15
- deps_args=""
16
- if [ ! -z ${PREFIX} ]; then
17
- deps_args="-prefix=$PREFIX"
18
- fi
19
- sudo ./etc/DependencyInstaller.sh $deps_args
20
-
21
- cmake_args="-DENABLE_TESTS=OFF"
22
- if [ ! -z ${PREFIX} ]; then
23
- cmake_args="$cmake_args -DCMAKE_INSTALL_PREFIX=$PREFIX"
24
- fi
25
-
26
- ./etc/Build.sh -cmake="$cmake_args"
27
-
28
- cd build
29
- sudo make install
30
-
31
- cd -