siliconcompiler 0.28.6__py3-none-any.whl → 0.28.8__py3-none-any.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.28.6'
+version = '0.28.8'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/report/dashboard/components/graph.py

@@ -133,7 +133,7 @@ def graph(metrics, nodes, node_to_step_index_map, graph_number):
 
     data, metric_unit = report.get_chart_data(_get_report_chips(), metric, nodes_as_step_and_index)
     if metric_unit:
-        y_axis_label = f'{metric}({metric_unit})'
+        y_axis_label = f'{metric} ({metric_unit})'
 
     # Prepare plot data
     filtered_data = {
@@ -142,7 +142,12 @@ def graph(metrics, nodes, node_to_step_index_map, graph_number):
         color_label: []
     }
 
-    if not nodes.empty:
+    labels = {
+        "runs": state.get_key(state.GRAPH_JOBS),
+        "nodes": [f'{step}{index}' for step, index in data]
+    }
+
+    if nodes:
         # filtering through data
         for job_name in state.get_key(state.GRAPH_JOBS):
             for step, index in data:
@@ -154,7 +159,7 @@ def graph(metrics, nodes, node_to_step_index_map, graph_number):
                     filtered_data[y_axis_label].append(data[(step, index)][job_name])
 
     # Setup chart
-    x_axis = altair.X(x_axis_label, axis=altair.Axis(labelAngle=-75))
+    x_axis = altair.X(x_axis_label, axis=altair.Axis(labelAngle=-75), sort=labels[x_axis_label])
 
     y_axis = y_axis_label
     if log_scale and chart_type != 'bar':
@@ -183,9 +188,9 @@ def graph(metrics, nodes, node_to_step_index_map, graph_number):
     streamlit.altair_chart(chart, use_container_width=True, theme='streamlit')
 
 
-def viewer(metric_dataframe, node_to_step_index_map, metric_to_metric_unit_map):
-    metrics = metric_dataframe.index.map(lambda x: metric_to_metric_unit_map[x])
-    nodes = metric_dataframe.columns
+def viewer(node_to_step_index_map):
+    nodes, metrics = report.get_chart_selection_options(_get_report_chips())
+    metrics = sorted(metrics)
 
     job_selector_col, graph_adder_col = streamlit.columns(2, gap='large')
     with job_selector_col:

siliconcompiler/report/dashboard/layouts/vertical_flowgraph.py

@@ -91,6 +91,6 @@ def layout():
 
     if "Graphs" in tabs:
         with tabs["Graphs"]:
-            graph.viewer(metric_dataframe, node_to_step_index_map, metric_to_metric_unit_map)
+            graph.viewer(node_to_step_index_map)
 
     _common.check_rerun()

siliconcompiler/report/dashboard/layouts/vertical_flowgraph_node_tab.py

@@ -112,6 +112,6 @@ def layout():
         components.file_viewer(chip, f'{chip.getworkdir()}/{chip.design}.png')
 
     if tab_selected == "Graphs":
-        graph.viewer(metric_dataframe, node_to_step_index_map, metric_to_metric_unit_map)
+        graph.viewer(node_to_step_index_map)
 
     _common.check_rerun()

siliconcompiler/report/dashboard/layouts/vertical_flowgraph_sac_tabs.py

@@ -105,6 +105,6 @@ def layout():
         components.file_viewer(chip, f'{chip.getworkdir()}/{chip.design}.png')
 
     if tab_selected == "Graphs":
-        graph.viewer(metric_dataframe, node_to_step_index_map, metric_to_metric_unit_map)
+        graph.viewer(node_to_step_index_map)
 
     _common.check_rerun()

siliconcompiler/report/report.py

@@ -335,9 +335,28 @@ def get_files(chip, step, index):
     return logs_and_reports
 
 
+def get_chart_selection_options(chips):
+    '''
+    Returns all the nodes and metrics available in the provided chips
+
+    Args:
+        chips (list) : A list of dictionaries with the form
+            {'chip_object': chip, 'chip_name': name}.
+    '''
+    nodes = set()
+    metrics = set()
+    for chip_and_chip_name in chips:
+        chip = chip_and_chip_name['chip_object']
+        nodes_list, _, _, _, chip_metrics, _ = \
+            utils._collect_data(chip, format_as_string=False)
+        nodes.update(set([f'{step}{index}' for step, index in nodes_list]))
+        metrics.update(set(chip_metrics))
+    return nodes, metrics
+
+
 def get_chart_data(chips, metric, nodes):
     '''
-    Returns returns a a tuple where the first element is a 2d dictionary of
+    Returns returns a tuple where the first element is a 2d dictionary of
     data points, following the forms {step+index: {chip_name: value}} where
     each dictionary can have many keys. The second element is a string that represents the unit.
 

siliconcompiler/tools/_common/asic.py

@@ -1,4 +1,5 @@
 from .. import _common
+import json
 
 
 def get_mainlib(chip):
@@ -169,3 +170,49 @@ def get_tool_task_var(chip,
     _, value = _common.pick_key(chip, reversed(check_keys), step=step, index=index)
 
     return value
+
+
+class CellArea:
+    def __init__(self):
+        self.__areas = {}
+
+    def addCell(self, name=None, module=None,
+                cellarea=None, cellcount=None,
+                macroarea=None, macrocount=None,
+                stdcellarea=None, stdcellcount=None):
+        if not name and not module:
+            return
+
+        if all([metric is None for metric in (
+                cellarea, cellcount,
+                macroarea, macrocount,
+                stdcellarea, stdcellcount)]):
+            return
+
+        if not name:
+            name = module
+
+        # ensure name is unique
+        check_name = name
+        idx = 0
+        while check_name in self.__areas:
+            check_name = f'{name}{idx}'
+            idx += 1
+        name = check_name
+
+        self.__areas[name] = {
+            "module": module,
+            "cellarea": cellarea,
+            "cellcount": cellcount,
+            "macroarea": macroarea,
+            "macrocount": macrocount,
+            "stdcellarea": stdcellarea,
+            "stdcellcount": stdcellcount
+        }
+
+    def size(self):
+        return len(self.__areas)
+
+    def writeReport(self, path):
+        with open(path, 'w') as f:
+            json.dump(self.__areas, f, indent=4)

siliconcompiler/tools/klayout/klayout_show.py

@@ -3,7 +3,7 @@ import os
 import sys
 
 
-def show(schema, tech, input_path, output_path, screenshot=False):
+def show(schema, tech, input_path, output_path, screenshot=False, report=None):
     # Extract info from manifest
     flow = schema.get('option', 'flow')
     step = schema.get('arg', 'step')
@@ -80,6 +80,14 @@ def show(schema, tech, input_path, output_path, screenshot=False):
             __screenshot(schema, layout_view, output_path)
         else:
             __screenshot_montage(schema, layout_view, xbins, ybins)
+    else:
+        if report:
+            rdb_id = layout_view.create_rdb(os.path.basename(report))
+            rdb = layout_view.rdb(rdb_id)
+            print(f"[INFO] reading DRC report: {report}")
+            rdb.load(report)
+
+            layout_view.show_rdb(rdb_id, cell_view.index())
 
 
 def __screenshot(schema, layout_view, output_path):
@@ -215,24 +223,56 @@ def main():
     if not design:
         design = schema.get('design')
 
-    if 'show_filepath' in schema.getkeys('tool', 'klayout', 'task', task, 'var') and \
-       schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
-                  step=step, index=index):
-        sc_filename = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
-                                 step=step, index=index)[0]
-    else:
-        sc_fileext = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filetype',
-                                step=step, index=index)[0]
-        for ext in (f'{sc_fileext}.gz', sc_fileext):
-            sc_filename = f"inputs/{design}.{ext}"
-            if os.path.exists(sc_filename):
+    sc_fileext = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filetype',
+                            step=step, index=index)[0]
+    sc_report = None
+    if sc_fileext in ('lyrdb', 'ascii'):
+        sc_report = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
+                               step=step, index=index)[0]
+
+        sc_filename = None
+        for fileext in ('gds', 'oas'):
+            for ext in (f'{fileext}.gz', fileext):
+                sc_filename = f"inputs/{design}.{ext}"
+                if os.path.exists(sc_filename):
+                    break
+                sc_filename = None
+            if sc_filename:
                 break
 
+        if not sc_filename:
+            show_step = schema.get('arg', 'step')
+            if schema.valid('tool', 'klayout', 'task', task, 'var', 'show_step'):
+                show_index = schema.get('tool', 'klayout', 'task', task, 'var', 'show_step',
+                                        step=step, index=index)[0]
+            show_index = schema.get('arg', 'index')
+            if schema.valid('tool', 'klayout', 'task', task, 'var', 'show_index'):
+                show_index = schema.get('tool', 'klayout', 'task', task, 'var', 'show_index',
+                                        step=step, index=index)[0]
+            for fileext in ('gds', 'oas'):
+                if schema.valid('input', 'layout', fileext) and \
+                   schema.get('input', 'layout', fileext, step=show_step, index=show_index):
+                    sc_filename = schema.get('input', 'layout', fileext,
+                                             step=show_step, index=show_index)[0]
+                    if sc_filename:
+                        break
+    else:
+        if 'show_filepath' in schema.getkeys('tool', 'klayout', 'task', task, 'var') and \
+           schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
+                      step=step, index=index):
+            sc_filename = schema.get('tool', 'klayout', 'task', task, 'var', 'show_filepath',
+                                     step=step, index=index)[0]
+        else:
+            for ext in (f'{sc_fileext}.gz', sc_fileext):
+                sc_filename = f"inputs/{design}.{ext}"
+                if os.path.exists(sc_filename):
+                    break
+
     sc_exit = schema.get('tool', 'klayout', 'task', task, 'var', 'show_exit',
                          step=step, index=index) == ["true"]
 
     show(schema, technology(design, schema), sc_filename, f'outputs/{design}.png',
-         screenshot=(task == 'screenshot'))
+         screenshot=(task == 'screenshot'), report=sc_report)
 
     if sc_exit:
         pya.Application.instance().exit(0)

siliconcompiler/tools/openroad/openroad.py

@@ -17,7 +17,8 @@ from siliconcompiler import sc_open
 from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, add_common_file, \
     get_tool_task, record_metric
-from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var, get_libraries
+from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var, get_libraries, \
+    CellArea
 from siliconcompiler.targets import asap7_demo
 
 
@@ -268,8 +269,12 @@ def post_process(chip):
                      "timing/hold.rpt",
                      "timing/hold.topN.rpt"],
         "holdpaths": ["timing/hold.topN.rpt"],
-        "unconstrained": ["timing/unconstrained.topN.rpt"],
-        "peakpower": [f"power/{corner}.rpt" for corner in chip.getkeys('constraint', 'timing')],
+        "unconstrained": ["timing/unconstrained.rpt", "timing/unconstrained.topN.rpt"],
+        "peakpower": [
+            *[f"power/{corner}.rpt" for corner in chip.getkeys('constraint', 'timing')],
+            *[f"images/heatmap/power_density/{corner}.png"
+              for corner in chip.getkeys('constraint', 'timing')]
+        ],
         "drvs": ["timing/drv_violators.rpt",
                  "floating_nets.rpt",
                  f"{chip.design}_antenna.rpt",
@@ -277,7 +282,9 @@ def post_process(chip):
         "drcs": [f"{chip.design}_drc.rpt",
                  f"markers/{chip.design}.drc.rpt",
                  f"markers/{chip.design}.drc.json",
-                 f"images/markers/{chip.design}.drc.png"]
+                 f"images/markers/{chip.design}.drc.png"],
+        "utilization": ["images/heatmap/placement_density.png"],
+        "wirelength": [f"images/{chip.design}.routing.png"]
     }
     metric_reports["leakagepower"] = metric_reports["peakpower"]
 
@@ -300,6 +307,8 @@ def post_process(chip):
             chip.logger.error(f'Unable to parse metrics from OpenROAD: {e}')
             metrics = {}
 
+        _generate_cell_area_report(chip.top(), metrics)
+
         or_units = {}
         for unit, or_unit in [('time', 'run__flow__platform__time_units'),
                               ('capacitance', 'run__flow__platform__capacitance_units'),
@@ -424,6 +433,114 @@ def post_process(chip):
             record_metric(chip, step, index, 'drcs', drcs, get_metric_sources('drcs'))
 
 
+def _generate_cell_area_report(design, ord_metrics):
+    cellarea_report = CellArea()
+
+    prefix = "sc__cellarea__design__instance"
+
+    filtered_data = {}
+    for key, value in ord_metrics.items():
+        if key.startswith(prefix):
+            filtered_data[key[len(prefix)+2:]] = value
+
+    modules = set()
+    modules.add("")
+    for key in filtered_data.keys():
+        if "__in_module:" in key:
+            module = key[key.find("__in_module:"):]
+            modules.add(module)
+
+    def process_cell(group):
+        data = {}
+        for key, value in filtered_data.items():
+            if (group != "" and key.endswith(group)):
+                key = key[:key.find("__in_module:")]
+                data[key] = value
+            elif (group == "" and "__in_module" not in key):
+                data[key] = value
+
+        cell_type = None
+        cell_name = None
+
+        if not group:
+            cell_type = design
+            cell_name = design
+        else:
+            cell_type = group[len("__in_module:"):]
+
+        cellarea = None
+        cellcount = None
+
+        macroarea = None
+        macrocount = None
+
+        stdcell_types = (
+            'tie_cell',
+            'standard_cell',
+            'buffer',
+            'clock_buffer',
+            'timing_repair_buffer',
+            'inverter',
+            'clock_inverter',
+            'timing_Repair_inverter',
+            'clock_gate_cell',
+            'level_shifter_cell',
+            'sequential_cell',
+            'multi_input_combinational_cell',
+            'other'
+            )
+
+        stdcell_info_area = []
+        stdcell_info_count = []
+        stdcellarea = None
+        stdcellcount = None
+
+        for key, value in data.items():
+            if key == 'name':
+                cell_name = value
+            elif key == 'count':
+                cellcount = value
+            elif key == 'area':
+                cellarea = value
+            elif key.startswith('count__class'):
+                _, cell_class = key.split(':')
+                if cell_class == 'macro':
+                    macrocount = value
+                elif cell_class in stdcell_types:
+                    stdcell_info_count.append(value)
+            elif key.startswith('area__class'):
+                _, cell_class = key.split(':')
+                if cell_class == 'macro':
+                    macroarea = value
+                elif cell_class in stdcell_types:
+                    stdcell_info_area.append(value)
+
+        if stdcell_info_count:
+            stdcellcount = sum(stdcell_info_count)
+        if stdcell_info_area:
+            stdcellarea = sum(stdcell_info_area)
+
+        cellarea_report.addCell(
+            name=cell_name,
+            module=cell_type,
+            cellarea=cellarea,
+            cellcount=cellcount,
+            macroarea=macroarea,
+            macrocount=macrocount,
+            stdcellarea=stdcellarea,
+            stdcellcount=stdcellcount)
+
+        if filtered_data:
+            return True
+        return False
+
+    for module in modules:
+        process_cell(module)
+
+    if cellarea_report.size() > 0:
+        cellarea_report.writeReport("reports/hierarchical_cell_area.json")
+
+
 ######
 def get_library_timing_keypaths(chip, lib):
     step = chip.get('arg', 'step')

siliconcompiler/tools/openroad/scripts/sc_procs.tcl

@@ -483,3 +483,12 @@ proc sc_convert_rotation { rot } {
     default { utl::error FLW 1 "$rot not recognized" }
   }
 }
+
+proc sc_check_version { min_required } {
+  set version [split [ord::openroad_version] "-"]
+  if { [lindex $version 0] != "v2.0" } {
+    return false
+  }
+
+  return [expr { [lindex $version 1] >= $min_required }]
+}

siliconcompiler/tools/openroad/scripts/sc_report.tcl

@@ -168,3 +168,22 @@ foreach markerdb [[ord::get_db_block] getMarkerCategories] {
   $markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
   $markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
 }
+
+if { [sc_check_version 17038] } {
+  utl::push_metrics_stage "sc__cellarea__{}"
+  tee -file reports/cell_usage.rpt {report_cell_usage -verbose}
+
+  foreach modinst [[ord::get_db_block] getModInsts] {
+    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
+    tee -quiet -append -file reports/cell_usage.rpt {
+      puts "########################################################"
+    }
+    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
+
+    utl::metric "design__instance__name__in_module:[[$modinst getMaster] getName]" \
+      [$modinst getHierarchicalName]
+    tee -quiet -append -file reports/cell_usage.rpt \
+      "report_cell_usage -verbose [$modinst getHierarchicalName]"
+  }
+  utl::pop_metrics_stage
+}

siliconcompiler/tools/vpr/vpr.py

@@ -128,6 +128,12 @@ def runtime_options(chip):
     # If we allow VPR to sweep dangling primary I/Os and logic blocks
     # it can interfere with circuit debugging; so disable that
     options.append('--sweep_dangling_primary_ios off')
+    # If you don't sweep dangling primary I/Os, but sweeping nets
+    # VPR can crash:
+    options.append('--sweep_dangling_nets off')
+    # If you don't sweep dangling nets then the timing engine requires
+    # you to set an option allowing dangling nodes
+    options.append('--allow_dangling_combinational_nodes on')
     options.append('--sweep_constant_primary_outputs off')
     options.append('--sweep_dangling_blocks off')
 

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -231,6 +231,8 @@ sc_map_memory $sc_memory_libmap_files $sc_memory_techmap_files 0
 
 # Perform hierarchy flattening
 if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "true" } {
+    yosys log -push
+    yosys log -header "SC Auto flattening"
     set sc_hier_iterations \
         [lindex [sc_cfg_tool_task_get var hier_iterations] 0]
     set sc_hier_threshold \
@@ -240,6 +242,7 @@ if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "
             break
         }
     }
+    yosys log -pop
 }
 
 # Finish synthesis

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "dcba5786c8e714e3b7682a98d73de40e875699b1",
+    "git-commit": "c3e802e73aa2ca2974874e487ae481fc4f2cb8c3",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",

siliconcompiler/utils/__init__.py

@@ -84,7 +84,7 @@ def get_default_iomap():
     # Record extensions:
 
     # High level languages
-    hll_c = ('c', 'cc', 'cpp', 'c++', 'cp', 'cxx', 'hpp')
+    hll_c = ('c', 'cc', 'cpp', 'c++', 'cp', 'cxx', 'hpp', 'h')
     hll_bsv = ('bsv',)
     hll_scala = ('scala',)
     hll_python = ('py',)
@@ -92,8 +92,8 @@ def get_default_iomap():
     config_chisel = ('sbt',)
 
     # Register transfer languages
-    rtl_verilog = ('v', 'verilog')
-    rtl_systemverilog = ('sv',)
+    rtl_verilog = ('v', 'verilog', 'vh')
+    rtl_systemverilog = ('sv', 'svh')
     rtl_vhdl = ('vhd', 'vhdl')
 
     # Timing libraries
@@ -116,8 +116,8 @@ def get_default_iomap():
     waveform_vcd = ('vcd',)
 
     # Constraint
-    constraint_sdc = ('sdc', )
-    constraint_upf = ('upf', )
+    constraint_sdc = ('sdc',)
+    constraint_upf = ('upf',)
 
     # FPGA constraints
     fpga_xdc = ('xdc',)
@@ -125,6 +125,10 @@ def get_default_iomap():
     fpga_vpr_place = ('place',)
     fpga_vpr_route = ('route',)
 
+    # Reports
+    report_drc = ('lyrdb', 'ascii')
+    report_log = ('log',)
+
     # Build default map with fileset and type
     default_iomap = {}
     default_iomap.update({ext: ('hll', 'c') for ext in hll_c})
@@ -160,6 +164,9 @@ def get_default_iomap():
     default_iomap.update({ext: ('fpga', 'vpr_place') for ext in fpga_vpr_place})
     default_iomap.update({ext: ('fpga', 'vpr_route') for ext in fpga_vpr_route})
 
+    default_iomap.update({ext: ('report', 'drc') for ext in report_drc})
+    default_iomap.update({ext: ('report', 'log') for ext in report_log})
+
     return default_iomap
 
 

siliconcompiler/utils/showtools.py

@@ -14,6 +14,8 @@ def setup(chip):
     chip.register_showtool('oas', klayout_screenshot)
     chip.register_showtool('lef', klayout_show)
     chip.register_showtool('lef', klayout_screenshot)
+    chip.register_showtool('lyrdb', klayout_show)
+    chip.register_showtool('ascii', klayout_show)
 
     chip.register_showtool('odb', openroad_show)
     chip.register_showtool('odb', openroad_screenshot)

{siliconcompiler-0.28.6.dist-info → siliconcompiler-0.28.8.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.6
+Version: 0.28.8
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -25,7 +25,6 @@ Classifier: Topic :: Software Development :: Build Tools
 Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: aiohttp ==3.10.10
 Requires-Dist: requests ==2.32.3
 Requires-Dist: PyYAML ==6.0.2
 Requires-Dist: pandas >=1.1.5
@@ -43,13 +42,15 @@ Requires-Dist: fastjsonschema ==2.20.0
 Requires-Dist: docker ==7.1.0
 Requires-Dist: sc-surelog ==1.84.1
 Requires-Dist: orjson ==3.10.11
-Requires-Dist: streamlit ==1.40.0 ; python_version != "3.9.7"
-Requires-Dist: streamlit-agraph ==0.0.45 ; python_version != "3.9.7"
-Requires-Dist: streamlit-antd-components ==0.3.2 ; python_version != "3.9.7"
-Requires-Dist: streamlit-javascript ==0.1.5 ; python_version != "3.9.7"
-Requires-Dist: streamlit-autorefresh ==1.0.1 ; python_version != "3.9.7"
+Requires-Dist: streamlit ==1.40.1 ; python_full_version != "3.9.7"
+Requires-Dist: streamlit-agraph ==0.0.45 ; python_full_version != "3.9.7"
+Requires-Dist: streamlit-antd-components ==0.3.2 ; python_full_version != "3.9.7"
+Requires-Dist: streamlit-javascript ==0.1.5 ; python_full_version != "3.9.7"
+Requires-Dist: streamlit-autorefresh ==1.0.1 ; python_full_version != "3.9.7"
 Requires-Dist: importlib-metadata ; python_version < "3.10"
+Requires-Dist: aiohttp ==3.10.11 ; python_version <= "3.8"
 Requires-Dist: Pillow ==10.4.0 ; python_version <= "3.8"
+Requires-Dist: aiohttp ==3.11.2 ; python_version >= "3.9"
 Requires-Dist: Pillow ==11.0.0 ; python_version >= "3.9"
 Provides-Extra: docs
 Requires-Dist: Sphinx ==8.1.3 ; extra == 'docs'

{siliconcompiler-0.28.6.dist-info → siliconcompiler-0.28.8.dist-info}/RECORD

@@ -1,7 +1,7 @@
 siliconcompiler/__init__.py,sha256=Ke_Bcryj9N6MoUq_5z_IDW3qMrUzR-3-kJVsvUenYzY,511
 siliconcompiler/__main__.py,sha256=JwWkcvaNngqgMWprEQ1cFy2Wdq9GMvk46UGTHyh_qvM,170
 siliconcompiler/_common.py,sha256=c6r0SbI2xTpNOZayFsyCDo0riJGNJSPN-0zW8R7rDBI,1488
-siliconcompiler/_metadata.py,sha256=5pJMzZkLbYvufGtouHKsIxsoZIMBfPT7UXrw4Df388U,1264
+siliconcompiler/_metadata.py,sha256=CumyMn5odWcWqlPwYTx9IioZ5rx0a68RKL7IvU2SO-A,1264
 siliconcompiler/core.py,sha256=_T1eEY7lUsrbaEBUaG1WSAzY2JFxyz5tXEKxvoCGZaI,135718
 siliconcompiler/flowgraph.py,sha256=WLcbBWFj5DdYRRIxNy_Djm2v4yN9WELQM_ypNPB5QVM,21963
 siliconcompiler/issue.py,sha256=9ZpdEBh8QB56-bZ1YXRnjqgg9hwnFty2u1o5oI66W7M,11125
@@ -80,7 +80,7 @@ siliconcompiler/remote/server_schema/responses/get_results.json,sha256=h4XraLW4h
 siliconcompiler/remote/server_schema/responses/remote_run.json,sha256=FWW_0m46qwIJHiTriISzChKHJF6G9RIwP0rmp1OjIuA,475
 siliconcompiler/report/__init__.py,sha256=ADa-8Jwy4fl2Wtg0ejy4Tvil805uwA4WWTdK125JKcs,388
 siliconcompiler/report/html_report.py,sha256=Wh5X7iQpfIEHcs-WrVE9dtDf-gkz3GhT_yf8kVG0O3o,2597
-siliconcompiler/report/report.py,sha256=Bw09BzVAm1gDBPf2jR3FrEF0434B6bSIa-E3IWbywvI,14294
+siliconcompiler/report/report.py,sha256=OPJhuKAnUzP-dm-6CG6Fy45Gm_rbMapey2WKuJiouYI,14924
 siliconcompiler/report/summary_image.py,sha256=tKuoLiG6Whvnc8LHeSzU4FookpBkYYCMWUGb-ux2i8k,3570
 siliconcompiler/report/summary_table.py,sha256=Y5ByOCJQtNOXIz5n9VU_CBHOTdSE0g8ClmfflWkQcXU,3386
 siliconcompiler/report/utils.py,sha256=70klZsAKwhW55kOxBBdV9zzOU-NorMk6y6riMyKXo7c,6423
@@ -89,12 +89,12 @@ siliconcompiler/report/dashboard/state.py,sha256=qBAmLpKb0xXqf2vRbBBgYs8P71v3MGI
 siliconcompiler/report/dashboard/viewer.py,sha256=scF4MkbOdqM1pRCzGWnXeMrk4r2M4Y2cDyEIrAWCFiw,1095
 siliconcompiler/report/dashboard/components/__init__.py,sha256=BkVt0JakAj9kC5WlewdvFESwygjDmhyj85xiV8oc00I,18097
 siliconcompiler/report/dashboard/components/flowgraph.py,sha256=bjPuaWlEra4HbIUIbtCkYQMNTYueSGP0WO-r16MrBss,3525
-siliconcompiler/report/dashboard/components/graph.py,sha256=ueuuDxV6KOtK_akxLFqkbB_MTmiF7JwXaLGE1ZN12Ow,6683
+siliconcompiler/report/dashboard/components/graph.py,sha256=m9y4lxKDgTJNp_eOdLohN1bn6uE3XEnE387xnb4HnUo,6776
 siliconcompiler/report/dashboard/layouts/__init__.py,sha256=aYhWEoQg4CiwGMCcLH4Yj__d_5tD4vyb164dP2RpURY,638
 siliconcompiler/report/dashboard/layouts/_common.py,sha256=_Iz5IxftnNKYvhQNA-PWpyv8R1uejvrVUMGmUIEvPf0,1276
-siliconcompiler/report/dashboard/layouts/vertical_flowgraph.py,sha256=nudDr8x6IKa8zrVugtvfj166MEC84eLXwxHCagX6DMc,3470
-siliconcompiler/report/dashboard/layouts/vertical_flowgraph_node_tab.py,sha256=ORyj7xu7r6sI15IgSS8Epql7yI93n-9dzGQzxCGxbj8,4274
-siliconcompiler/report/dashboard/layouts/vertical_flowgraph_sac_tabs.py,sha256=zEFjSby2fyHGt-mxHV-OceHNuTEyYMSyMF3KVRclyFI,4131
+siliconcompiler/report/dashboard/layouts/vertical_flowgraph.py,sha256=ml8qPg2-g3n-HW9E4znwkaYBISyloUjD19_Ooy3iCn0,3425
+siliconcompiler/report/dashboard/layouts/vertical_flowgraph_node_tab.py,sha256=09n3LqXedQOX8UizlTn9BHyepizmbwz9SIN0QB2PNkA,4229
+siliconcompiler/report/dashboard/layouts/vertical_flowgraph_sac_tabs.py,sha256=g6lrnXJVEkTh7OQY1xCgl_q0So0XewItuY0sjnjaBCA,4086
 siliconcompiler/report/dashboard/utils/__init__.py,sha256=mkcBAlfPovfgoRv9nPbtgQSeFglwlxlSIXsEQmdsDz8,2540
 siliconcompiler/report/dashboard/utils/file_utils.py,sha256=5MKAyf7TGXQIc3yxwbP1H6xi0NGwUfzu2j3LOv1Yei0,3333
 siliconcompiler/scheduler/__init__.py,sha256=bkJ5S06BNXsdfjx5nPcgak_9FT8XHxgsnLIYvee5uvk,84997
@@ -139,7 +139,7 @@ siliconcompiler/templates/tcl/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5N
 siliconcompiler/templates/tcl/manifest.tcl.j2,sha256=XT2pKuPSaa2GPJj1IpEl3Al5N70yqQS8jZecmpyeV4o,3547
 siliconcompiler/tools/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/_common/__init__.py,sha256=wQ0FQcg6bBRmpiUquHVaBpLabyMjSA0ecmxkohv5LlE,14483
-siliconcompiler/tools/_common/asic.py,sha256=gmFMY5EWm9c8zC43E-lmjMmCQsrdd852cVoHg_PVpmo,5227
+siliconcompiler/tools/_common/asic.py,sha256=0-yMpvuMBy2dzN6uRFC96z8mN-7Ndzj7LhiMuR2MKtk,6469
 siliconcompiler/tools/_common/sdc/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/_common/sdc/sc_constraints.sdc,sha256=Hz6OLebi14UTcfGXgJoNJeFo0BH_4N5XwjFe2mrey8g,2827
 siliconcompiler/tools/_common/tcl/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
@@ -188,7 +188,7 @@ siliconcompiler/tools/klayout/klayout.py,sha256=w0iqtdr_tjwH31hgdpCuCZlRByev3c7r
 siliconcompiler/tools/klayout/klayout_convert_drc_db.py,sha256=WVLI_HJ2yY1_OFDzG40n0B4ULZE6bPqB-l9a8nmoO9E,5608
 siliconcompiler/tools/klayout/klayout_export.py,sha256=RHGatKDzeBSY6n9oA7PNaLe4HG75kGV4ztAhjNXio0I,8026
 siliconcompiler/tools/klayout/klayout_operations.py,sha256=okHyVcFVkwHge4hsyOVQBrxILesVtVicT70mGQM51Yk,13054
-siliconcompiler/tools/klayout/klayout_show.py,sha256=jZk_p9D3wZ_VjSmiRh71SQ6AduOkFEMVErKvGzWF1P8,9127
+siliconcompiler/tools/klayout/klayout_show.py,sha256=G0buKR41h41VCxlkhFhWdeHiuMJHmnrVFxT8AaGzuA8,11069
 siliconcompiler/tools/klayout/klayout_utils.py,sha256=62AZwICFrlDzswKbw0H-vcVpoQPaRVjv_wbmclFvlm0,6575
 siliconcompiler/tools/klayout/operations.py,sha256=_dqcizzyo3MvNBqyLYH9zrPN9vzfJaxCGld7VK6anTc,7850
 siliconcompiler/tools/klayout/screenshot.py,sha256=ft6mFUdUtgMpEc3sULrO3LNbjReHBeGyaJdbEdW9j1k,3890
@@ -217,7 +217,7 @@ siliconcompiler/tools/openroad/dfm.py,sha256=RjdOqq7oPVSx5HzYUTSlBh4ZGnVfJqJHR0c
 siliconcompiler/tools/openroad/export.py,sha256=svZZlcUIq9FTDydpoDZdlPyoMVYIkLBUTIBD2dm8TOk,5273
 siliconcompiler/tools/openroad/floorplan.py,sha256=y7V2WOhHW0MhMJkjx4hQuTsiIKCMpcJiQEu4RaMlq_k,2804
 siliconcompiler/tools/openroad/metrics.py,sha256=SyGF-foyfJz2VZRxEdA_HCKI9wW3s8jzdBkph1WMG3E,1048
-siliconcompiler/tools/openroad/openroad.py,sha256=Xbs2FcTy1ooMhi6NIksidlGi4a8EAnmtUk6Gm8Ez98c,46911
+siliconcompiler/tools/openroad/openroad.py,sha256=Tcte1Vk5zV2LyhNi1gycj2hW8IQ9C86GBtUG2_vP_J8,50463
 siliconcompiler/tools/openroad/physyn.py,sha256=ZgEPRTGyXe930PsXNHx1p7ITsBa6x7_EyZfW8vM0-O8,682
 siliconcompiler/tools/openroad/place.py,sha256=0eRg3n0x3zawg8jp7akDpc1KbUw4LKqeGJ2MMliXbnU,1018
 siliconcompiler/tools/openroad/rcx_bench.py,sha256=EEOsuQhB2z09dbKqQ8CVgFQyymTceKG1fgFWUbEbcxQ,3658
@@ -235,12 +235,12 @@ siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl,sha256=XufELL8Ys4kUrSSQw
 siliconcompiler/tools/openroad/scripts/sc_metrics.tcl,sha256=AbpHGcgLb-kRsJGnwFEktk7uzpZOCcBY74-YBdrKVGs,1
 siliconcompiler/tools/openroad/scripts/sc_physyn.tcl,sha256=hLAVeE_a__ZBgVMOSmMwCwtTDfflZptPmphaqibYvEk,115
 siliconcompiler/tools/openroad/scripts/sc_place.tcl,sha256=WMuYB-LXQP8YdcYMHTkqGzOvn1bK6X7mOm12gEK4kKY,1937
-siliconcompiler/tools/openroad/scripts/sc_procs.tcl,sha256=1OtBZJiy9zZgCzD6uDqCtFJrSu1n8kO0EoeVVXx0Ctc,12426
+siliconcompiler/tools/openroad/scripts/sc_procs.tcl,sha256=ZjLhdb0ddjFMn_ATbVRhGRrgUC1bi4aCfHNjbDosHIQ,12640
 siliconcompiler/tools/openroad/scripts/sc_rcx.tcl,sha256=-70AuNikbsoHd_bW-myc8QMbmJNFSK-DqKIN_HF0luc,1514
 siliconcompiler/tools/openroad/scripts/sc_rcx_bench.tcl,sha256=d_VgTJA4hwRiaJVTTBOl1LxfJ3KB7fHJjmj8eTm1GRs,682
 siliconcompiler/tools/openroad/scripts/sc_rcx_extract.tcl,sha256=Aj9J_8aiOR1WqcQvdx99WyUDcN8RafxXwtrexcS5UcU,489
 siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl,sha256=HFGXVIb8f3FPHl0qR25_I3xhx49jfIMI8WSIw0sYbSw,4844
-siliconcompiler/tools/openroad/scripts/sc_report.tcl,sha256=mVZaVB3bEp6DQkdzP3m-uzqAIIbslnA5lCmmkJmHZfw,5477
+siliconcompiler/tools/openroad/scripts/sc_report.tcl,sha256=lrMQ5j41xIXA5a6Q_6EejAT2P0dj3gMBwwGNjKdSN2I,6208
 siliconcompiler/tools/openroad/scripts/sc_route.tcl,sha256=m1TanwYlYcPbisO92gCih4jnxyaQ5BVDB71PtOCipqI,3919
 siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl,sha256=nMbqIIcnUQ5kmdYXjeu-P2k3SOSWS1ORrUEMyGavGU0,437
 siliconcompiler/tools/openroad/scripts/sc_write.tcl,sha256=5N7ZKWU_8NdEYO-n6tuTXCmWCYtClDjHykOidKyFWdk,168
@@ -289,7 +289,7 @@ siliconcompiler/tools/vpr/place.py,sha256=CwzEmQELZ5IUnQ6lg964icDhmcBOxcNI32Ysdg
 siliconcompiler/tools/vpr/route.py,sha256=uD4A2fSahluRhSJayjW1rfXt9pI3wWAbLIRU_YuXwlA,4876
 siliconcompiler/tools/vpr/screenshot.py,sha256=5Ji6J9p0R0C7C9WkuCwLu2InGQpeCo_Ciif7wUXz9ng,1818
 siliconcompiler/tools/vpr/show.py,sha256=Dm0efQaOa2G6FsDeo6BpNYEp0farqKQOXeF_JLBuSYo,3120
-siliconcompiler/tools/vpr/vpr.py,sha256=MjHf4J5s1Hz05SG_dOxrnQAR9hTv980339xH67hI5B4,14091
+siliconcompiler/tools/vpr/vpr.py,sha256=Ydzh25XqK70tH-IAdF2ZMBfYsCqpG7I9KSAaJEtuF4s,14410
 siliconcompiler/tools/xdm/__init__.py,sha256=uEo7uTPRdoARmk0E5U8yQ_MZOntO-cWJfGb6_pPA0ZQ,729
 siliconcompiler/tools/xdm/convert.py,sha256=rlirszWfNs2x9KApd3AiKpx78B3bfQ5VVWv5Nk_LSuU,2371
 siliconcompiler/tools/xyce/__init__.py,sha256=YTSk-XGtviqthGmGHb6RCDEAIMUQ7ElYZjZzpa1aSBg,1297
@@ -303,7 +303,7 @@ siliconcompiler/tools/yosys/sc_screenshot.tcl,sha256=-7Bb-HhJsZjSdSIlYCTZnZgigwB
 siliconcompiler/tools/yosys/sc_syn.tcl,sha256=ZtLbH-x9tPdZgHwcCLWZ4qQ4zqh1imLluj2LyW86P4k,2321
 siliconcompiler/tools/yosys/screenshot.py,sha256=Octzl15bG8LmXdyU-hv9QsP9GTrhoLYzdvi_yTRzXXo,5629
 siliconcompiler/tools/yosys/syn_asic.py,sha256=jEYfQTaTIPj4UHY2AKJocW3wMW2Prtgu6t55esNpZ_E,24106
-siliconcompiler/tools/yosys/syn_asic.tcl,sha256=kws8B7e7_2Z_Bat2_3D9SnKmuNWpuuIAHy02kpGwe5Y,11875
+siliconcompiler/tools/yosys/syn_asic.tcl,sha256=MNUmV_qdkHfgDAPDb0urVwRLE65Y5xNodGOW4Zo7nTM,11957
 siliconcompiler/tools/yosys/syn_fpga.py,sha256=rF4TMBUhmtiWwdx1KJeW-cNiAnkTXmo_0htyuUE7plY,5427
 siliconcompiler/tools/yosys/syn_fpga.tcl,sha256=03w87fLgDwD65tDiUbkTBI-rKQUkMDnHI0u42UrA6D8,8030
 siliconcompiler/tools/yosys/syn_strategies.tcl,sha256=YJ5bXCdUNDZZ4EY4wBGS-9m0EeNlANBIO9e5a_6A0KA,5329
@@ -312,7 +312,7 @@ siliconcompiler/tools/yosys/techmaps/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeu
 siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v,sha256=M4T-ygiKmlsprl5eGGLaV5w6HVqlEepn0wlUDmOkapg,773
 siliconcompiler/tools/yosys/templates/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/yosys/templates/abc.const,sha256=TAq9ThdLMYCJGrtToEU0gWcLuEtjE4Gk8huBbTm1v-I,116
-siliconcompiler/toolscripts/_tools.json,sha256=wTknmgxxAimBLm0crN_uDsJ40sbt-rUQFEMAbc37qiA,3959
+siliconcompiler/toolscripts/_tools.json,sha256=I7xm0H0ev5Xe8_mZG94ABEJ5NO4fnO5DBBmbleFHYIU,3959
 siliconcompiler/toolscripts/_tools.py,sha256=P30KY_xbbjl8eHGsPAxDcAzWvJJpiL07ZfGZZDQbdR8,7174
 siliconcompiler/toolscripts/rhel8/install-chisel.sh,sha256=lPORZN7vlBX6sJSv01JOIiDE9-_7GcCZGA7EP5ri3MQ,525
 siliconcompiler/toolscripts/rhel8/install-ghdl.sh,sha256=xCLeEUuJVI_6PVEvnTwBsTWoEHiQg0TY3x-tJXfg6Zk,459
@@ -321,7 +321,6 @@ siliconcompiler/toolscripts/rhel8/install-klayout.sh,sha256=lUCSc0Yr0NBUMVragNyJ
 siliconcompiler/toolscripts/rhel8/install-magic.sh,sha256=ugiH7ybdxQggs0ucUHiVtCOO142XOh5OhOmmt_aZXRs,609
 siliconcompiler/toolscripts/rhel8/install-montage.sh,sha256=pbN01ZSgiueaTfmzGusGO2-fkkZvZrfkXJ677TRRI0s,51
 siliconcompiler/toolscripts/rhel8/install-netgen.sh,sha256=--stLV3oJXJQhCyhTMZ5xFpXgmUf7lyHyPdvVzfZLWo,507
-siliconcompiler/toolscripts/rhel8/install-openroad.sh,sha256=pbhQLUq29Z-mW6Xht9HqvRk2LNcoEMKH_yrWbJIHMj0,641
 siliconcompiler/toolscripts/rhel8/install-slang.sh,sha256=ACEaxECARXBlLuvflv9DnToi8ShQuycBNwaDyCVB5V8,698
 siliconcompiler/toolscripts/rhel8/install-surelog.sh,sha256=5Z6yEJWnSjj-2hHUJzFyokmIm04UOKKAAND_U6779qA,955
 siliconcompiler/toolscripts/rhel8/install-sv2v.sh,sha256=WtLXu7Z2bMFsmjP_G6Dox4VXXx1u96uTBpnJJMXU8lo,549
@@ -410,12 +409,12 @@ siliconcompiler/toolscripts/ubuntu24/install-vpr.sh,sha256=W-zXV8t0BoiXWMDOPaUlt
 siliconcompiler/toolscripts/ubuntu24/install-xdm.sh,sha256=6xhhCtqqVeFaiSuIzLYMLhPBY685XMejEmcXuU_bXwg,701
 siliconcompiler/toolscripts/ubuntu24/install-xyce.sh,sha256=33Iq99sLdiVWFl4zpD2hxbK1Cq5qYiXYukbr5p9Yw4k,1805
 siliconcompiler/toolscripts/ubuntu24/install-yosys.sh,sha256=zpyt0MVI7tY8kGY2GIIZvWlXOXm0T7N9IMIZ18Oe26E,713
-siliconcompiler/utils/__init__.py,sha256=fdTd5f6W-45YiVY4lU2lyVWE4Y97-uRUfEXY8SpAFgU,13887
+siliconcompiler/utils/__init__.py,sha256=6u8A5atgPW7cbC1xrerU67rlOM0FitCgxFIu5F_n5zo,14126
 siliconcompiler/utils/asic.py,sha256=cMLs7dneSmh5BlHS0-bZ1tLUpvghTw__gNaUCMpyBds,4986
-siliconcompiler/utils/showtools.py,sha256=QPlS42bkJM3EPKDcoxA0oATSFJM2TFpz-ZVCBV_7Ts4,1306
-siliconcompiler-0.28.6.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
-siliconcompiler-0.28.6.dist-info/METADATA,sha256=Q4jplEpdLt1k-TpRSnjevgVqhFVTilZJenNEHMZUPu8,10798
-siliconcompiler-0.28.6.dist-info/WHEEL,sha256=a7TGlA-5DaHMRrarXjVbQagU3Man_dCnGIWMJr5kRWo,91
-siliconcompiler-0.28.6.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
-siliconcompiler-0.28.6.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
-siliconcompiler-0.28.6.dist-info/RECORD,,
+siliconcompiler/utils/showtools.py,sha256=qc5HLqCQxUITdhp9rESf0w_blAkKVYL6JpkXQdrew00,1406
+siliconcompiler-0.28.8.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
+siliconcompiler-0.28.8.dist-info/METADATA,sha256=gebkDkb8zph1f-QBL3MlH-uAXGcbz8b5FU6hvNiHRm4,10907
+siliconcompiler-0.28.8.dist-info/WHEEL,sha256=R06PA3UVYHThwHvxuRWMqaGcr-PuniXahwjmQRFMEkY,91
+siliconcompiler-0.28.8.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
+siliconcompiler-0.28.8.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
+siliconcompiler-0.28.8.dist-info/RECORD,,

{siliconcompiler-0.28.6.dist-info → siliconcompiler-0.28.8.dist-info}/WHEEL

@@ -1,5 +1,5 @@
 Wheel-Version: 1.0
-Generator: setuptools (75.4.0)
+Generator: setuptools (75.5.0)
 Root-Is-Purelib: true
 Tag: py3-none-any
 

siliconcompiler/toolscripts/rhel8/install-openroad.sh

@@ -1,31 +0,0 @@
-#!/bin/sh
-
-set -e
-
-src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
-
-mkdir -p deps
-cd deps
-
-git clone $(python3 ${src_path}/_tools.py --tool openroad --field git-url) openroad
-cd openroad
-git checkout $(python3 ${src_path}/_tools.py --tool openroad --field git-commit)
-git submodule update --init --recursive
-
-deps_args=""
-if [ ! -z ${PREFIX} ]; then
-    deps_args="-prefix=$PREFIX"
-fi
-sudo ./etc/DependencyInstaller.sh $deps_args
-
-cmake_args="-DENABLE_TESTS=OFF"
-if [ ! -z ${PREFIX} ]; then
-    cmake_args="$cmake_args -DCMAKE_INSTALL_PREFIX=$PREFIX"
-fi
-
-./etc/Build.sh -cmake="$cmake_args"
-
-cd build
-sudo make install
-
-cd -