siliconcompiler 0.28.5__py3-none-any.whl → 0.28.7__py3-none-any.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.28.5'
+version = '0.28.7'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/apps/utils/summarize.py

@@ -0,0 +1,47 @@
+# Copyright 2024 Silicon Compiler Authors. All Rights Reserved.
+
+# Standard Modules
+import sys
+
+import siliconcompiler
+from siliconcompiler.apps._common import UNSET_DESIGN
+from siliconcompiler import SiliconCompilerError
+
+
+###########################
+def main():
+    progname = "summarize"
+    description = """
+    ------------------------------------------------------------
+    Utility script to print job summary from a manifest
+    ------------------------------------------------------------
+    """
+    # Create a base chip class.
+    chip = siliconcompiler.Chip(UNSET_DESIGN)
+
+    # Read command-line inputs and generate Chip objects to run the flow on.
+    try:
+        chip.create_cmdline(progname,
+                            description=description,
+                            switchlist=['-cfg',
+                                        '-loglevel'])
+    except SiliconCompilerError:
+        return 1
+    except Exception as e:
+        chip.logger.error(e)
+        return 1
+
+    design = chip.get('design')
+    if design == UNSET_DESIGN:
+        chip.logger.error('Design not loaded')
+        return 1
+
+    # Print Job Summary
+    chip.summary(generate_image=False, generate_html=False)
+
+    return 0
+
+
+#########################
+if __name__ == "__main__":
+    sys.exit(main())

siliconcompiler/core.py

@@ -399,7 +399,7 @@ class Chip:
                     self.set(*key, packages, field='package', step=step, index=index)
 
             # Read in target if set
-            if "target" in extra_params:
+            if extra_params is not None and "target" in extra_params:
                 if extra_params["target"]:
                     # running target command
                     # Search order "{name}", and "siliconcompiler.targets.{name}"
@@ -416,7 +416,7 @@ class Chip:
                     self.use(modules[0])
                     extra_params["target"] = modules[0].__name__
 
-            if "use" in extra_params:
+            if extra_params is not None and "use" in extra_params:
                 if extra_params["use"]:
                     for use in extra_params["use"]:
                         mod = self._load_module(use)
@@ -437,19 +437,25 @@ class Chip:
         if "-target" in additional_args:
             raise ValueError('-target cannot be used as an additional argument')
 
-        additional_args["-target"] = {
-            "help": "target to load",
-            "metavar": "<target>"
-        }
+        if switchlist is None or '-target' in switchlist:
+            additional_args["-target"] = {
+                "help": "target to load",
+                "metavar": "<target>"
+            }
+            if switchlist:
+                switchlist.remove('-target')
 
         if "-use" in additional_args:
             raise ValueError('-use cannot be used as an additional argument')
 
-        additional_args["-use"] = {
-            "action": "append",
-            "help": "modules to load",
-            "metavar": "<module>"
-        }
+        if switchlist is None or '-use' in switchlist:
+            additional_args["-use"] = {
+                "action": "append",
+                "help": "modules to load",
+                "metavar": "<module>"
+            }
+            if switchlist:
+                switchlist.remove('-use')
 
         try:
             return self.schema.create_cmdline(

siliconcompiler/report/dashboard/__init__.py

@@ -3,9 +3,6 @@ import time
 import tempfile
 import json
 
-from streamlit.web import bootstrap
-from streamlit import config as _config
-
 import multiprocessing
 import subprocess
 import atexit
@@ -16,6 +13,13 @@ import socketserver
 
 from siliconcompiler.report.dashboard import utils
 
+try:
+    from streamlit.web import bootstrap
+    from streamlit import config as _config
+except ModuleNotFoundError:
+    bootstrap = None
+    _config = None
+
 
 class Dashboard():
     __port = 8501
@@ -26,6 +30,9 @@ class Dashboard():
         pass
 
     def __init__(self, chip, port=None, graph_chips=None):
+        if not bootstrap:
+            raise NotImplementedError('streamlit is not available')
+
         if not port:
             port = Dashboard.get_next_port()
         if not port:

siliconcompiler/tools/openroad/metrics.py

@@ -1,4 +1,3 @@
-
 from siliconcompiler.tools.openroad.openroad import setup as setup_tool
 from siliconcompiler.tools.openroad.openroad import build_pex_corners
 from siliconcompiler.tools.openroad.openroad import post_process as or_post_process

siliconcompiler/tools/openroad/scripts/sc_apr.tcl

@@ -198,30 +198,28 @@ if { [file exists "inputs/$sc_design.odb"] } {
     }
   }
 
-  if { $sc_task == "floorplan" } {
+  if { [file exists "inputs/${sc_design}.def"] } {
+    # Read DEF
+    # get from previous step
+    puts "Reading DEF: inputs/${sc_design}.def"
+    read_def "inputs/${sc_design}.def"
+  } elseif { [sc_cfg_exists input layout def] } {
+    # Read DEF
+    set sc_def [lindex [sc_cfg_get input layout def] 0]
+    puts "Reading DEF: ${sc_def}"
+    read_def $sc_def
+  } elseif { [file exists "inputs/${sc_design}.vg"] } {
     # Read Verilog
-    if { [file exists "inputs/${sc_design}.vg"] } {
-      puts "Reading netlist verilog: inputs/${sc_design}.vg"
-      read_verilog "inputs/${sc_design}.vg"
-    } else {
-      foreach netlist [sc_cfg_get input netlist verilog] {
-        puts "Reading netlist verilog: ${netlist}"
-        read_verilog $netlist
-      }
-    }
+    puts "Reading netlist verilog: inputs/${sc_design}.vg"
+    read_verilog "inputs/${sc_design}.vg"
     link_design $sc_design
   } else {
-    # Read DEF
-    if { [file exists "inputs/${sc_design}.def"] } {
-      # get from previous step
-      puts "Reading DEF: inputs/${sc_design}.def"
-      read_def "inputs/${sc_design}.def"
-    } elseif { [sc_cfg_exists input layout def] } {
-      # Floorplan initialize handled separately in sc_floorplan.tcl
-      set sc_def [lindex [sc_cfg_get input layout def] 0]
-      puts "Reading DEF: ${sc_def}"
-      read_def $sc_def
+    # Read Verilog
+    foreach netlist [sc_cfg_get input netlist verilog] {
+      puts "Reading netlist verilog: ${netlist}"
+      read_verilog $netlist
     }
+    link_design $sc_design
   }
 }
 
@@ -405,7 +403,7 @@ utl::info FLW 1 "Using $sc_rc_signal for signal parasitics estimation"
 
 set_thread_count $sc_threads
 
-if { $sc_task != "floorplan" } {
+if { $sc_task != "floorplan" && $sc_task != "metrics" } {
   ## Setup global routing
 
   # Adjust routing track density

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "1531ad983bfe91384e9253769fdc5f8dcf24fea8",
+    "git-commit": "dcba5786c8e714e3b7682a98d73de40e875699b1",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",

{siliconcompiler-0.28.5.dist-info → siliconcompiler-0.28.7.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.5
+Version: 0.28.7
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -34,22 +34,23 @@ Requires-Dist: graphviz ==0.20.3
 Requires-Dist: distro ==1.9.0
 Requires-Dist: packaging <24,>=21.3
 Requires-Dist: psutil >=5.8.0
-Requires-Dist: Pillow ==10.4.0
 Requires-Dist: GitPython ==3.1.43
 Requires-Dist: lambdapdk >=0.1.38
-Requires-Dist: PyGithub ==2.4.0
+Requires-Dist: PyGithub ==2.5.0
 Requires-Dist: urllib3 >=1.26.0
 Requires-Dist: fasteners ==0.19
 Requires-Dist: fastjsonschema ==2.20.0
 Requires-Dist: docker ==7.1.0
 Requires-Dist: sc-surelog ==1.84.1
 Requires-Dist: orjson ==3.10.11
-Requires-Dist: streamlit ==1.39.0
-Requires-Dist: streamlit-agraph ==0.0.45
-Requires-Dist: streamlit-antd-components ==0.3.2
-Requires-Dist: streamlit-javascript ==0.1.5
-Requires-Dist: streamlit-autorefresh ==1.0.1
+Requires-Dist: streamlit ==1.40.0 ; python_full_version != "3.9.7"
+Requires-Dist: streamlit-agraph ==0.0.45 ; python_full_version != "3.9.7"
+Requires-Dist: streamlit-antd-components ==0.3.2 ; python_full_version != "3.9.7"
+Requires-Dist: streamlit-javascript ==0.1.5 ; python_full_version != "3.9.7"
+Requires-Dist: streamlit-autorefresh ==1.0.1 ; python_full_version != "3.9.7"
 Requires-Dist: importlib-metadata ; python_version < "3.10"
+Requires-Dist: Pillow ==10.4.0 ; python_version <= "3.8"
+Requires-Dist: Pillow ==11.0.0 ; python_version >= "3.9"
 Provides-Extra: docs
 Requires-Dist: Sphinx ==8.1.3 ; extra == 'docs'
 Requires-Dist: pip-licenses ==5.0.0 ; extra == 'docs'
@@ -57,7 +58,7 @@ Requires-Dist: pydata-sphinx-theme ==0.16.0 ; extra == 'docs'
 Requires-Dist: sc-leflib >=0.2.0 ; extra == 'docs'
 Provides-Extra: examples
 Requires-Dist: migen ==0.9.2 ; extra == 'examples'
-Requires-Dist: lambdalib ==0.3.0 ; extra == 'examples'
+Requires-Dist: lambdalib ==0.3.1 ; extra == 'examples'
 Provides-Extra: profile
 Requires-Dist: gprof2dot ==2024.6.6 ; extra == 'profile'
 Provides-Extra: test
@@ -65,12 +66,13 @@ Requires-Dist: pytest ==8.3.3 ; extra == 'test'
 Requires-Dist: pytest-xdist ==3.6.1 ; extra == 'test'
 Requires-Dist: pytest-timeout ==2.3.1 ; extra == 'test'
 Requires-Dist: pytest-asyncio ==0.24.0 ; extra == 'test'
-Requires-Dist: pytest-cov ==5.0.0 ; extra == 'test'
 Requires-Dist: responses ==0.25.3 ; extra == 'test'
 Requires-Dist: PyVirtualDisplay ==3.0 ; extra == 'test'
 Requires-Dist: flake8 ==7.1.1 ; extra == 'test'
 Requires-Dist: tclint ==0.4.2 ; extra == 'test'
 Requires-Dist: codespell ==2.3.0 ; extra == 'test'
+Requires-Dist: pytest-cov ==5.0.0 ; (python_version <= "3.8") and extra == 'test'
+Requires-Dist: pytest-cov ==6.0.0 ; (python_version >= "3.9") and extra == 'test'
 
 ![SiliconCompiler](https://raw.githubusercontent.com/siliconcompiler/siliconcompiler/main/docs/_static/sc_logo_with_text.png)
 

{siliconcompiler-0.28.5.dist-info → siliconcompiler-0.28.7.dist-info}/RECORD

@@ -1,8 +1,8 @@
 siliconcompiler/__init__.py,sha256=Ke_Bcryj9N6MoUq_5z_IDW3qMrUzR-3-kJVsvUenYzY,511
 siliconcompiler/__main__.py,sha256=JwWkcvaNngqgMWprEQ1cFy2Wdq9GMvk46UGTHyh_qvM,170
 siliconcompiler/_common.py,sha256=c6r0SbI2xTpNOZayFsyCDo0riJGNJSPN-0zW8R7rDBI,1488
-siliconcompiler/_metadata.py,sha256=jaUgT5R28lGdBWHqU0NGMNPPyrH8AI5laRlGivIlNPQ,1264
-siliconcompiler/core.py,sha256=uDm5cAV9DEe_s4vyu5faWQHhFSm7loTcnozWc3byloE,135370
+siliconcompiler/_metadata.py,sha256=uHqTgPki2c0kr5ODJxHpeZjAGsSPLAYzpKQui1WbfCk,1264
+siliconcompiler/core.py,sha256=_T1eEY7lUsrbaEBUaG1WSAzY2JFxyz5tXEKxvoCGZaI,135718
 siliconcompiler/flowgraph.py,sha256=WLcbBWFj5DdYRRIxNy_Djm2v4yN9WELQM_ypNPB5QVM,21963
 siliconcompiler/issue.py,sha256=9ZpdEBh8QB56-bZ1YXRnjqgg9hwnFty2u1o5oI66W7M,11125
 siliconcompiler/package.py,sha256=nGFzYI63dwO6ULEyEGHu_Pd-8QYMWu8BtpzgwEmppag,14111
@@ -18,6 +18,7 @@ siliconcompiler/apps/sc_remote.py,sha256=M7wH7lULkeDSEiVkvTY2xmuAK8lJ-3eVM6fC3bq
 siliconcompiler/apps/sc_server.py,sha256=d3SCfKtNneIBiAk7Udc5SqXvSIoFSK40iHWcKuY7unk,894
 siliconcompiler/apps/sc_show.py,sha256=KZGm6nd2On3a15u-OPQnLxNetiHndJKqzWMZG2_Q_1g,4652
 siliconcompiler/apps/smake.py,sha256=jj69IuMLf4jblpVGeLT3GAvC-zDLHwPq16YPKtHosdA,7124
+siliconcompiler/apps/utils/summarize.py,sha256=mcViWpuS8UI2JqOF-QD99YAl0tjiy6_TbVl_coRCmNI,1291
 siliconcompiler/checklists/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/checklists/oh_tapeout.py,sha256=xBXAHOVNslFUlOfVTLLoPEJazczP8MTsa5EGo5GYQk0,1441
 siliconcompiler/data/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
@@ -83,7 +84,7 @@ siliconcompiler/report/report.py,sha256=Bw09BzVAm1gDBPf2jR3FrEF0434B6bSIa-E3IWby
 siliconcompiler/report/summary_image.py,sha256=tKuoLiG6Whvnc8LHeSzU4FookpBkYYCMWUGb-ux2i8k,3570
 siliconcompiler/report/summary_table.py,sha256=Y5ByOCJQtNOXIz5n9VU_CBHOTdSE0g8ClmfflWkQcXU,3386
 siliconcompiler/report/utils.py,sha256=70klZsAKwhW55kOxBBdV9zzOU-NorMk6y6riMyKXo7c,6423
-siliconcompiler/report/dashboard/__init__.py,sha256=YNCeN4Ni2GEPoXuZ-ymyejOcjaXzjX-cT9jBnY0apgw,5378
+siliconcompiler/report/dashboard/__init__.py,sha256=bvSfStUvkMa1zW1R5WtzzzKKAMm9FCNiPbIIFXOotJ0,5554
 siliconcompiler/report/dashboard/state.py,sha256=qBAmLpKb0xXqf2vRbBBgYs8P71v3MGIL6z0WHoAED-Y,5924
 siliconcompiler/report/dashboard/viewer.py,sha256=scF4MkbOdqM1pRCzGWnXeMrk4r2M4Y2cDyEIrAWCFiw,1095
 siliconcompiler/report/dashboard/components/__init__.py,sha256=BkVt0JakAj9kC5WlewdvFESwygjDmhyj85xiV8oc00I,18097
@@ -215,7 +216,7 @@ siliconcompiler/tools/openroad/cts.py,sha256=CZz_eJxCyuMpA7bvQaDm6dYgOkUM9phNKD1
 siliconcompiler/tools/openroad/dfm.py,sha256=RjdOqq7oPVSx5HzYUTSlBh4ZGnVfJqJHR0cs4WdG1pQ,2244
 siliconcompiler/tools/openroad/export.py,sha256=svZZlcUIq9FTDydpoDZdlPyoMVYIkLBUTIBD2dm8TOk,5273
 siliconcompiler/tools/openroad/floorplan.py,sha256=y7V2WOhHW0MhMJkjx4hQuTsiIKCMpcJiQEu4RaMlq_k,2804
-siliconcompiler/tools/openroad/metrics.py,sha256=y6pPn-iHHL4Wd80ktX2bHfDsCQDxScPjxEweVTIIOv8,1049
+siliconcompiler/tools/openroad/metrics.py,sha256=SyGF-foyfJz2VZRxEdA_HCKI9wW3s8jzdBkph1WMG3E,1048
 siliconcompiler/tools/openroad/openroad.py,sha256=Xbs2FcTy1ooMhi6NIksidlGi4a8EAnmtUk6Gm8Ez98c,46911
 siliconcompiler/tools/openroad/physyn.py,sha256=ZgEPRTGyXe930PsXNHx1p7ITsBa6x7_EyZfW8vM0-O8,682
 siliconcompiler/tools/openroad/place.py,sha256=0eRg3n0x3zawg8jp7akDpc1KbUw4LKqeGJ2MMliXbnU,1018
@@ -226,7 +227,7 @@ siliconcompiler/tools/openroad/route.py,sha256=4kLuBXeCyztS3sccORtjxSS8et0OFtaxG
 siliconcompiler/tools/openroad/screenshot.py,sha256=VWh74bLxgeW_8YOhUokDYDIN8rsQgb1G3KMLOPbF-EQ,1970
 siliconcompiler/tools/openroad/show.py,sha256=YtdKChcf2cdp2QoKvoHBjeKUWLP-7A8kWe3TfsZhuVw,3731
 siliconcompiler/tools/openroad/scripts/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
-siliconcompiler/tools/openroad/scripts/sc_apr.tcl,sha256=DsMZMD5GvFKwlUbo00D0_y_jLn1JPQT8Ip8yjNZZEk4,20386
+siliconcompiler/tools/openroad/scripts/sc_apr.tcl,sha256=2HFzF54m6I1rGSYPb-n9eyGAkKFeiSyR0R0pN0hVXDQ,20320
 siliconcompiler/tools/openroad/scripts/sc_cts.tcl,sha256=IcHanlIAwd0183CaRTNG4lzP-DuFy5GYu4gGsUftBBo,1987
 siliconcompiler/tools/openroad/scripts/sc_dfm.tcl,sha256=vhIUebTDyDtg7mnwDzUgMmdKZd5NmgG68wQBj1P34Pg,587
 siliconcompiler/tools/openroad/scripts/sc_export.tcl,sha256=-r3WUFON7gMgXxcJUL_uGBp_-wi46h1hAMKlRWtOzWg,2830
@@ -311,7 +312,7 @@ siliconcompiler/tools/yosys/techmaps/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeu
 siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v,sha256=M4T-ygiKmlsprl5eGGLaV5w6HVqlEepn0wlUDmOkapg,773
 siliconcompiler/tools/yosys/templates/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/yosys/templates/abc.const,sha256=TAq9ThdLMYCJGrtToEU0gWcLuEtjE4Gk8huBbTm1v-I,116
-siliconcompiler/toolscripts/_tools.json,sha256=O2D-CCc6HaxpLgqVuuRojjwc2hb5N0Xetzdjy_Rocxc,3959
+siliconcompiler/toolscripts/_tools.json,sha256=wTknmgxxAimBLm0crN_uDsJ40sbt-rUQFEMAbc37qiA,3959
 siliconcompiler/toolscripts/_tools.py,sha256=P30KY_xbbjl8eHGsPAxDcAzWvJJpiL07ZfGZZDQbdR8,7174
 siliconcompiler/toolscripts/rhel8/install-chisel.sh,sha256=lPORZN7vlBX6sJSv01JOIiDE9-_7GcCZGA7EP5ri3MQ,525
 siliconcompiler/toolscripts/rhel8/install-ghdl.sh,sha256=xCLeEUuJVI_6PVEvnTwBsTWoEHiQg0TY3x-tJXfg6Zk,459
@@ -412,9 +413,9 @@ siliconcompiler/toolscripts/ubuntu24/install-yosys.sh,sha256=zpyt0MVI7tY8kGY2GII
 siliconcompiler/utils/__init__.py,sha256=fdTd5f6W-45YiVY4lU2lyVWE4Y97-uRUfEXY8SpAFgU,13887
 siliconcompiler/utils/asic.py,sha256=cMLs7dneSmh5BlHS0-bZ1tLUpvghTw__gNaUCMpyBds,4986
 siliconcompiler/utils/showtools.py,sha256=QPlS42bkJM3EPKDcoxA0oATSFJM2TFpz-ZVCBV_7Ts4,1306
-siliconcompiler-0.28.5.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
-siliconcompiler-0.28.5.dist-info/METADATA,sha256=2UvkeavcC7n0QzshBwK0j9gXuKE_jlh5YQb9BEuJhMs,10463
-siliconcompiler-0.28.5.dist-info/WHEEL,sha256=P9jw-gEje8ByB7_hXoICnHtVCrEwMQh-630tKvQWehc,91
-siliconcompiler-0.28.5.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
-siliconcompiler-0.28.5.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
-siliconcompiler-0.28.5.dist-info/RECORD,,
+siliconcompiler-0.28.7.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
+siliconcompiler-0.28.7.dist-info/METADATA,sha256=1w3SlTr_7Lwc6Mu0j0DkPXC-7zkI-aA9b6-CR48UdRo,10823
+siliconcompiler-0.28.7.dist-info/WHEEL,sha256=a7TGlA-5DaHMRrarXjVbQagU3Man_dCnGIWMJr5kRWo,91
+siliconcompiler-0.28.7.dist-info/entry_points.txt,sha256=TZVS-8akO-8Z1Z1oMjgWryzk_F9dAW74d2ArJV843pg,501
+siliconcompiler-0.28.7.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
+siliconcompiler-0.28.7.dist-info/RECORD,,

{siliconcompiler-0.28.5.dist-info → siliconcompiler-0.28.7.dist-info}/WHEEL

@@ -1,5 +1,5 @@
 Wheel-Version: 1.0
-Generator: setuptools (75.3.0)
+Generator: setuptools (75.4.0)
 Root-Is-Purelib: true
 Tag: py3-none-any