siliconcompiler 0.28.4__py3-none-any.whl → 0.28.6__py3-none-any.whl

siliconcompiler/scheduler/__init__.py

@@ -688,7 +688,9 @@ def _makecmd(chip, tool, task, step, index, script_name='replay.sh', include_pat
         runtime_options = getattr(chip._get_tool_module(step, index), 'runtime_options', None)
     if runtime_options:
         try:
+            chip.schema._start_record_access()
             cmdlist.extend(parse_options(runtime_options(chip)))
+            chip.schema._stop_record_access()
         except Exception as e:
             chip.logger.error(f'Failed to get runtime options for {tool}/{task}')
             raise e
@@ -983,7 +985,9 @@ def _post_process(chip, step, index):
     func = getattr(chip._get_task_module(step, index, flow=flow), 'post_process', None)
     if func:
         try:
+            chip.schema._start_record_access()
             func(chip)
+            chip.schema._stop_record_access()
         except Exception as e:
             chip.logger.error(f'Failed to run post-process for {tool}/{task}.')
             print_traceback(chip, e)
@@ -1076,7 +1080,9 @@ def _pre_process(chip, step, index):
     func = getattr(chip._get_task_module(step, index, flow=flow), 'pre_process', None)
     if func:
         try:
+            chip.schema._start_record_access()
             func(chip)
+            chip.schema._stop_record_access()
         except Exception as e:
             chip.logger.error(f"Pre-processing failed for '{tool}/{task}'.")
             raise e
@@ -1088,6 +1094,8 @@ def _pre_process(chip, step, index):
 def _set_env_vars(chip, step, index):
     flow = chip.get('option', 'flow')
     tool, task = get_tool_task(chip, step, index, flow)
+
+    chip.schema._start_record_access()
     # License file configuration.
     for item in chip.getkeys('tool', tool, 'licenseserver'):
         license_file = chip.get('tool', tool, 'licenseserver', item, step=step, index=index)
@@ -1100,6 +1108,8 @@ def _set_env_vars(chip, step, index):
         if val:
             os.environ[item] = val
 
+    chip.schema._stop_record_access()
+
 
 def _check_tool_version(chip, step, index, run_func=None):
     '''
@@ -1191,6 +1201,9 @@ def _hash_files(chip, step, index, setup=False):
 
 
 def _finalizenode(chip, step, index, replay):
+    if chip.schema._do_record_access():
+        assert_required_accesses(chip, step, index)
+
     flow = chip.get('option', 'flow')
     tool, task = get_tool_task(chip, step, index, flow)
     quiet = (
@@ -1286,6 +1299,86 @@ def assert_output_files(chip, step, index):
             chip=chip)
 
 
+def assert_required_accesses(chip, step, index):
+    flow = chip.get('option', 'flow')
+    jobname = chip.get('option', 'jobname')
+    tool, task = get_tool_task(chip, step, index, flow)
+
+    if tool == 'builtin':
+        return
+
+    gets = chip.schema._get_record_access()
+    logfile = os.path.join(
+        chip.getworkdir(jobname=jobname, step=step, index=index),
+        f'{step}.log')
+
+    with sc_open(logfile) as f:
+        for line in f:
+            if line.startswith(Schema._RECORD_ACCESS_IDENTIFIER):
+                key = line[len(Schema._RECORD_ACCESS_IDENTIFIER):].strip().split(',')
+                if chip.valid(*key, check_complete=True):
+                    gets.add(tuple(key))
+
+    def get_value(*key):
+        if chip.get(*key, field='pernode') == 'never':
+            return chip.get(*key)
+        else:
+            return chip.get(*key, step=step, index=index)
+
+    getkeys = set()
+    # Remove keys with empty values
+    for key in set(sorted(gets)):
+        if get_value(*key):
+            getkeys.add(key)
+
+    # Remove keys that dont matter
+    exempt = [
+        ('design',),
+        ('arg', 'step'), ('arg', 'index'),
+        ('option', 'jobname'), ('option', 'flow'), ('option', 'strict'), ('option', 'builddir'),
+        ('option', 'quiet'),
+        ('tool', tool, 'exe'),
+        ('tool', tool, 'task', task, 'require'),
+        ('tool', tool, 'task', task, 'threads'),
+        ('flowgraph', flow, step, index, 'tool'), ('flowgraph', flow, step, index, 'task'),
+        ('flowgraph', flow, step, index, 'taskmodule')]
+    for key in chip.getkeys('metric'):
+        exempt.append(('metric', key))
+    for key in chip.getkeys('tool', tool, 'task', task, 'report'):
+        exempt.append(('tool', tool, 'task', task, 'report', key))
+
+    # Get exempted keys from task
+    func = getattr(chip._get_task_module(step, index, flow=flow), 'exempt_keys', None)
+    if func:
+        # No need for try / except since this must work properly
+        exempt.extend(func(chip))
+
+    required = set(
+        [tuple(key.split(',')) for key in chip.get('tool', tool, 'task', task, 'require',
+                                                   step=step, index=index)])
+
+    for key in set(exempt):
+        if key in getkeys:
+            getkeys.remove(key)
+        if key in required:
+            required.remove(key)
+
+    excess_require = required.difference(getkeys)
+    if True:
+        for key in sorted(excess_require):
+            chip.logger.error(f"{step}{index} does not require requirement: {','.join(key)}")
+    missing_require = getkeys.difference(required)
+    for key in sorted(missing_require):
+        chip.logger.error(f"{step}{index} has an unexpressed requirement: "
+                          f"{','.join(key)} = {get_value(*key)}")
+
+    if missing_require:
+        raise SiliconCompilerError(
+            f'Requirements for {step}{index} does not match access list: '
+            f'{", ".join([",".join(key) for key in sorted(missing_require)])}',
+            chip=chip)
+
+
 def _reset_flow_nodes(chip, flow, nodes_to_execute):
     # Reset flowgraph/records/metrics by probing build directory. We need
     # to set values to None for steps we may re-run so that merging

siliconcompiler/schema/schema_cfg.py

@@ -10,7 +10,7 @@ try:
 except ImportError:
     from siliconcompiler.schema.utils import trim
 
-SCHEMA_VERSION = '0.48.2'
+SCHEMA_VERSION = '0.48.4'
 
 #############################################################################
 # PARAM DEFINITION
@@ -1252,7 +1252,6 @@ def schema_datasheet(cfg, name='default', mode='default'):
     # Package Description
     #########################
 
-    # high level description
     scparam(cfg, ['datasheet', 'package', name, 'type'],
             sctype='enum',
             enum=['bga', 'lga', 'csp', 'qfn', 'qfp', 'sop', 'die', 'wafer'],
@@ -1263,6 +1262,16 @@ def schema_datasheet(cfg, name='default', mode='default'):
                 "api: chip.set('datasheet', 'package', 'abcd', 'type', 'bga')"],
             schelp="""Package type specified on a named package basis.""")
 
+    scparam(cfg, ['datasheet', 'package', name, 'footprint'],
+            sctype='str',
+            shorthelp="Datasheet: package footprint",
+            switch="-datasheet_package_footprint 'name <str>'",
+            example=[
+                "cli: -datasheet_package_footprint 'abcd soic8'",
+                "api: chip.set('datasheet', 'package', 'abcd', 'footprint', 'soic8')"],
+            schelp="""Package footprint name. The name of the footprint can be a standard
+            footprint name or a reference designator from a footprint library.""")
+
     scparam(cfg, ['datasheet', 'package', name, 'drawing'],
             sctype='[file]',
             shorthelp="Datasheet: package drawing",
@@ -2158,7 +2167,10 @@ def schema_metric(cfg, step='default', index='default'):
                 device families.""")
 
     metrics = {'cellarea': 'cell area (ignoring fillers)',
-               'totalarea': 'physical die area'}
+               'totalarea': 'physical die area',
+               'macroarea': 'macro cell area',
+               'padcellarea': 'io pad cell area',
+               'stdcellarea': 'standard cell area'}
 
     for item, val in metrics.items():
         scparam(cfg, ['metric', item],

siliconcompiler/schema/schema_obj.py

@@ -61,6 +61,8 @@ class Schema:
         logger (logging.Logger): instance of the parent logger if available
     """
 
+    _RECORD_ACCESS_IDENTIFIER = "SC_CFG_ACCESS_KEY"
+
     # Special key in node dict that represents a value corresponds to a
     # global default for all steps/indices.
     GLOBAL_KEY = 'global'
@@ -70,6 +72,9 @@ class Schema:
         if cfg is not None and manifest is not None:
             raise ValueError('You may not specify both cfg and manifest')
 
+        # Use during testing to record calls to Schema.get
+        self._init_record_access()
+
         self._init_logger(logger)
 
         self._stop_journal()
@@ -256,6 +261,10 @@ class Schema:
 
         See :meth:`~siliconcompiler.core.Chip.get` for detailed documentation.
         """
+
+        if self.__record_access["recording"]:
+            self.__record_access["record"].add(tuple(keypath))
+
         # Prevent accidental modifications of the schema content by not passing a reference
         return copy.copy(self.__get(*keypath, field=field, job=job, step=step, index=index))
 
@@ -1087,7 +1096,9 @@ class Schema:
 
         if template:
             fout.write(template.render(manifest_dict='\n'.join(tcl_set_cmds),
-                                       scroot=os.path.abspath(PACKAGE_ROOT)))
+                                       scroot=os.path.abspath(PACKAGE_ROOT),
+                                       record_access=self._do_record_access(),
+                                       record_access_id=Schema._RECORD_ACCESS_IDENTIFIER))
         else:
             for cmd in tcl_set_cmds:
                 fout.write(cmd + '\n')
@@ -1305,6 +1316,45 @@ class Schema:
             except Exception as e:
                 self.logger.error(f'Exception: {e}')
 
+    #######################################
+    def _do_record_access(self):
+        '''
+        Determine if Schema should record calls to .get
+        '''
+        return False
+
+    #######################################
+    def _init_record_access(self):
+        '''
+        Initialize record access data record
+        '''
+        self.__record_access = {
+            "do": self._do_record_access(),
+            "recording": False,
+            "record": set()
+        }
+
+    #######################################
+    def _start_record_access(self):
+        '''
+        Start recording calls to .get
+        '''
+        self.__record_access["recording"] = True
+
+    #######################################
+    def _stop_record_access(self):
+        '''
+        Stop recording calls to .get
+        '''
+        self.__record_access["recording"] = False
+
+    #######################################
+    def _get_record_access(self):
+        '''
+        Return calls to record_access
+        '''
+        return self.__record_access["record"].copy()
+
     #######################################
     def get_default(self, *keypath):
         '''Returns default value of a parameter.

siliconcompiler/targets/interposer_demo.py

@@ -0,0 +1,56 @@
+from siliconcompiler import Chip
+from siliconcompiler.flows import interposerflow, drcflow
+
+from lambdapdk import interposer
+from lambdapdk.interposer.libs import bumps
+
+
+####################################################
+# Target Setup
+####################################################
+def setup(chip):
+    '''
+    Interposer Demo Target
+    '''
+
+    # 1. Load PDK, flow, libs
+    chip.use(interposer)
+    chip.use(bumps)
+    chip.use(interposerflow)
+    chip.use(drcflow)
+
+    # 2. Set default targets
+    chip.set('option', 'flow', 'interposerflow', clobber=False)
+    chip.set('option', 'pdk', 'interposer', clobber=False)
+    chip.set('option', 'stackup', '3ML_0400', clobber=False)
+    chip.set('option', 'var', 'openroad_libtype', 'none', clobber=False)
+    chip.set('option', 'var', 'klayout_libtype', 'none', clobber=False)
+
+    # 3. Set project specific design choices
+    chip.set('asic', 'macrolib', 'interposer_bumps', clobber=False)
+
+    # 4. get project specific design choices
+    chip.set('asic', 'delaymodel', 'nldm', clobber=False)
+
+    # 5. Timing corners
+    chip.set('constraint', 'timing', 'slow', 'libcorner', 'slow', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'pexcorner', 'maximum', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'fast', 'libcorner', 'fast', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'pexcorner', 'minimum', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'typical', 'libcorner', 'typ', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'pexcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'check', ['setup', 'hold'], clobber=False)
+
+
+#########################
+if __name__ == "__main__":
+    target = Chip('<target>')
+    setup(target)
+    target.write_manifest('interposer_demo.json')

siliconcompiler/templates/tcl/manifest.tcl.j2

@@ -16,6 +16,8 @@ proc sc_cfg_get { args } {
     # Refer to global sc_cfg dictionary
     global sc_cfg
 
+    {% if record_access %}puts "{{ record_access_id }} [join $args ,]"{% endif %}
+
     if { ![sc_cfg_exists {*}$args] } {
         throw {FLOW KEYERROR} "key \"$args\" is not in the siliconcompiler configuration"
     }

siliconcompiler/tools/klayout/export.py

@@ -41,11 +41,9 @@ def setup(chip):
                               step=step, index=index)[0]
     sc_stream_order = [default_stream, *[s for s in streams if s != default_stream]]
 
-    if stackup and targetlibs:
+    if stackup:
         macrolibs = get_libraries(chip, 'macro')
 
-        chip.add('tool', tool, 'task', task, 'require', ",".join(['asic', 'logiclib']),
-                 step=step, index=index)
         chip.add('tool', tool, 'task', task, 'require', ",".join(['option', 'stackup']),
                  step=step, index=index)
         req_set = False
@@ -83,7 +81,12 @@ def setup(chip):
                      ",".join(['library', lib, 'output', stackup, 'lef']),
                      step=step, index=index)
     else:
-        chip.error('Stackup and targetlib parameters required for Klayout.')
+        chip.error('Stackup parameter required for Klayout.')
+
+    if not targetlibs:
+        chip.add('tool', tool, 'task', task, 'require',
+                 'option,var,klayout_libtype',
+                 step=step, index=index)
 
     # Input/Output requirements for default flow
     design = chip.top()

siliconcompiler/tools/klayout/klayout_export.py

@@ -61,6 +61,9 @@ def gds_export(design_name, in_def, in_files, out_file, tech, allow_missing, con
     for cell in def_cells:
         print(f"  [INFO] DEF cell: {cell}")
 
+    if f"{design_name}_DEF_FILL" in def_cells:
+        def_cells.remove(f"{design_name}_DEF_FILL")
+
     # Load in the gds to merge
     print("[INFO] Merging GDS/OAS files...")
     for fil in in_files:

siliconcompiler/tools/klayout/klayout_utils.py

@@ -31,8 +31,14 @@ def technology(design, schema):
         sc_stackup = schema.get('option', 'stackup')
     else:
         sc_stackup = schema.get('pdk', sc_pdk, 'stackup')[0]
-    sc_mainlib = schema.get('asic', 'logiclib', step=sc_step, index=sc_index)[0]
-    sc_libtype = schema.get('library', sc_mainlib, 'asic', 'libarch', step=sc_step, index=sc_index)
+
+    logiclibs = schema.get('asic', 'logiclib', step=sc_step, index=sc_index)
+    if not logiclibs:
+        sc_libtype = schema.get('option', 'var', 'klayout_libtype')[0]
+    else:
+        sc_mainlib = logiclibs[0]
+        sc_libtype = schema.get('library', sc_mainlib, 'asic', 'libarch',
+                                step=sc_step, index=sc_index)
 
     sc_libs = []
     sc_libs += get_libraries(schema, 'logic')

siliconcompiler/tools/openroad/metrics.py

@@ -0,0 +1,44 @@
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
+
+
+def setup(chip):
+    '''
+    Extract metrics
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    _set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'clock_placement',
+        'clock_trees',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/openroad.py

@@ -326,6 +326,9 @@ def post_process(chip):
             ('vias', 'sc__step__route__vias', True, None),
             ('wirelength', 'sc__step__route__wirelength', True, 'distance'),
             ('cellarea', 'sc__metric__design__instance__area', True, 'area'),
+            ('stdcellarea', 'sc__metric__design__instance__area__stdcell', True, 'area'),
+            ('macroarea', 'sc__metric__design__instance__area__macros', True, 'area'),
+            ('padcellarea', 'sc__metric__design__instance__area__padcells', True, 'area'),
             ('totalarea', 'sc__metric__design__core__area', True, 'area'),
             ('utilization', 'sc__metric__design__instance__utilization', True, 100.0),
             ('setuptns', 'sc__metric__timing__setup__tns', has_timing, 'time'),

siliconcompiler/tools/openroad/rdlroute.py

@@ -0,0 +1,97 @@
+import os
+
+from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools._common.asic import set_tool_task_var
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+
+
+def setup(chip):
+    '''
+    Perform floorplanning, pin placements, macro placements and power grid generation
+    '''
+
+    # Generic tool setup.
+    # default tool settings, note, not additive!
+
+    tool = 'openroad'
+    script = 'sc_rdlroute.tcl'
+    refdir = os.path.join('tools', tool, 'scripts')
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    chip.set('tool', tool, 'exe', tool)
+    chip.set('tool', tool, 'vswitch', '-version')
+    chip.set('tool', tool, 'version', '>=v2.0-16839')
+    chip.set('tool', tool, 'format', 'tcl')
+
+    # exit automatically in batch mode and not breakpoint
+    option = ''
+    if exit and not chip.get('option', 'breakpoint', step=step, index=index):
+        option += " -exit"
+
+    option += " -metrics reports/metrics.json"
+    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index)
+
+    # Input/Output requirements for default asicflow steps
+
+    chip.set('tool', tool, 'task', task, 'refdir', refdir,
+             step=step, index=index,
+             package='siliconcompiler')
+    chip.set('tool', tool, 'task', task, 'script', script,
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    if chip.get('option', 'nodisplay'):
+        # Tells QT to use the offscreen platform if nodisplay is used
+        chip.set('tool', tool, 'task', task, 'env', 'QT_QPA_PLATFORM', 'offscreen',
+                 step=step, index=index)
+
+    # basic warning and error grep check on logfile
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', r'^\[WARNING|^Warning',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', r'^\[ERROR',
+             step=step, index=index, clobber=False)
+
+    chip.add('tool', tool, 'task', task, 'require',
+             'option,var,openroad_libtype',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'file', 'rdlroute']),
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'file', 'rdlroute',
+             'script to perform rdl route',
+             field='help')
+
+    set_tool_task_var(chip, param_key='fin_add_fill',
+                      default_value='false',
+                      schelp='true/false, when true enables adding fill, '
+                             'if enabled by the PDK, to the design',
+                      skip='lib')
+
+    if f'{design}.v' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    elif f'{design}.vg' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.vg', step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['input', 'netlist', 'verilog']),
+                 step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', design + '.sdc', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.def', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.odb', step=step, index=index)
+
+
+def pre_process(chip):
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/scripts/sc_apr.tcl

@@ -198,30 +198,28 @@ if { [file exists "inputs/$sc_design.odb"] } {
     }
   }
 
-  if { $sc_task == "floorplan" } {
+  if { [file exists "inputs/${sc_design}.def"] } {
+    # Read DEF
+    # get from previous step
+    puts "Reading DEF: inputs/${sc_design}.def"
+    read_def "inputs/${sc_design}.def"
+  } elseif { [sc_cfg_exists input layout def] } {
+    # Read DEF
+    set sc_def [lindex [sc_cfg_get input layout def] 0]
+    puts "Reading DEF: ${sc_def}"
+    read_def $sc_def
+  } elseif { [file exists "inputs/${sc_design}.vg"] } {
     # Read Verilog
-    if { [file exists "inputs/${sc_design}.vg"] } {
-      puts "Reading netlist verilog: inputs/${sc_design}.vg"
-      read_verilog "inputs/${sc_design}.vg"
-    } else {
-      foreach netlist [sc_cfg_get input netlist verilog] {
-        puts "Reading netlist verilog: ${netlist}"
-        read_verilog $netlist
-      }
-    }
+    puts "Reading netlist verilog: inputs/${sc_design}.vg"
+    read_verilog "inputs/${sc_design}.vg"
     link_design $sc_design
   } else {
-    # Read DEF
-    if { [file exists "inputs/${sc_design}.def"] } {
-      # get from previous step
-      puts "Reading DEF: inputs/${sc_design}.def"
-      read_def "inputs/${sc_design}.def"
-    } elseif { [sc_cfg_exists input layout def] } {
-      # Floorplan initialize handled separately in sc_floorplan.tcl
-      set sc_def [lindex [sc_cfg_get input layout def] 0]
-      puts "Reading DEF: ${sc_def}"
-      read_def $sc_def
+    # Read Verilog
+    foreach netlist [sc_cfg_get input netlist verilog] {
+      puts "Reading netlist verilog: ${netlist}"
+      read_verilog $netlist
     }
+    link_design $sc_design
   }
 }
 
@@ -405,7 +403,7 @@ utl::info FLW 1 "Using $sc_rc_signal for signal parasitics estimation"
 
 set_thread_count $sc_threads
 
-if { $sc_task != "floorplan" } {
+if { $sc_task != "floorplan" && $sc_task != "metrics" } {
   ## Setup global routing
 
   # Adjust routing track density
@@ -504,7 +502,7 @@ if { $sc_task == "show" || $sc_task == "screenshot" } {
   ###############################
 
   utl::push_metrics_stage "sc__metric__{}"
-  source "$sc_refdir/sc_metrics.tcl"
+  source "$sc_refdir/sc_report.tcl"
   utl::pop_metrics_stage
 
   # Images