siliconcompiler 0.28.2__py3-none-any.whl → 0.28.4__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl

@@ -290,12 +290,12 @@ if { $do_automatic_pins } {
 # since we get an error otherwise.
 if { [sc_design_has_unplaced_macros] } {
   if { $openroad_rtlmp_enable == "true" } {
-    set halo_max [expr {
-      max([lindex $openroad_mpl_macro_place_halo 0],
-        [lindex $openroad_mpl_macro_place_halo 1])
-    }]
+    lassign $openroad_mpl_macro_place_halo halo_x halo_y
 
     set rtlmp_args []
+    if { $openroad_rtlmp_max_levels != "" } {
+      lappend rtlmp_args -max_num_level $openroad_rtlmp_max_levels
+    }
     if { $openroad_rtlmp_min_instances != "" } {
       lappend rtlmp_args -min_num_inst $openroad_rtlmp_min_instances
     }
@@ -308,9 +308,48 @@ if { [sc_design_has_unplaced_macros] } {
     if { $openroad_rtlmp_max_macros != "" } {
       lappend rtlmp_args -max_num_macro $openroad_rtlmp_max_macros
     }
+    if { $openroad_rtlmp_min_aspect_ratio != "" } {
+      lappend rtlmp_args -min_ar $openroad_rtlmp_min_aspect_ratio
+    }
+    if { $openroad_rtlmp_fence != "" } {
+      lappend rtlmp_args -fence_lx [lindex $openroad_rtlmp_fence 0]
+      lappend rtlmp_args -fence_ly [lindex $openroad_rtlmp_fence 1]
+      lappend rtlmp_args -fence_ux [lindex $openroad_rtlmp_fence 2]
+      lappend rtlmp_args -fence_uy [lindex $openroad_rtlmp_fence 3]
+    }
+    if { $openroad_rtlmp_bus_planning == "true" } {
+      lappend rtlmp_args -bus_planning
+    }
+    if { $openroad_rtlmp_target_dead_space != "" } {
+      lappend rtlmp_args -target_dead_space $openroad_rtlmp_target_dead_space
+    }
+
+    if { $openroad_rtlmp_area_weight != "" } {
+      lappend rtlmp_args -area_weight $openroad_rtlmp_area_weight
+    }
+    if { $openroad_rtlmp_outline_weight != "" } {
+      lappend rtlmp_args -outline_weight $openroad_rtlmp_outline_weight
+    }
+    if { $openroad_rtlmp_wirelength_weight != "" } {
+      lappend rtlmp_args -wirelength_weight $openroad_rtlmp_wirelength_weight
+    }
+    if { $openroad_rtlmp_guidance_weight != "" } {
+      lappend rtlmp_args -guidance_weight $openroad_rtlmp_guidance_weight
+    }
+    if { $openroad_rtlmp_fence_weight != "" } {
+      lappend rtlmp_args -fence_weight $openroad_rtlmp_fence_weight
+    }
+    if { $openroad_rtlmp_notch_weight != "" } {
+      lappend rtlmp_args -notch_weight $openroad_rtlmp_notch_weight
+    }
+    if { $openroad_rtlmp_blockage_weight != "" } {
+      lappend rtlmp_args -blockage_weight $openroad_rtlmp_blockage_weight
+    }
 
     rtl_macro_placer -report_directory reports/rtlmp \
-      -halo_width $halo_max \
+      -halo_width $halo_x \
+      -halo_height $halo_y \
+      -target_util [sc_global_placement_density] \
       {*}$rtlmp_args
   } else {
     ###########################
@@ -330,6 +369,9 @@ if { [sc_design_has_unplaced_macros] } {
     # technologies we support do not, so we don't include that step for now.
   }
 }
+
+sc_print_macro_information
+
 if { [sc_design_has_unplaced_macros] } {
   utl::error FLW 1 "Design contains unplaced macros."
 }
@@ -349,11 +391,18 @@ global_connect
 # Tap Cells
 ###########################
 
-if { [sc_cfg_tool_task_exists {file} ifp_tapcell] } {
-  set tapcell_file [lindex [sc_cfg_tool_task_get {file} ifp_tapcell] 0]
-  puts "Sourcing tapcell file: ${tapcell_file}"
-  source $tapcell_file
+if {
+  [sc_cfg_tool_task_exists {file} ifp_tapcell] &&
+  [llength [sc_cfg_tool_task_get {file} ifp_tapcell]] > 0
+} {
+  foreach tapcell_file [sc_cfg_tool_task_get {file} ifp_tapcell] {
+    puts "Sourcing tapcell file: ${tapcell_file}"
+    source $tapcell_file
+  }
   global_connect
+} else {
+  utl::warn FLW 1 "Tapcell configuration not provided"
+  cut_rows
 }
 
 ###########################
@@ -402,4 +451,6 @@ foreach net [sc_psm_check_nets] {
 # Remove buffers inserted by synthesis
 ###########################
 
-remove_buffers
+if { [lindex [sc_cfg_tool_task_get var remove_synth_buffers] 0] == "true" } {
+  remove_buffers
+}

siliconcompiler/tools/openroad/scripts/sc_metrics.tcl

@@ -158,3 +158,13 @@ if { $unconstrained_endpoints == "" } {
   set unconstrained_endpoints 0
 }
 utl::metric_int "timing__unconstrained" $unconstrained_endpoints
+
+# Write markers
+foreach markerdb [[ord::get_db_block] getMarkerCategories] {
+  if { [$markerdb getMarkerCount] == 0 } {
+    continue
+  }
+
+  $markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
+  $markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
+}

siliconcompiler/tools/openroad/scripts/sc_procs.tcl

@@ -72,8 +72,10 @@ proc sc_global_placement { args } {
     lappend openroad_gpl_args "-skip_io"
   }
 
+  set density [sc_global_placement_density]
+
   global_placement {*}$openroad_gpl_args \
-    -density [sc_global_placement_density] \
+    -density $density \
     -pad_left $openroad_gpl_padding \
     -pad_right $openroad_gpl_padding
 }
@@ -220,6 +222,34 @@ proc sc_design_has_unplaced_macros { } {
   return false
 }
 
+###########################
+# Print macros placement
+###########################
+
+proc sc_print_macro_information { } {
+  set print_header "true"
+  foreach inst [[ord::get_db_block] getInsts] {
+    if { [$inst isBlock] } {
+      set master [$inst getMaster]
+      set status [$inst getPlacementStatus]
+
+      if { $print_header == "true" } {
+        puts "Macro placement information"
+        set print_header "false"
+      }
+      if { [$inst isPlaced] } {
+        set location [$inst getLocation]
+        set orient [$inst getOrient]
+        set xloc [ord::dbu_to_microns [lindex $location 0]]
+        set yloc [ord::dbu_to_microns [lindex $location 1]]
+        puts "[$inst getName] ([$master getName]): $status at ($xloc um, $yloc um) $orient"
+      } else {
+        utl::warn FLW 1 "[$inst getName] ([$master getName]): UNPLACED"
+      }
+    }
+  }
+}
+
 ###########################
 # Design has unplaced pads
 ###########################

siliconcompiler/tools/openroad/scripts/sc_route.tcl

@@ -8,8 +8,14 @@
 
 proc insert_fillers { } {
   upvar sc_filler sc_filler
-  if { $sc_filler != "" } {
-    filler_placement $sc_filler
+  global sc_mainlib
+
+  set fillers $sc_filler
+  if { [lindex [sc_cfg_tool_task_get var dpl_use_decap_fillers] 0] == "true" } {
+    lappend fillers {*}[sc_cfg_get library $sc_mainlib asic cells decap]
+  }
+  if { $fillers != "" } {
+    filler_placement $fillers
   }
 
   check_placement -verbose

siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl

@@ -3,11 +3,6 @@ gui::save_display_controls
 set sc_resolution \
   [lindex [sc_cfg_tool_task_get {var} show_vertical_resolution] 0]
 
-# Show the drc markers (if any)
-if { [file exists reports/${sc_design}_drc.rpt] } {
-  gui::load_drc reports/${sc_design}_drc.rpt
-}
-
 sc_image_setup_default
 
 sc_save_image "screenshot" "outputs/${sc_design}.png" $sc_resolution

siliconcompiler/tools/openroad/scripts/sc_write_images.tcl

@@ -226,6 +226,12 @@ proc sc_image_clocks { } {
 proc sc_image_clocktree { } {
   gui::show_widget "Clock Tree Viewer"
   global sc_scenarios
+  global sc_design
+
+  sc_image_setup_default
+  gui::set_display_controls "Layers/*" visible true
+  gui::set_display_controls "Nets/*" visible false
+  gui::set_display_controls "Nets/Clock" visible true
 
   set clock_state []
   foreach clock [all_clocks] {
@@ -233,6 +239,7 @@ proc sc_image_clocktree { } {
   }
   set_propagated_clock [all_clocks]
 
+  file mkdir reports/images/clocks
   foreach clock [get_clocks *] {
     if { [llength [get_property $clock sources]] == 0 } {
       # Skip virtual clocks
@@ -243,13 +250,18 @@ proc sc_image_clocktree { } {
     set clock_name [get_name $clock]
     foreach corner $sc_scenarios {
       set path reports/images/clocktree/${clock_name}.${corner}.png
-      utl::info FLW 1 "Saving $clock_name clock tree for $corner in $path"
+      utl::info FLW 1 "Saving \"$clock_name\" clock tree for $corner to $path"
       save_clocktree_image $path \
         -clock $clock_name \
         -width 1024 \
         -height 1024 \
         -corner $corner
     }
+
+    if { [info commands gui::select_clockviewer_clock] != "" } {
+      gui::select_clockviewer_clock ${clock_name}
+      sc_save_image "clock - ${clock_name}" reports/images/clocks/${sc_design}.${clock_name}.png
+    }
   }
 
   foreach {clock state} $clock_state {
@@ -306,21 +318,39 @@ proc sc_image_optimizer { } {
   sc_save_image "optimizer" reports/images/${sc_design}.optimizer.png
 }
 
+proc sc_image_markers { } {
+  global sc_design
+  sc_image_setup_default
+
+  file mkdir reports/images/markers
+  foreach markerdb [[ord::get_db_block] getMarkerCategories] {
+    if { [$markerdb getMarkerCount] == 0 } {
+      continue
+    }
+
+    gui::select_marker_category $markerdb
+
+    sc_save_image \
+      "markers - [$markerdb getName]" \
+      reports/images/markers/${sc_design}.[$markerdb getName].png
+  }
+
+  gui::select_marker_category NULL
+}
+
 # Setup
 file mkdir reports/images
 gui::save_display_controls
 sc_image_setup_default
 
-if { [file exists reports/${sc_design}_drc.rpt] } {
-  # Show the drc markers (if any)
-  gui::load_drc reports/${sc_design}_drc.rpt
-}
-
 # General images
 sc_image_everything
 sc_image_placement
 sc_image_routing
 
+# Markers
+sc_image_markers
+
 # Heatmaps
 if { [sc_cfg_tool_task_check_in_list placement_density var reports] } {
   sc_image_placement_density

siliconcompiler/tools/surelog/__init__.py

@@ -61,24 +61,36 @@ def setup(chip):
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'enable_lowmem', 'false',
              step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'enable_lowmem']),
+             step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'disable_write_cache',
              'true/false, when true instructs Surelog to not write to its cache.',
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'disable_write_cache', 'false',
              step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'disable_write_cache']),
+             step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'disable_info',
              'true/false, when true instructs Surelog to not log infos.',
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'disable_info', 'false',
              step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'disable_info']),
+             step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'disable_note',
              'true/false, when true instructs Surelog to not log notes.',
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'disable_note', 'false',
              step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'disable_note']),
+             step=step, index=index)
 
 
 def parse_version(stdout):

siliconcompiler/tools/verilator/compile.py

@@ -34,24 +34,42 @@ def setup(chip):
     if mode not in (['cc'], ['systemc']):
         chip.error(f"Invalid mode {mode} provided to verilator/compile. Expected one of 'cc' or "
                    "'systemc'")
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'mode']),
+             step=step, index=index)
 
     trace_type = chip.get('tool', tool, 'task', task, 'var', 'trace_type', step=step, index=index)
     if trace_type not in (['vcd'], ['fst']):
         chip.error(f"Invalid trace type {trace_type} provided to verilator/compile. Expected "
                    "one of 'vcd' or 'fst'.")
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'trace_type']),
+             step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'cflags',
              'flags to provide to the C++ compiler invoked by Verilator',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'cflags', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'cflags']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'ldflags',
              'flags to provide to the linker invoked by Verilator',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'ldflags', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'ldflags']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'pins_bv',
              'controls datatypes used to represent SystemC inputs/outputs. See --pins-bv in '
              'Verilator docs for more info.',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'pins_bv', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'pins_bv']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'mode',
              "defines compilation mode for Verilator. Valid options are 'cc' for C++, or 'systemc' "
@@ -61,10 +79,19 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'dir', 'cincludes',
              'include directories to provide to the C++ compiler invoked by Verilator',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'dir', 'cincludes', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'dir', 'cincludes']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'trace',
              "if true, enables trace generation.",
              field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'trace', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'trace']),
+                 step=step, index=index)
+
     chip.set('tool', tool, 'task', task, 'var', 'trace_type',
              "specifies type of wave file to create when [trace] is set. Valid options are "
              "'vcd' or 'fst'. Defaults to 'vcd'.",

siliconcompiler/tools/verilator/verilator.py

@@ -71,6 +71,10 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'file', 'config',
              'Verilator configuration file',
              field='help')
+    if chip.get('tool', tool, 'task', task, 'file', 'config', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'file', 'config']),
+                 step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'var', 'enable_assert',
              'true/false, when true assertions are enabled in Verilator.',
@@ -78,6 +82,11 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'var', 'enable_assert', 'false',
              step=step, index=index, clobber=False)
 
+    if chip.get('tool', tool, 'task', task, 'var', 'enable_assert', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'enable_assert']),
+                 step=step, index=index)
+
     if f'{chip.top()}.v' not in input_provides(chip, step, index):
         add_require_input(chip, 'input', 'rtl', 'verilog')
         add_require_input(chip, 'input', 'rtl', 'systemverilog')

siliconcompiler/tools/vpr/vpr.py

@@ -66,6 +66,20 @@ def setup_tool(chip, clobber=True):
         chip.add('tool', tool, 'task', task, 'require', f'fpga,{part_name},var,{resource}',
                  step=step, index=index)
 
+    add_tool_requirements(chip)
+
+
+def add_tool_requirements(chip):
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    part_name = chip.get('fpga', 'partname')
+
+    chip.add('tool', tool, 'task', task, 'require', f'fpga,{part_name},var,vpr_device_code',
+             step=step, index=index)
+
 
 def runtime_options(chip):
 
@@ -76,6 +90,10 @@ def runtime_options(chip):
 
     options = []
 
+    device_code = chip.get('fpga', part_name, 'var', 'vpr_device_code')
+
+    options.append(f"--device {device_code[0]}")
+
     options.append(f"--write_block_usage {__block_file}")
     options.append("--outfile_prefix outputs/")
 

siliconcompiler/tools/yosys/{syn_asic_fpga_shared.tcl → procs.tcl}

@@ -29,3 +29,26 @@ proc sc_map_memory { lib_file techmap_file do_rom } {
 
     return $design_mod
 }
+
+proc sc_apply_params { } {
+    global sc_design
+
+    yosys chparam -list $sc_design
+    if { [sc_cfg_exists option param] } {
+        yosys echo off
+        set module_params [yosys tee -q -s result.string chparam -list $sc_design]
+        yosys echo on
+
+        dict for {key value} [sc_cfg_get option param] {
+            if { ![string is integer $value] } {
+                set value [concat \"$value\"]
+            }
+
+            if { [string first $key $module_params] != -1 } {
+                yosys chparam -set $key $value $sc_design
+            } else {
+                puts "Warning: $key is not a defined parameter in $sc_design"
+            }
+        }
+    }
+}

siliconcompiler/tools/yosys/sc_screenshot.tcl

@@ -0,0 +1,104 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+yosys echo on
+
+###############################
+# Schema Adapter
+###############################
+
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_design [sc_top]
+
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
+########################################################
+# Design Inputs
+########################################################
+
+if { [file exists "inputs/$sc_design.v"] } {
+    set input_verilog "inputs/$sc_design.v"
+    yosys read_verilog -noblackbox -sv $input_verilog
+    set file_type "v"
+} elseif { [file exists "inputs/$sc_design.vg"] } {
+    set input_verilog "inputs/$sc_design.vg"
+    yosys read_verilog -noblackbox -sv $input_verilog
+    set file_type "vg"
+} elseif { [sc_cfg_tool_task_exists var show_filepath] } {
+    yosys read_verilog -noblackbox -sv [sc_cfg_tool_task_get var show_filepath]
+    set file_type [lindex [sc_cfg_tool_task_get var show_filetype] 0]
+}
+
+########################################################
+# Override top level parameters
+########################################################
+
+sc_apply_params
+
+########################################################
+# Read Libraries
+########################################################
+
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
+if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
+    set sc_macro_libraries \
+        [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
+} else {
+    set sc_macro_libraries []
+}
+
+set sc_blackboxes []
+foreach lib $sc_macrolibs {
+    if { [sc_cfg_exists library $lib output blackbox verilog] } {
+        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
+            lappend sc_blackboxes $lib_f
+        }
+    }
+}
+
+foreach lib_file "$sc_libraries $sc_macro_libraries" {
+    yosys read_liberty -lib $lib_file
+}
+foreach bb_file $sc_blackboxes {
+    yosys log "Reading blackbox model file: $bb_file"
+    yosys read_verilog -sv $bb_file
+}
+
+########################################################
+# Screenshot
+########################################################
+
+yosys hierarchy -top $sc_design
+
+if { $file_type == "v" } {
+    yosys proc
+}
+
+yosys show \
+    -nobg \
+    -format png \
+    -width \
+    -signed \
+    -stretch \
+    -prefix outputs/${sc_design} \
+    $sc_design

siliconcompiler/tools/yosys/sc_syn.tcl

@@ -26,6 +26,12 @@ set sc_flow [sc_cfg_get option flow]
 set sc_optmode [sc_cfg_get option optmode]
 set sc_pdk [sc_cfg_get option pdk]
 
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
 ########################################################
 # Design Inputs
 ########################################################
@@ -57,15 +63,7 @@ if { [file exists "inputs/$sc_design.v"] } {
 # Override top level parameters
 ########################################################
 
-yosys chparam -list
-if { [sc_cfg_exists option param] } {
-    dict for {key value} [sc_cfg_get option param] {
-        if { ![string is integer $value] } {
-            set value [concat \"$value\"]
-        }
-        yosys chparam -set $key $value $sc_design
-    }
-}
+sc_apply_params
 
 ########################################################
 # Synthesis based on mode