siliconcompiler 0.28.0__py3-none-any.whl → 0.28.1__py3-none-any.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.28.0'
+version = '0.28.1'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/flows/dvflow.py

@@ -3,6 +3,8 @@ import siliconcompiler
 from siliconcompiler.tools.icarus import compile as icarus_compile
 from siliconcompiler.tools.verilator import compile as verilator_compile
 from siliconcompiler.tools.execute import exec_input
+from siliconcompiler.tools.xyce import simulate as xyce_simulate
+from siliconcompiler.tools.xdm import convert as xdm_convert
 
 
 ############################################################################
@@ -31,33 +33,68 @@ def setup(flowname='dvflow',
     Setting 'np' > 1 results in multiple independent verification
     pipelines to be launched.
 
+    Supported tools are:
+
+    * icarus
+    * verilator
+    * xyce
+    * xdm-xyce
+
     This flow is a WIP
     '''
 
     flow = siliconcompiler.Flow(flowname)
 
-    tasks = {
-        'compile': None,
-        'sim': None
-    }
+    tasks = {}
+    flow_np = {}
 
     if tool == 'icarus':
         tasks['compile'] = icarus_compile
         tasks['sim'] = exec_input
+
+        flowpipe = [
+            'compile',
+            'sim'
+        ]
+        flow_np = {
+            'compile': 1,
+            'sim': np
+        }
     elif tool == 'verilator':
         tasks['compile'] = verilator_compile
         tasks['sim'] = exec_input
+
+        flowpipe = [
+            'compile',
+            'sim'
+        ]
+        flow_np = {
+            'compile': 1,
+            'sim': np
+        }
+    elif tool == 'xyce':
+        tasks['sim'] = xyce_simulate
+
+        flowpipe = [
+            'sim'
+        ]
+        flow_np = {
+            'sim': np
+        }
+    elif tool == 'xdm-xyce':
+        tasks['compile'] = xdm_convert
+        tasks['sim'] = xyce_simulate
+
+        flowpipe = [
+            'compile',
+            'sim'
+        ]
+        flow_np = {
+            'compile': 1,
+            'sim': np
+        }
     else:
-        raise ValueError(f'{tool} is not a supported tool for {flowname}: icarus')
-
-    flowpipe = [
-        'compile',
-        'sim'
-    ]
-    flow_np = {
-        'compile': 1,
-        'sim': np
-    }
+        raise ValueError(f'{tool} is not a supported tool for {flowname}')
 
     prevstep = None
     # Flow setup

siliconcompiler/libs/sg13g2_stdcell.py

@@ -0,0 +1,8 @@
+import siliconcompiler
+from lambdapdk.ihp130.libs.sg13g2_stdcell import setup
+
+
+#########################
+if __name__ == "__main__":
+    lib = setup(siliconcompiler.Chip('<lib>'))
+    lib.write_manifest(f'{lib.top()}.json')

siliconcompiler/pdks/ihp130.py

@@ -0,0 +1,8 @@
+import siliconcompiler
+from lambdapdk.ihp130 import setup
+
+
+#########################
+if __name__ == "__main__":
+    pdk = setup(siliconcompiler.Chip('<pdk>'))
+    pdk.write_manifest(f'{pdk.top()}.json')

siliconcompiler/schema/schema_cfg.py

@@ -10,7 +10,7 @@ try:
 except ImportError:
     from siliconcompiler.schema.utils import trim
 
-SCHEMA_VERSION = '0.48.1'
+SCHEMA_VERSION = '0.48.2'
 
 #############################################################################
 # PARAM DEFINITION
@@ -3767,7 +3767,7 @@ def schema_constraint(cfg):
             defvalue='R0',
             enum=['R0', 'R90', 'R180', 'R270',
                   'MX', 'MX_R90', 'MX_R180', 'MX_R270',
-                  'MY_R90', 'MY_R180', 'MY_R270',
+                  'MY', 'MY_R90', 'MY_R180', 'MY_R270',
                   'MZ', 'MZ_R90', 'MZ_R180', 'MZ_R270',
                   'MZ_MX', 'MZ_MX_R90', 'MZ_MX_R180', 'MZ_MX_R270',
                   'MZ_MY', 'MZ_MY_R90', 'MZ_MY_R180', 'MZ_MY_R270'],

siliconcompiler/targets/ihp130_demo.py

@@ -0,0 +1,68 @@
+import siliconcompiler
+from siliconcompiler.flows import asicflow, asictopflow, signoffflow, synflow
+from siliconcompiler.checklists import oh_tapeout
+from lambdapdk import ihp130
+from lambdapdk.ihp130.libs import sg13g2_stdcell
+
+
+####################################################
+# Target Setup
+####################################################
+def setup(chip, syn_np=1, floorplan_np=1, physyn_np=1, place_np=1, cts_np=1, route_np=1,
+          timing_np=1):
+    '''
+    IHP130 Demo Target
+    '''
+
+    asic_flow_args = {
+        "syn_np": syn_np,
+        "floorplan_np": floorplan_np,
+        "physyn_np": physyn_np,
+        "place_np": place_np,
+        "cts_np": cts_np,
+        "route_np": route_np
+    }
+    # 1. Load PDK, flow, libs
+    chip.use(ihp130)
+    chip.use(sg13g2_stdcell)
+    chip.use(asicflow, **asic_flow_args)
+    chip.use(synflow, syn_np=syn_np, timing_np=timing_np)
+    chip.use(asictopflow)
+    chip.use(signoffflow)
+    chip.use(oh_tapeout)
+
+    # 2. Set default targets
+    chip.set('option', 'flow', 'asicflow', clobber=False)
+    chip.set('option', 'pdk', 'ihp130', clobber=False)
+    chip.set('option', 'stackup', '5M2TL', clobber=False)
+
+    # 3. Set project specific design choices
+    chip.set('asic', 'logiclib', 'sg13g2_stdcell', clobber=False)
+
+    # 4. get project specific design choices
+    chip.set('asic', 'delaymodel', 'nldm', clobber=False)
+    chip.set('constraint', 'density', 40, clobber=False)
+    chip.set('constraint', 'coremargin', 4.8, clobber=False)
+
+    # 5. Timing corners
+    chip.set('constraint', 'timing', 'slow', 'libcorner', 'slow', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'pexcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'fast', 'libcorner', 'fast', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'pexcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'typical', 'libcorner', 'typ', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'pexcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'check', ['power'], clobber=False)
+
+
+#########################
+if __name__ == "__main__":
+    target = siliconcompiler.Chip('<target>')
+    setup(target)
+    target.write_manifest('ihp130_demo.json')

siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl

@@ -240,11 +240,7 @@ if { [sc_cfg_exists constraint component] } {
 
   dict for {name params} [sc_cfg_get constraint component] {
     set location [dict get $params placement]
-    set rotation [dict get $params rotation]
-    if { [string match "*MZ*" $rotation] } {
-      utl::error FLW 1 "Z mirroring is not supported in OpenROAD"
-    }
-    set rotation [string map {"_" ""} $rotation]
+    set rotation [sc_convert_rotation [dict get $params rotation]]
 
     if { [dict exists $params partname] } {
       set cell [dict get $params partname]

siliconcompiler/tools/openroad/scripts/sc_procs.tcl

@@ -427,3 +427,29 @@ proc count_logic_depth {} {
   # Subtract 1 to account for initial launch
   return [expr { $count - 1 }]
 }
+
+###########################
+# Translate schema rotation
+###########################
+
+proc sc_convert_rotation { rot } {
+  if { [string match "MZ*" $rot] } {
+    utl::error FLW 1 "Z mirroring is not supported in OpenROAD"
+  }
+
+  switch $rot {
+    "R0" { return "R0" }
+    "R90" { return "R90" }
+    "R180" { return "R180" }
+    "R270" { return "R270" }
+    "MX" { return "MX" }
+    "MX_R90" { return "MXR90" }
+    "MX_R180" { return "MY" }
+    "MX_R270" { return "MYR90" }
+    "MY" { return "MY" }
+    "MY_R90" { return "MYR90" }
+    "MY_R180" { return "MX" }
+    "MY_R270" { return "MXR90" }
+    default { utl::error FLW 1 "$rot not recognized" }
+  }
+}

siliconcompiler/tools/xdm/__init__.py

@@ -0,0 +1,28 @@
+'''
+Xyce XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.
+
+Sources: https://github.com/Xyce/XDM
+
+Installation: https://github.com/Xyce/XDM
+
+Status: SC integration WIP
+'''
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'exe', 'xdm_bdl')
+    chip.set('tool', tool, 'vswitch', '-h')
+    chip.set('tool', tool, 'version', '>=v2.7.0', clobber=False)
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    line = stdout.splitlines()[5]
+    return line.split()[1]

siliconcompiler/tools/xdm/convert.py

@@ -0,0 +1,71 @@
+from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools.xdm import setup as tool_setup
+import os
+import shutil
+
+
+def setup(chip):
+    tool_setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    if f'{design}.cir' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.cir',
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require', 'input,netlist,spice',
+                 step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', f'{design}.xyce', step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'option', '--auto',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'option', '--source_file_format hspice',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'option', f'--dir_out outputs/{design}.xyce',
+             step=step, index=index)
+
+    chip.set('tool', 'xdm', 'task', 'convert', 'var', 'rename', 'true',
+             step=step, index=index, clobber=False)
+    chip.set('tool', 'xdm', 'task', 'convert', 'var', 'rename',
+             'true/false: indicate whether to rename the output file to match the '
+             'naming scheme for siliconcompiler', field='help')
+
+
+def runtime_options(chip):
+    return __get_input_file(chip)
+
+
+def __get_input_file(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    design = chip.top()
+
+    if f'{design}.cir' in input_provides(chip, step, index):
+        return [f'inputs/{design}.cir']
+
+    return chip.find_files('input', 'netlist', 'spice',
+                           step=step, index=index)
+
+
+def post_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    if chip.get('tool', 'xdm', 'task', 'convert', 'var', 'rename',
+                step=step, index=index) == ['false']:
+        return
+
+    inputfile = __get_input_file(chip)[0]
+
+    outdir = f'outputs/{chip.top()}.xyce'
+
+    inputfile_base = os.path.basename(inputfile)
+    outputfile_base = f'{chip.top()}.cir'
+
+    if inputfile_base != outputfile_base:
+        shutil.move(os.path.join(outdir, inputfile_base), os.path.join(outdir, outputfile_base))

siliconcompiler/tools/xyce/__init__.py

@@ -0,0 +1,40 @@
+'''
+Xyce is a high performance SPICE-compatible circuit simulator
+capable capable of solving extremely large circuit problems by
+supporting large-scale parallel computing platforms. It also
+supports serial execution on all common desktop platforms,
+and small-scale parallel runs on Unix-like systems.
+
+Documentation: https://xyce.sandia.gov/documentation-tutorials/
+
+Sources: https://github.com/Xyce/Xyce
+
+Installation: https://xyce.sandia.gov/documentation-tutorials/building-guide/
+
+Status: SC integration WIP
+'''
+from siliconcompiler.tools._common import get_tool_task
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def setup(chip):
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'exe', 'Xyce')
+    chip.set('tool', tool, 'vswitch', '-v')
+    chip.set('tool', tool, 'version', '>=v7.8')
+
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', 'warning',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', 'error',
+             step=step, index=index, clobber=False)
+
+
+def parse_version(stdout):
+    ver = stdout.split()[-1]
+    return ver.split('-')[0]

siliconcompiler/tools/xyce/simulate.py

@@ -0,0 +1,70 @@
+from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools.xyce import setup as tool_setup
+import os
+
+
+def setup(chip):
+    tool_setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    if f'{design}.xyce' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.xyce',
+                 step=step, index=index)
+    elif f'{design}.cir' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.cir',
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require', 'input,netlist,spice',
+                 step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'trace', 'false',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'trace', 'true/false, enable dumping all signals',
+             field='help')
+
+    allowed_traced = ['ASCII', 'binary']
+    chip.set('tool', tool, 'task', task, 'var', 'trace_format', 'ASCII',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'trace_format', 'Format to use for traces. '
+             f'Allowed values are {allowed_traced}',
+             field='help')
+
+    if chip.get('tool', tool, 'task', task, 'var', 'trace_format', step=step, index=index)[0] \
+            not in allowed_traced:
+        raise ValueError(f"{chip.get('tool', tool, 'task', task, 'var', 'trace_format')[0]} "
+                         "is not an accepted value")
+
+    if chip.get('tool', tool, 'task', task, 'var', 'trace_format', step=step, index=index) == \
+            ['ASCII']:
+        chip.add('tool', tool, 'task', task, 'option', '-a',
+                 step=step, index=index)
+
+    if chip.get('tool', tool, 'task', task, 'var', 'trace',
+                step=step, index=index) == ['true']:
+        chip.add('tool', tool, 'task', task, 'output', f'{design}.raw',
+                 step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'option', f'-r outputs/{design}.raw',
+                 step=step, index=index)
+
+
+def runtime_options(chip):
+    design = chip.top()
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    if f'{design}.xyce' in input_provides(chip, step, index):
+        if os.path.isfile(f'inputs/{design}.xyce'):
+            return [f'inputs/{design}.xyce']
+        elif os.path.isfile(f'inputs/{design}.xyce/{design}.cir'):
+            return [f'inputs/{design}.xyce/{design}.cir']
+        else:
+            return [f'inputs/{design}.xyce']
+    elif f'{design}.cir' in input_provides(chip, step, index):
+        return [f'inputs/{design}.cir']
+
+    return chip.find_files('input', 'netlist', 'spice', step=step, index=index)

{siliconcompiler-0.28.0.dist-info → siliconcompiler-0.28.1.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.0
+Version: 0.28.1
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -23,7 +23,7 @@ Requires-Dist: packaging <24,>=21.3
 Requires-Dist: psutil >=5.8.0
 Requires-Dist: Pillow ==10.4.0
 Requires-Dist: GitPython ==3.1.43
-Requires-Dist: lambdapdk >=0.1.31
+Requires-Dist: lambdapdk >=0.1.34
 Requires-Dist: PyGithub ==2.4.0
 Requires-Dist: urllib3 >=1.26.0
 Requires-Dist: fasteners ==0.19
@@ -84,7 +84,7 @@ SiliconCompiler is a modular hardware build system ("make for silicon"). The pro
 |**FPGA APR**| VPR, nextpnr, Vivado
 |**Layout Viewer**| Klayout, OpenRoad, Cadence, Synopsys
 |**DRC/LVS**| Magic, Synopsys, Siemens
-|**PDKs**| sky130, gf180, asap7, freepdk45, gf12lp, gf22fdx, intel16
+|**PDKs**| sky130, gf180, asap7, freepdk45, gf12lp, gf22fdx, intel16, ihp130
 
 # Getting Started
 

{siliconcompiler-0.28.0.dist-info → siliconcompiler-0.28.1.dist-info}/RECORD

@@ -1,7 +1,7 @@
 siliconcompiler/__init__.py,sha256=Ke_Bcryj9N6MoUq_5z_IDW3qMrUzR-3-kJVsvUenYzY,511
 siliconcompiler/__main__.py,sha256=JwWkcvaNngqgMWprEQ1cFy2Wdq9GMvk46UGTHyh_qvM,170
 siliconcompiler/_common.py,sha256=yQ0X02-k6ZMVhz74zJwwMQi2DUpnm27NZMvDga84OZc,1234
-siliconcompiler/_metadata.py,sha256=MZM3Ctbc0094rwAXzWxkZG_T3qWEvH9OjGWryTAGgXk,1264
+siliconcompiler/_metadata.py,sha256=FTCBWMpxoH-jmQpBwPPvfqJ8kSV_-zzAj6xCc6zSjMo,1264
 siliconcompiler/core.py,sha256=EvQmBcsjkwVGe8TBb4vx0glnlZd8qd9CS4Fsgh7x0Qw,132714
 siliconcompiler/flowgraph.py,sha256=WLcbBWFj5DdYRRIxNy_Djm2v4yN9WELQM_ypNPB5QVM,21963
 siliconcompiler/issue.py,sha256=9ZpdEBh8QB56-bZ1YXRnjqgg9hwnFty2u1o5oI66W7M,11125
@@ -29,7 +29,7 @@ siliconcompiler/flows/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3h
 siliconcompiler/flows/_common.py,sha256=-T3OPvzgOpzVdHdgQANtPm5h7zzgghhKd4XJH4EKqcE,2133
 siliconcompiler/flows/asicflow.py,sha256=AbnwSersQ4EsBaAvnH3sz44Tj62aroZSGZaTgVSmO6g,6084
 siliconcompiler/flows/asictopflow.py,sha256=UosrdJhh_NVyjigzz2KGhqcy2UBotkwTUUnCdOVaZXg,1155
-siliconcompiler/flows/dvflow.py,sha256=p_pnEut9-G7kkFGpDrHfhxP7H6z70QykcI3O3l0xvYo,2294
+siliconcompiler/flows/dvflow.py,sha256=uchIXjAmKTQljkoBUMl9UWFvzwsON4vFWTBGCxPpKE4,3064
 siliconcompiler/flows/fpgaflow.py,sha256=l6uhqieVwEBTwA4pHuAHYOR7y1-61xHVQQaxj94KU5g,6359
 siliconcompiler/flows/generate_openroad_rcx.py,sha256=Czc3GEm0Q0dkPR0sRv1VdhRfVCAI8y6h3C-HVaxdmvE,2340
 siliconcompiler/flows/lintflow.py,sha256=mCOojrSnd2gYoV80rsKpim5iPlV8Kb7rHx9jSEUVMtc,1000
@@ -44,12 +44,14 @@ siliconcompiler/libs/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hS
 siliconcompiler/libs/asap7sc7p5t.py,sha256=vHu9_ySMbC0aCPpwQ6mb72Xa2vxgopFf090kCmTrNXY,230
 siliconcompiler/libs/gf180mcu.py,sha256=ZX3dEytbvZZb7z2A0flAnpM86I9NeiUEH-_M0t4h45I,217
 siliconcompiler/libs/nangate45.py,sha256=OoEUGkzG10mcKft_qQPYGRTFmAAqF7cIxkHYbJrtbuw,222
+siliconcompiler/libs/sg13g2_stdcell.py,sha256=ZboZlNUpKcsOqYYEio2ur0Ooy0AtGy5IhDv0ftd6IxE,224
 siliconcompiler/libs/sky130hd.py,sha256=MTYh8mVLamjZB-M3u-b4ICqghU3b1H6UeXsTSOx9OYE,218
 siliconcompiler/libs/sky130io.py,sha256=xd-EO5OQIUVCObddk8tIYjz8Ks8ahYhUYA7ciLC4Ntk,218
 siliconcompiler/pdks/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/pdks/asap7.py,sha256=WbH4UETdDtDRUYsB39wv-gf5rCd0OgnqSlnBwwTY03E,203
 siliconcompiler/pdks/freepdk45.py,sha256=ynxretkAtlEJ8N_maz6FJ3L8P5Tlffc1gAsxqtg-kE4,207
 siliconcompiler/pdks/gf180.py,sha256=yT_tQmfXTMuU-NngX1lakxPXVxZxwdl_FwNP-Rxx2rU,203
+siliconcompiler/pdks/ihp130.py,sha256=grtX2Z2nQiQqtXGwkYcux3CrUM7EZp18F-s_yLxW0J4,204
 siliconcompiler/pdks/skywater130.py,sha256=6UxJaWDQfs180tbKAfhLT2jfO6yTa41cdFrBKxCfniU,204
 siliconcompiler/remote/__init__.py,sha256=2tRoHeocMaOltgsablWrX31KESPgP3In0oEJvaZDEY8,810
 siliconcompiler/remote/client.py,sha256=BHhnCMEDTeaT1ZezavWE0hJSmHjSSjMlDxcQxfiUCHM,30920
@@ -86,7 +88,7 @@ siliconcompiler/scheduler/slurm.py,sha256=CAuN5xmiWhk_k3CW6yMe5iukex4CWxp5Ox6_qA
 siliconcompiler/scheduler/validation/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/scheduler/validation/email_credentials.json,sha256=m141zzx3DxBt_Qztr9_Ej_-kYMP1tUc2Xj2YW_a3Pu0,1746
 siliconcompiler/schema/__init__.py,sha256=Gdny2AwDdg-X3RvghOHQYl3aG2alvMuK5CsSkFGKuYU,120
-siliconcompiler/schema/schema_cfg.py,sha256=ybDp8auEYof63Q-yuvzY1SLG7NUo1mHTHKTJlf7I2tE,182992
+siliconcompiler/schema/schema_cfg.py,sha256=Pn96dZ7QYcJG-wokZ-UO4BeyTh_qdZhSl35DSGl5Tv8,182998
 siliconcompiler/schema/schema_obj.py,sha256=uIufKDsfoTe9m8EY4-PVMUKb_dbJ4-_x89v4yRs5mkQ,73447
 siliconcompiler/schema/utils.py,sha256=V8xDBpQ3gIiEpuzme15h7xEz601uGi8tNi0QyK175qk,4018
 siliconcompiler/sphinx_ext/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
@@ -99,6 +101,7 @@ siliconcompiler/targets/asic_demo.py,sha256=jRvbDhMZDGf-8AQ241vu8qLgloxPUToAn01Y
 siliconcompiler/targets/fpgaflow_demo.py,sha256=-2L8Xi-TIB5FBuIxxB88Y9JagTTOXDHZcNFFwPU-sno,1379
 siliconcompiler/targets/freepdk45_demo.py,sha256=O983Nwrs9h_HHlHtlUUrP0cPgdf3IlME1yWXCRgdL_A,1953
 siliconcompiler/targets/gf180_demo.py,sha256=oTs07GFFyQT0LaE7jVdoLSBuGqpOGLyL-ThQ25ZpCkc,3075
+siliconcompiler/targets/ihp130_demo.py,sha256=3nCxfM0-XpZWjhE1yQezZKBGJwtf6AjpeinPM4z6wv0,2688
 siliconcompiler/targets/skywater130_demo.py,sha256=ct-kdVuZm2idynFm8eEZlL2S4-rfzWe16in8lOZPqrU,2689
 siliconcompiler/templates/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/templates/email/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
@@ -187,8 +190,6 @@ siliconcompiler/tools/netgen/sc_lvs.tcl,sha256=EKDVaYZZMi__ga-t8x-SWEyDG9Zat0wyZ
 siliconcompiler/tools/nextpnr/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/nextpnr/apr.py,sha256=dCMLDS4xnwqCoBtCKd3kwCxjIRqPn_zq3f7pkWPw5mw,802
 siliconcompiler/tools/nextpnr/nextpnr.py,sha256=B5kr-ZLnt2vDFtS4veIdf0_Cm6yvfS1QVqWhxYa8R24,1712
-siliconcompiler/tools/openfpgaloader/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
-siliconcompiler/tools/openfpgaloader/openfpgaloader.py,sha256=yeHIzKxsshAsR6Yhz7haxqev6BfGKB4CzvKyN0pSneM,1209
 siliconcompiler/tools/openroad/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/openroad/cts.py,sha256=CZz_eJxCyuMpA7bvQaDm6dYgOkUM9phNKD1aNcJKJgE,1080
 siliconcompiler/tools/openroad/dfm.py,sha256=RjdOqq7oPVSx5HzYUTSlBh4ZGnVfJqJHR0cs4WdG1pQ,2244
@@ -207,11 +208,11 @@ siliconcompiler/tools/openroad/scripts/sc_apr.tcl,sha256=wlVYGDyl0PmR9bV15pMDLGu
 siliconcompiler/tools/openroad/scripts/sc_cts.tcl,sha256=PAUk66gHgvnXc78SDrUqczX5Q7c0SPo48Vm5FXYvczM,1793
 siliconcompiler/tools/openroad/scripts/sc_dfm.tcl,sha256=vhIUebTDyDtg7mnwDzUgMmdKZd5NmgG68wQBj1P34Pg,587
 siliconcompiler/tools/openroad/scripts/sc_export.tcl,sha256=-r3WUFON7gMgXxcJUL_uGBp_-wi46h1hAMKlRWtOzWg,2830
-siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl,sha256=fC_0RcpYdJe6vcVrbcFnCiO4cjRTu9OAzK5wm8m7icE,11690
+siliconcompiler/tools/openroad/scripts/sc_floorplan.tcl,sha256=SArhDchIlL1VbWnzS0FNFvbz-st2QRhwlQFfW-ufhKI,11546
 siliconcompiler/tools/openroad/scripts/sc_metrics.tcl,sha256=sactbdEYt8i4Pn_g29BLEGm7hIFzWc_Uw1PfI7hGbxo,5181
 siliconcompiler/tools/openroad/scripts/sc_physyn.tcl,sha256=hLAVeE_a__ZBgVMOSmMwCwtTDfflZptPmphaqibYvEk,115
 siliconcompiler/tools/openroad/scripts/sc_place.tcl,sha256=WMuYB-LXQP8YdcYMHTkqGzOvn1bK6X7mOm12gEK4kKY,1937
-siliconcompiler/tools/openroad/scripts/sc_procs.tcl,sha256=nIYiWU6Uyk_4bENiZkEE69TGxySyu317lyoARSeCW5o,10876
+siliconcompiler/tools/openroad/scripts/sc_procs.tcl,sha256=nQcaGX1sQjYdW5SKVB2jtuVvRPyfJcNxqNMofIcWrDI,11530
 siliconcompiler/tools/openroad/scripts/sc_rcx.tcl,sha256=-70AuNikbsoHd_bW-myc8QMbmJNFSK-DqKIN_HF0luc,1514
 siliconcompiler/tools/openroad/scripts/sc_rcx_bench.tcl,sha256=d_VgTJA4hwRiaJVTTBOl1LxfJ3KB7fHJjmj8eTm1GRs,682
 siliconcompiler/tools/openroad/scripts/sc_rcx_extract.tcl,sha256=Aj9J_8aiOR1WqcQvdx99WyUDcN8RafxXwtrexcS5UcU,489
@@ -264,8 +265,10 @@ siliconcompiler/tools/vpr/route.py,sha256=uD4A2fSahluRhSJayjW1rfXt9pI3wWAbLIRU_Y
 siliconcompiler/tools/vpr/screenshot.py,sha256=5Ji6J9p0R0C7C9WkuCwLu2InGQpeCo_Ciif7wUXz9ng,1818
 siliconcompiler/tools/vpr/show.py,sha256=Dm0efQaOa2G6FsDeo6BpNYEp0farqKQOXeF_JLBuSYo,3120
 siliconcompiler/tools/vpr/vpr.py,sha256=3FZpwuh-FtatXt9qd7qRb6ALZe8P8AFJDoMvV_kunp0,13600
-siliconcompiler/tools/xyce/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
-siliconcompiler/tools/xyce/xyce.py,sha256=4WGNOpy6wLGu4fjSFRfvhRdQApnYkrbjK9tFfsfP-Hc,1082
+siliconcompiler/tools/xdm/__init__.py,sha256=uEo7uTPRdoARmk0E5U8yQ_MZOntO-cWJfGb6_pPA0ZQ,729
+siliconcompiler/tools/xdm/convert.py,sha256=rlirszWfNs2x9KApd3AiKpx78B3bfQ5VVWv5Nk_LSuU,2371
+siliconcompiler/tools/xyce/__init__.py,sha256=FV1MEcqT_NqnHaR15zXM0zDtEorg6Amma6SHqxHujJo,1279
+siliconcompiler/tools/xyce/simulate.py,sha256=Af4FcwLQrrlzsyCmMg9M_ZvpabWnLFrFYnitHNpBpkc,2900
 siliconcompiler/tools/yosys/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/yosys/lec.py,sha256=VD7FAIzvwZOsMViA0Nd9f3sY2a7kkE2BobfewkflwKQ,1906
 siliconcompiler/tools/yosys/prepareLib.py,sha256=9FbbAKhegY9Gwvgw9VnC0Rrl4tOCrNF0rZnUrOxJGNg,2267
@@ -285,9 +288,9 @@ siliconcompiler/tools/yosys/templates/abc.const,sha256=TAq9ThdLMYCJGrtToEU0gWcLu
 siliconcompiler/utils/__init__.py,sha256=Gu92RwiPZ8xrdsTUYVKp9TuNJGrU-5UvOuixPugzLww,13122
 siliconcompiler/utils/asic.py,sha256=cMLs7dneSmh5BlHS0-bZ1tLUpvghTw__gNaUCMpyBds,4986
 siliconcompiler/utils/showtools.py,sha256=sMZeHm3CpB4lH-MEeZfNSPYedmnokijTiAHmFDgbtsI,1133
-siliconcompiler-0.28.0.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
-siliconcompiler-0.28.0.dist-info/METADATA,sha256=CfWGG-LmWc3ePjf43oTyuu7snmPDRzBcM_-FSzqV6bM,9726
-siliconcompiler-0.28.0.dist-info/WHEEL,sha256=GV9aMThwP_4oNCtvEC2ec3qUYutgWeAzklro_0m4WJQ,91
-siliconcompiler-0.28.0.dist-info/entry_points.txt,sha256=M3cpZxvqanXhVU9CuLTRDzBdDKmKz-t0p4DT57TyysU,451
-siliconcompiler-0.28.0.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
-siliconcompiler-0.28.0.dist-info/RECORD,,
+siliconcompiler-0.28.1.dist-info/LICENSE,sha256=lbLR6sRo_CYJOf7SVgHi-U6CZdD8esESEZE5TZazOQE,10766
+siliconcompiler-0.28.1.dist-info/METADATA,sha256=MYsUWwDCrdU1RABFBlbajEG3SAj6PXMcnHaVudzQpzc,9734
+siliconcompiler-0.28.1.dist-info/WHEEL,sha256=GV9aMThwP_4oNCtvEC2ec3qUYutgWeAzklro_0m4WJQ,91
+siliconcompiler-0.28.1.dist-info/entry_points.txt,sha256=M3cpZxvqanXhVU9CuLTRDzBdDKmKz-t0p4DT57TyysU,451
+siliconcompiler-0.28.1.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
+siliconcompiler-0.28.1.dist-info/RECORD,,

siliconcompiler/tools/openfpgaloader/openfpgaloader.py

@@ -1,39 +0,0 @@
-'''
-The OpenFPGALoader is a universal utility for programming
-FPGAs. Compatible with many boards, cables and FPGA from
-major manufacturers (Xilinx, Altera/Intel, Lattice, Gowin,
-Efinix, Anlogic). openFPGALoader works on Linux, Windows and
-macOS.
-
-Documentation: https://github.com/trabucayre/openFPGALoader
-
-Sources: https://github.com/trabucayre/openFPGALoader
-
-Installation: https://github.com/trabucayre/openFPGALoader
-
-Status: SC integration WIP
-'''
-from siliconcompiler.tools._common import get_tool_task
-
-
-################################
-# Setup Tool (pre executable)
-################################
-def setup(chip):
-    ''' openFPGALoader setup function
-    '''
-
-    # If the 'lock' bit is set, don't reconfigure.
-    tool = 'openfpgaloader'
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
-
-    # tool setup
-    chip.set('tool', tool, 'exe', tool)
-    chip.set('tool', tool, 'vswitch', '--Version', clobber=False)
-    chip.set('tool', tool, 'version', '0.5.0', clobber=False)
-
-    options = []
-    options.append("inputs" + chip.top() + ".bit")
-    chip.add('tool', tool, 'task', task, 'option', options, step=step, index=index)

siliconcompiler/tools/xyce/xyce.py

@@ -1,36 +0,0 @@
-'''
-Xyce is a high performance SPICE-compatible circuit simulator
-capable capable of solving extremely large circuit problems by
-supporting large-scale parallel computing platforms. It also
-supports serial execution on all common desktop platforms,
-and small-scale parallel runs on Unix-like systems.
-
-Documentation: https://xyce.sandia.gov/documentation-tutorials/
-
-Sources: https://github.com/Xyce/Xyce
-
-Installation: https://xyce.sandia.gov/documentation-tutorials/building-guide/
-
-Status: SC integration WIP
-'''
-
-import os
-from siliconcompiler.tools._common import get_tool_task
-
-
-################################
-# Setup Tool (pre executable)
-################################
-def setup(chip):
-
-    tool = 'xyce'
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
-
-    clobber = False
-
-    chip.set('tool', tool, 'exe', tool)
-    chip.set('tool', tool, 'version', '0.0', clobber=clobber)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
-             step=step, index=index, clobber=clobber)