siliconcompiler 0.27.0__py3-none-any.whl → 0.28.0__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/sc_procs.tcl

@@ -19,8 +19,10 @@ proc sc_global_placement_density {} {
   # User specified adjustment
   if { $openroad_gpl_uniform_placement_adjustment > 0.0 } {
     set or_uniform_adjusted_density \
-      [expr { $or_uniform_density + ((1.0 - $or_uniform_density) * \
-              $openroad_gpl_uniform_placement_adjustment) + $or_adjust_density_adder }]
+      [expr {
+        $or_uniform_density + ((1.0 - $or_uniform_density) *
+          $openroad_gpl_uniform_placement_adjustment) + $or_adjust_density_adder
+      }]
     if { $or_uniform_adjusted_density > 1.00 } {
       utl::warn FLW 1 "Adjusted density exceeds 1.00 ([format %0.3f $or_uniform_adjusted_density]),\
         reverting to use ($openroad_gpl_place_density) for global placement"
@@ -56,8 +58,10 @@ proc sc_global_placement { args } {
   global openroad_gpl_padding
 
   set openroad_gpl_args []
-  if { $openroad_gpl_routability_driven == "true" && \
-       ![info exists flags(-disable_routability_driven)] } {
+  if {
+    $openroad_gpl_routability_driven == "true" &&
+    ![info exists flags(-disable_routability_driven)]
+  } {
     lappend openroad_gpl_args "-routability_driven"
   }
   if { $openroad_gpl_timing_driven == "true" } {
@@ -235,8 +239,10 @@ proc sc_design_has_unplaced_pads {} {
 
 proc sc_design_has_placeable_ios {} {
   foreach bterm [[ord::get_db_block] getBTerms] {
-    if { [$bterm getFirstPinPlacementStatus] != "FIXED" &&
-         [$bterm getFirstPinPlacementStatus] != "LOCKED" } {
+    if {
+      [$bterm getFirstPinPlacementStatus] != "FIXED" &&
+      [$bterm getFirstPinPlacementStatus] != "LOCKED"
+    } {
       return true
     }
   }

siliconcompiler/tools/openroad/scripts/sc_rcx.tcl

@@ -9,7 +9,7 @@ source ./sc_manifest.tcl > /dev/null
 ###############################
 
 proc sc_get_layer_name { name } {
-  if { [ string is integer $name ] } {
+  if { [string is integer $name] } {
     set layer [[ord::get_db_tech] findRoutingLayer $name]
     if { $layer == "NULL" } {
       utl::error FLW 1 "$name is not a valid routing layer."
@@ -23,18 +23,18 @@ proc sc_get_layer_name { name } {
 # Schema Adapter
 ###############################
 
-set sc_tool   openroad
-set sc_step   [sc_cfg_get arg step]
-set sc_index  [sc_cfg_get arg index]
-set sc_flow   [sc_cfg_get option flow]
-set sc_task   [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_tool openroad
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
 
 # Design
-set sc_design     [sc_top]
-set sc_pdk        [sc_cfg_get option pdk]
-set sc_stackup    [sc_cfg_get option stackup]
+set sc_design [sc_top]
+set sc_pdk [sc_cfg_get option pdk]
+set sc_stackup [sc_cfg_get option stackup]
 
 # Library
 set sc_libtype [lindex [sc_cfg_tool_task_get {var} libtype] 0]

siliconcompiler/tools/openroad/scripts/sc_route.tcl

@@ -71,10 +71,14 @@ global_route -guide_file "./route.guide" \
 ######################
 
 estimate_parasitics -global_routing
-if { $openroad_ant_check == "true" && \
-     [check_antennas -report_file "reports/${sc_design}_antenna.rpt"] != 0 } {
-  if { $openroad_ant_repair == "true" && \
-       [llength [sc_cfg_get library $sc_mainlib asic cells antenna]] != 0 } {
+if {
+  $openroad_ant_check == "true" &&
+  [check_antennas -report_file "reports/${sc_design}_antenna.rpt"] != 0
+} {
+  if {
+    $openroad_ant_repair == "true" &&
+    [llength [sc_cfg_get library $sc_mainlib asic cells antenna]] != 0
+  } {
     set sc_antenna [lindex [sc_cfg_get library $sc_mainlib asic cells antenna] 0]
 
     # Remove filler cells before attempting to repair antennas

siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl

@@ -14,8 +14,10 @@ sc_save_image "screenshot" "outputs/${sc_design}.png" $sc_resolution
 
 gui::restore_display_controls
 
-if { [sc_cfg_tool_task_exists {var} include_report_images] &&
-     [lindex [sc_cfg_tool_task_get {var} include_report_images] 0]
-     == "true" } {
+if {
+  [sc_cfg_tool_task_exists {var} include_report_images] &&
+  [lindex [sc_cfg_tool_task_get {var} include_report_images] 0]
+  == "true"
+} {
   source -echo "${sc_refdir}/sc_write_images.tcl"
 }

siliconcompiler/tools/openroad/scripts/sc_write_images.tcl

@@ -156,12 +156,13 @@ proc sc_image_estimated_routing_congestion {} {
   sc_image_setup_default
 
   suppress_message GRT 10
-  catch { \
+  catch {
     sc_image_heatmap "Estimated Congestion (RUDY)" \
       "RUDY" \
       "estimated_routing_congestion.png" \
       "estimated routing congestion" \
-      0 } err
+      0
+  } err
   unsuppress_message GRT 10
 }
 
@@ -271,30 +272,31 @@ proc sc_image_optimizer {} {
   gui::set_display_controls "Instances/*" visible true
   gui::set_display_controls "Instances/Physical/*" visible false
 
-  set hold_count       [select -name "hold*" -type Inst -highlight 0]       ;# green
-  set input_count      [select -name "input*" -type Inst -highlight 1]      ;# yellow
-  set output_count     [select -name "output*" -type Inst -highlight 1]
-  set repeater_count   [select -name "repeater*" -type Inst -highlight 3]   ;# magenta
-  set fanout_count     [select -name "fanout*" -type Inst -highlight 3]
-  set load_slew_count  [select -name "load_slew*" -type Inst -highlight 3]
-  set max_cap_count    [select -name "max_cap*" -type Inst -highlight 3]
+  set hold_count [select -name "hold*" -type Inst -highlight 0] ;# green
+  set input_count [select -name "input*" -type Inst -highlight 1] ;# yellow
+  set output_count [select -name "output*" -type Inst -highlight 1]
+  set repeater_count [select -name "repeater*" -type Inst -highlight 3] ;# magenta
+  set fanout_count [select -name "fanout*" -type Inst -highlight 3]
+  set load_slew_count [select -name "load_slew*" -type Inst -highlight 3]
+  set max_cap_count [select -name "max_cap*" -type Inst -highlight 3]
   set max_length_count [select -name "max_length*" -type Inst -highlight 3]
-  set wire_count       [select -name "wire*" -type Inst -highlight 3]
-  set rebuffer_count   [select -name "rebuffer*" -type Inst -highlight 4]   ;# red
-  set split_count      [select -name "split*" -type Inst -highlight 5]      ;# dark green
-
-  set select_count [expr { \
-    $hold_count + \
-    $input_count + \
-    $output_count + \
-    $repeater_count + \
-    $fanout_count + \
-    $load_slew_count + \
-    $max_cap_count + \
-    $max_length_count + \
-    $wire_count + \
-    $rebuffer_count + \
-    $split_count }]
+  set wire_count [select -name "wire*" -type Inst -highlight 3]
+  set rebuffer_count [select -name "rebuffer*" -type Inst -highlight 4] ;# red
+  set split_count [select -name "split*" -type Inst -highlight 5] ;# dark green
+
+  set select_count [expr {
+    $hold_count +
+    $input_count +
+    $output_count +
+    $repeater_count +
+    $fanout_count +
+    $load_slew_count +
+    $max_cap_count +
+    $max_length_count +
+    $wire_count +
+    $rebuffer_count +
+    $split_count
+  }]
 
   if { $select_count == 0 } {
     # Nothing selected

siliconcompiler/tools/opensta/scripts/sc_procs.tcl

@@ -1,4 +1,3 @@
-
 ###########################
 # Count the logic depth of the critical path
 ###########################

siliconcompiler/tools/verilator/compile.py

@@ -8,9 +8,6 @@ def setup(chip):
     Compiles Verilog and C/C++ sources into an executable. In addition to the
     standard RTL inputs, this task reads C/C++ sources from :keypath:`input,
     hll, c`.  Outputs an executable in ``outputs/<design>.vexe``.
-
-    This task supports using the :keypath:`option, trace` parameter to enable
-    Verilator's ``--trace`` flag.
     '''
 
     # Generic tool setup.
@@ -69,7 +66,7 @@ def setup(chip):
              "if true, enables trace generation.",
              field='help')
     chip.set('tool', tool, 'task', task, 'var', 'trace_type',
-             "specifies type of wave file to create when [option, trace] is set. Valid options are "
+             "specifies type of wave file to create when [trace] is set. Valid options are "
              "'vcd' or 'fst'. Defaults to 'vcd'.",
              field='help')
 

siliconcompiler/tools/verilator/verilator.py

@@ -14,8 +14,7 @@ exist, through the following keypaths:
     * :keypath:`option, idir`
 
 For all tasks, this driver runs Verilator using the ``-sv`` switch to enable
-parsing a subset of SystemVerilog features. All tasks also support using
-:keypath:`option, relax` to make warnings nonfatal.
+parsing a subset of SystemVerilog features.
 
 Documentation: https://verilator.org/guide/latest
 

siliconcompiler/tools/vivado/scripts/sc_run.tcl

@@ -1,4 +1,3 @@
-
 ###############################
 # Reading SC Schema
 ###############################
@@ -15,13 +14,13 @@ if { [sc_cfg_exists input fpga xdc] } {
 } else {
     set sc_constraint ""
 }
-set sc_tool       "vivado"
-set sc_partname   [sc_cfg_get fpga partname]
-set sc_step       [sc_cfg_get arg step]
-set sc_index      [sc_cfg_get arg index]
-set sc_flow       [sc_cfg_get option flow]
-set sc_task       [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
-set sc_refdir     [sc_cfg_tool_task_get refdir]
+set sc_tool "vivado"
+set sc_partname [sc_cfg_get fpga partname]
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
 
 source $sc_refdir/sc_$sc_task.tcl
 

siliconcompiler/tools/vivado/vivado.py

@@ -2,7 +2,7 @@
 Vivado is an FPGA programming tool suite from Xilinx used to
 program Xilinx devices.
 
-Documentation: https://www.xilinx.com/products/design-tools/vivado.html
+Documentation: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/vivado.html
 '''
 
 import json

siliconcompiler/tools/vpr/place.py

@@ -31,6 +31,9 @@ def setup(chip, clobber=True):
     chip.add('tool', tool, 'task', task, 'output', design + '.net', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.place', step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'placement', 'component placement constraints',
+             field='help')
+
 
 def runtime_options(chip):
     '''Command line options to vpr for the place step
@@ -75,12 +78,13 @@ def pre_process(chip):
 
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
 
     part_name = chip.get('fpga', 'partname')
 
     # If the user explicitly provides an XML constraints file, give that
     # priority over other constraints input types:
-    if 'vpr_pins' in chip.getkeys('input', 'constraint'):
+    if chip.valid('input', 'constraint', 'vpr_pins'):
         constraint_file = vpr.find_single_file(chip, 'input', 'constraint', 'vpr_pins',
                                                step=step, index=index,
                                                file_not_found_msg="VPR constraints file not found")
@@ -88,7 +92,7 @@ def pre_process(chip):
         if (constraint_file is not None):
             shutil.copy2(constraint_file, vpr.auto_constraints())
 
-    elif 'pcf' in chip.getkeys('input', 'constraint'):
+    elif chip.valid('input', 'constraint', 'pcf'):
         constraint_file = vpr.find_single_file(chip, 'input', 'constraint', 'pcf',
                                                step=step, index=index,
                                                file_not_found_msg="PCF constraints file not found")
@@ -111,11 +115,13 @@ def pre_process(chip):
         generate_vpr_constraints_xml_file(all_place_constraints, vpr.auto_constraints())
 
     else:
-        all_component_constraints = chip.getkeys('constraint', 'component')
+        all_component_constraints = chip.get('tool', tool, 'task', task, 'var', 'placement',
+                                             step=step, index=index)
+
         all_place_constraints = {}
-        for component in all_component_constraints:
-            place_constraint = chip.get('constraint', 'component', component, 'placement',
-                                        step=step, index=index)
+        for constraint in all_component_constraints:
+            component, *place_constraint = constraint.split(",")
+            place_constraint = tuple([int(loc) for loc in place_constraint])
             chip.logger.info(f'Place constraint for {component} at {place_constraint}')
             all_place_constraints[component] = place_constraint
 
@@ -123,6 +129,14 @@ def pre_process(chip):
             generate_vpr_constraints_xml_file(all_place_constraints, vpr.auto_constraints())
 
 
+def add_placement_constraint(chip, component, location, step=None, index=None):
+    tool = 'vpr'
+    task = 'place'
+
+    constraint = f"{component},{','.join([str(loc) for loc in location])}"
+
+    chip.add('tool', tool, 'task', task, 'var', 'placement', constraint, step=step, index=index)
+
 ################################
 # Post_process (post executable)
 ################################

siliconcompiler/tools/vpr/vpr.py

@@ -134,7 +134,7 @@ def runtime_options(chip):
                 'vpr_clock model must be set to ideal, route, or dedicated_clock_network',
                 chip=chip)
 
-    if 'sdc' in chip.getkeys('input', 'constraint'):
+    if chip.valid('input', 'constraint', 'sdc'):
         sdc_file = find_single_file(chip, 'input', 'constraint', 'sdc',
                                     step=step, index=index,
                                     file_not_found_msg="SDC file not found")

siliconcompiler/tools/yosys/sc_lec.tcl

@@ -6,14 +6,14 @@ set sc_tool yosys
 yosys echo on
 
 #Handling remote/local script execution
-set sc_step   [sc_cfg_get arg step]
-set sc_index  [sc_cfg_get arg index]
-set sc_flow   [sc_cfg_get option flow]
-set sc_task   [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
-set sc_refdir [sc_cfg_tool_task_get refdir ]
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
 
-set sc_design      [sc_top]
-set sc_targetlibs  [sc_get_asic_libraries logic]
+set sc_design [sc_top]
+set sc_targetlibs [sc_get_asic_libraries logic]
 
 # TODO: properly handle complexity here
 set lib [lindex $sc_targetlibs 0]

siliconcompiler/tools/yosys/sc_syn.tcl

@@ -10,21 +10,21 @@ yosys echo on
 # Schema Adapter
 ###############################
 
-set sc_tool   yosys
-set sc_step   [sc_cfg_get arg step]
-set sc_index  [sc_cfg_get arg index]
-set sc_flow   [sc_cfg_get option flow]
-set sc_task   [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
 set sc_refdir [sc_cfg_tool_task_get refdir]
 
 ####################
 # DESIGNER's CHOICE
 ####################
 
-set sc_design      [sc_top]
-set sc_flow        [sc_cfg_get option flow]
-set sc_optmode     [sc_cfg_get option optmode]
-set sc_pdk         [sc_cfg_get option pdk]
+set sc_design [sc_top]
+set sc_flow [sc_cfg_get option flow]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
 
 ########################################################
 # Design Inputs

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -82,8 +82,8 @@ proc determine_keep_hierarchy { iter cell_limit } {
 # DESIGNER's CHOICE
 ####################
 
-set sc_logiclibs        [sc_get_asic_libraries logic]
-set sc_macrolibs        [sc_get_asic_libraries macro]
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_macrolibs [sc_get_asic_libraries macro]
 
 set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
 if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
@@ -127,8 +127,10 @@ proc has_tie_cell { type } {
     upvar sc_mainlib sc_mainlib
     upvar sc_tool sc_tool
 
-    return [expr { [sc_cfg_exists library $sc_mainlib option {var} yosys_tie${type}_cell] && \
-                   [sc_cfg_exists library $sc_mainlib option {var} yosys_tie${type}_port] }]
+    return [expr {
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_tie${type}_cell] &&
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_tie${type}_port]
+    }]
 }
 
 proc get_tie_cell { type } {
@@ -149,9 +151,11 @@ proc has_buffer_cell { } {
     upvar sc_mainlib sc_mainlib
     upvar sc_tool sc_tool
 
-    return [expr { [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_cell] && \
-                   [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_input] && \
-                   [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_output] }]
+    return [expr {
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_cell] &&
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_input] &&
+        [sc_cfg_exists library $sc_mainlib option {var} yosys_buffer_output]
+    }]
 }
 
 proc get_buffer_cell { } {
@@ -160,8 +164,8 @@ proc get_buffer_cell { } {
     upvar sc_tool sc_tool
 
     set cell [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_cell] 0]
-    set in   [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_input] 0]
-    set out  [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_output] 0]
+    set in [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_input] 0]
+    set out [lindex [sc_cfg_get library $sc_mainlib option {var} yosys_buffer_output] 0]
 
     return "$cell $in $out"
 }
@@ -207,8 +211,10 @@ yosys hierarchy -top $sc_design
 # Mark modules to keep from getting removed in flattening
 preserve_modules
 
-set flatten_design [expr { [lindex [sc_cfg_tool_task_get var flatten] 0] \
-    == "true" }]
+set flatten_design [expr {
+    [lindex [sc_cfg_tool_task_get var flatten] 0]
+    == "true"
+}]
 set synth_args []
 if { $flatten_design } {
     lappend synth_args "-flatten"
@@ -359,8 +365,10 @@ if { [llength $yosys_hilomap_args] != 0 } {
     yosys hilomap -singleton {*}$yosys_hilomap_args
 }
 
-if { [has_buffer_cell] && \
-     [sc_cfg_tool_task_get var add_buffers] == "true" } {
+if {
+    [has_buffer_cell] &&
+    [sc_cfg_tool_task_get var add_buffers] == "true"
+} {
     yosys insbuf -buf {*}[get_buffer_cell]
 }
 

siliconcompiler/tools/yosys/syn_fpga.tcl

@@ -1,27 +1,31 @@
-
 source "$sc_refdir/syn_asic_fpga_shared.tcl"
 
 proc legalize_flops { feature_set } {
-
     set legalize_flop_types []
 
-    if { [lsearch -exact $feature_set enable] >= 0 && \
-         [lsearch -exact $feature_set async_set] >= 0 && \
-         [lsearch -exact $feature_set async_reset] >= 0 } {
+    if {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_set] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
         lappend legalize_flop_types \$_DFF_P_
         lappend legalize_flop_types \$_DFF_PN?_
         lappend legalize_flop_types \$_DFFE_PP_
         lappend legalize_flop_types \$_DFFE_PN?P_
         lappend legalize_flop_types \$_DFFSR_PNN_
         lappend legalize_flop_types \$_DFFSRE_PNNP_
-    } elseif { [lsearch -exact $feature_set enable] >= 0 && \
-               [lsearch -exact $feature_set async_set] >= 0 } {
+    } elseif {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_set] >= 0
+    } {
         lappend legalize_flop_types \$_DFF_P_
         lappend legalize_flop_types \$_DFF_PN1_
         lappend legalize_flop_types \$_DFFE_PP_
         lappend legalize_flop_types \$_DFFE_PN1P_
-    } elseif { [lsearch -exact $feature_set enable] >= 0 && \
-               [lsearch -exact $feature_set async_reset] >= 0 } {
+    } elseif {
+        [lsearch -exact $feature_set enable] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
         lappend legalize_flop_types \$_DFF_P_
         lappend legalize_flop_types \$_DFF_PN0_
         lappend legalize_flop_types \$_DFFE_PP_
@@ -31,8 +35,10 @@ proc legalize_flops { feature_set } {
         lappend legalize_flop_types \$_DFF_P??_
         lappend legalize_flop_types \$_DFFE_PP_
         lappend legalize_flop_types \$_DFFE_P??P_
-    } elseif { [lsearch -exact $feature_set async_set] >= 0 && \
-               [lsearch -exact $feature_set async_reset] >= 0 } {
+    } elseif {
+        [lsearch -exact $feature_set async_set] >= 0 &&
+        [lsearch -exact $feature_set async_reset] >= 0
+    } {
         lappend legalize_flop_types \$_DFF_P_
         lappend legalize_flop_types \$_DFF_PN?_
         lappend legalize_flop_types \$_DFFSR_PNN_
@@ -59,8 +65,7 @@ proc legalize_flops { feature_set } {
 }
 
 proc get_dsp_options { sc_syn_dsp_options } {
-
-    set option_text [ list ]
+    set option_text [list]
     foreach dsp_option $sc_syn_dsp_options {
         lappend option_text -D $dsp_option
     }
@@ -80,7 +85,7 @@ if { [sc_cfg_exists fpga $sc_partname var feature_set] } {
     set sc_syn_feature_set \
         [sc_cfg_get fpga $sc_partname var feature_set]
 } else {
-    set sc_syn_feature_set [ list ]
+    set sc_syn_feature_set [list]
 }
 
 if { [sc_cfg_exists fpga $sc_partname var yosys_dsp_options] } {
@@ -89,7 +94,7 @@ if { [sc_cfg_exists fpga $sc_partname var yosys_dsp_options] } {
         [sc_cfg_get fpga $sc_partname var yosys_dsp_options]
     yosys log "Yosys DSP techmap options = $sc_syn_dsp_options"
 } else {
-    set sc_syn_dsp_options [ list ]
+    set sc_syn_dsp_options [list]
 }
 
 # TODO: add logic that remaps yosys built in name based on part number
@@ -101,13 +106,11 @@ yosys hierarchy -top $sc_design
 if { [string match {ice*} $sc_partname] } {
     yosys synth_ice40 -top $sc_design -json "${sc_design}.netlist.json"
 } else {
-
     # Pre-processing step:  if DSPs instance are hard-coded into
     # the user's design, we can use a blackbox flow for DSP mapping
     # as follows:
 
     if { [sc_cfg_exists fpga $sc_partname file yosys_macrolib] } {
-
         set sc_syn_macrolibs \
             [sc_cfg_get fpga $sc_partname file yosys_macrolib]
 

siliconcompiler/use.py

@@ -12,7 +12,8 @@ class PackageChip(Chip):
         super().__init__(name)
 
         if len(args) == 2:
-            self.logger.warning(f'passing Chip object to {type(self)} is deprecated')
+            self.logger.warning(
+                f'passing Chip object to {name} ({type(self).__name__}) is deprecated')
 
         path = None
         ref = None

{siliconcompiler-0.27.0.dist-info → siliconcompiler-0.28.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.27.0
+Version: 0.28.0
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -23,7 +23,7 @@ Requires-Dist: packaging <24,>=21.3
 Requires-Dist: psutil >=5.8.0
 Requires-Dist: Pillow ==10.4.0
 Requires-Dist: GitPython ==3.1.43
-Requires-Dist: lambdapdk >=0.1.25
+Requires-Dist: lambdapdk >=0.1.31
 Requires-Dist: PyGithub ==2.4.0
 Requires-Dist: urllib3 >=1.26.0
 Requires-Dist: fasteners ==0.19
@@ -31,7 +31,7 @@ Requires-Dist: fastjsonschema ==2.20.0
 Requires-Dist: docker ==7.1.0
 Requires-Dist: sc-surelog ==1.84.1
 Requires-Dist: orjson ==3.10.7
-Requires-Dist: streamlit ==1.37.1
+Requires-Dist: streamlit ==1.38.0
 Requires-Dist: streamlit-agraph ==0.0.45
 Requires-Dist: streamlit-tree-select ==0.0.5
 Requires-Dist: streamlit-javascript ==0.1.5
@@ -43,21 +43,22 @@ Requires-Dist: pydata-sphinx-theme ==0.15.4 ; extra == 'docs'
 Requires-Dist: sc-leflib >=0.2.0 ; extra == 'docs'
 Provides-Extra: examples
 Requires-Dist: migen ==0.9.2 ; extra == 'examples'
-Requires-Dist: lambdalib ==0.2.9 ; extra == 'examples'
+Requires-Dist: lambdalib ==0.2.10 ; extra == 'examples'
 Provides-Extra: profile
 Requires-Dist: gprof2dot ==2024.6.6 ; extra == 'profile'
 Provides-Extra: test
-Requires-Dist: pytest ==8.3.2 ; extra == 'test'
+Requires-Dist: pytest ==8.3.3 ; extra == 'test'
 Requires-Dist: pytest-xdist ==3.6.1 ; extra == 'test'
 Requires-Dist: pytest-timeout ==2.3.1 ; extra == 'test'
 Requires-Dist: pytest-asyncio ==0.24.0 ; extra == 'test'
 Requires-Dist: pytest-cov ==5.0.0 ; extra == 'test'
+Requires-Dist: responses ==0.25.3 ; extra == 'test'
 Requires-Dist: PyVirtualDisplay ==3.0 ; extra == 'test'
 Requires-Dist: flake8 ==7.1.1 ; extra == 'test'
-Requires-Dist: tclint ==0.3.2 ; extra == 'test'
+Requires-Dist: tclint ==0.4.0 ; extra == 'test'
 Requires-Dist: codespell ==2.3.0 ; extra == 'test'
 
-![SiliconCompiler](https://raw.githubusercontent.com/siliconcompiler/siliconcompiler/main/docs/_images/sc_logo_with_text.png)
+![SiliconCompiler](https://raw.githubusercontent.com/siliconcompiler/siliconcompiler/main/docs/_static/sc_logo_with_text.png)
 
 [![Python CI Tests](https://github.com/siliconcompiler/siliconcompiler/actions/workflows/python_ci.yml/badge.svg?branch=main)](https://github.com/siliconcompiler/siliconcompiler/actions/workflows/python_ci.yml)
 [![Tools CI Tests](https://github.com/siliconcompiler/siliconcompiler/actions/workflows/tools_ci.yml/badge.svg?branch=main)](https://github.com/siliconcompiler/siliconcompiler/actions/workflows/tools_ci.yml)