siliconcompiler 0.26.3__cp310-cp310-win_amd64.whl → 0.26.4.post1__cp310-cp310-win_amd64.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.26.3'
+version = '0.26.4.post1'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/core.py

@@ -15,6 +15,7 @@ import inspect
 import textwrap
 import graphviz
 import codecs
+import copy
 from siliconcompiler.remote import client
 from siliconcompiler.schema import Schema, SCHEMA_VERSION
 from siliconcompiler.schema import utils as schema_utils
@@ -234,6 +235,7 @@ class Chip:
             for future_step, future_index in nodes_to_run:
                 max_step_len = max(len(future_step), max_step_len)
                 max_index_len = max(len(future_index), max_index_len)
+            max_step_len = min(max_step_len, 20)
 
             jobname = self.get('option', 'jobname')
 
@@ -243,7 +245,7 @@ class Chip:
                 index = '-' * max(max_index_len // 4, 1)
 
             log_format.append(jobname)
-            log_format.append(f'{step: <{max_step_len}}')
+            log_format.append(f'{utils.truncate_text(step, max_step_len): <{max_step_len}}')
             log_format.append(f'{index: >{max_index_len}}')
 
         log_format.append('%(message)s')
@@ -555,7 +557,12 @@ class Chip:
 
             elif isinstance(use_module, (Library, Chip)):
                 self._loaded_modules['libs'].append(use_module.design)
-                self.__import_library(use_module.design, use_module.schema.cfg)
+                cfg = use_module.schema.cfg
+                keep_inputs = True
+                if not isinstance(use_module, Library):
+                    keep_inputs = False
+                self.__import_library(use_module.design, cfg,
+                                      keep_input=keep_inputs)
 
                 is_auto_enable = getattr(use_module, 'is_auto_enable', None)
                 if is_auto_enable:
@@ -1163,6 +1170,10 @@ class Chip:
 
         result = []
 
+        collection_dir = self._getcollectdir(jobname=job)
+        if not os.path.exists(collection_dir):
+            collection_dir = None
+
         # Special cases for various ['tool', ...] files that may be implicitly
         # under the workdir (or refdir in the case of scripts).
         # TODO: it may be cleaner to have a file resolution scope flag in schema
@@ -1191,10 +1202,8 @@ class Chip:
             search_paths = self.__convert_paths_to_posix(search_paths)
 
         for (dependency, path) in zip(dependencies, paths):
-            if not search_paths:
-                import_path = self.__find_sc_imported_file(path,
-                                                           dependency,
-                                                           self._getcollectdir(jobname=job))
+            if not search_paths and collection_dir:
+                import_path = self.__find_sc_imported_file(path, dependency, collection_dir)
                 if import_path:
                     result.append(import_path)
                     continue
@@ -1239,6 +1248,10 @@ class Chip:
         if not path:
             return None
 
+        collected_files = os.listdir(collected_dir)
+        if not collected_files:
+            return None
+
         path_paths = pathlib.PurePosixPath(path).parts
         for n in range(len(path_paths)):
             # Search through the path elements to see if any of the previous path parts
@@ -1248,7 +1261,11 @@ class Chip:
             basename = str(pathlib.PurePosixPath(*path_paths[0:n]))
             endname = str(pathlib.PurePosixPath(*path_paths[n:]))
 
-            abspath = os.path.join(collected_dir, self.__get_imported_filename(basename, package))
+            import_name = self.__get_imported_filename(basename, package)
+            if import_name not in collected_files:
+                continue
+
+            abspath = os.path.join(collected_dir, import_name)
             if endname:
                 abspath = os.path.join(abspath, endname)
             abspath = os.path.abspath(abspath)
@@ -1257,19 +1274,18 @@ class Chip:
 
         return None
 
-    ###########################################################################
-    def find_result(self, filetype, step, jobname=None, index='0'):
+    def find_node_file(self, path, step, jobname=None, index='0'):
         """
-        Returns the absolute path of a compilation result.
+        Returns the absolute path of a file from a particular node.
 
-        Utility function that returns the absolute path to a results
+        Utility function that returns the absolute path to a node
         file based on the provided arguments. The result directory
         structure is:
 
-        <dir>/<design>/<jobname>/<step>/<index>/outputs/<design>.filetype
+        <dir>/<design>/<jobname>/<step>/<index>/<path>
 
         Args:
-            filetype (str): File extension (v, def, etc)
+            path (str): Path to file inside node run directory
             step (str): Task step name ('syn', 'place', etc)
             jobname (str): Jobid directory name
             index (str): Task index
@@ -1278,23 +1294,54 @@ class Chip:
             Returns absolute path to file.
 
         Examples:
-            >>> manifest_filepath = chip.find_result('vg', 'syn')
-           Returns the absolute path to the manifest.
+            >>> manifest_filepath = chip.find_node_file('outputs/heartbeat.vg', 'syn')
+           Returns the absolute path to the gate level verilog.
         """
         if jobname is None:
             jobname = self.get('option', 'jobname')
 
         workdir = self.getworkdir(jobname, step, index)
-        design = self.top()
-        filename = f"{workdir}/outputs/{design}.{filetype}"
+        filename = f"{workdir}/{path}"
 
-        self.logger.debug("Finding result %s", filename)
+        self.logger.debug(f"Finding node file: {filename}")
 
         if os.path.exists(filename):
             return filename
         else:
             return None
 
+    ###########################################################################
+    def find_result(self, filetype, step, jobname=None, index='0'):
+        """
+        Returns the absolute path of a compilation result.
+
+        Utility function that returns the absolute path to a results
+        file based on the provided arguments. The result directory
+        structure is:
+
+        <dir>/<design>/<jobname>/<step>/<index>/outputs/<design>.filetype
+
+        Args:
+            filetype (str): File extension (v, def, etc)
+            step (str): Task step name ('syn', 'place', etc)
+            jobname (str): Jobid directory name
+            index (str): Task index
+
+        Returns:
+            Returns absolute path to file.
+
+        Examples:
+            >>> vg_filepath = chip.find_result('vg', 'syn')
+           Returns the absolute path to the gate level verilog.
+        """
+
+        design = self.top()
+        return self.find_node_file(
+            f"outputs/{design}.{filetype}",
+            step=step,
+            jobname=jobname,
+            index=index)
+
     ###########################################################################
     def __abspath(self):
         '''
@@ -1569,13 +1616,15 @@ class Chip:
         if not os.path.exists(os.path.dirname(filepath)):
             os.makedirs(os.path.dirname(filepath))
 
+        schema = self.schema
         # resolve absolute paths
         if abspath:
             schema = self.__abspath()
-        else:
-            schema = self.schema.copy()
 
         if prune:
+            if schema is self.schema:
+                schema = schema.copy()
+
             self.logger.debug('Pruning dictionary before writing file %s', filepath)
             schema.prune()
 
@@ -1798,7 +1847,7 @@ class Chip:
         return not error
 
     ###########################################################################
-    def __import_library(self, libname, libcfg, job=None, clobber=True):
+    def __import_library(self, libname, libcfg, job=None, clobber=True, keep_input=True):
         '''Helper to import library with config 'libconfig' as a library
         'libname' in current Chip object.'''
         if job:
@@ -1809,19 +1858,22 @@ class Chip:
         if 'library' in libcfg:
             for sublib_name, sublibcfg in libcfg['library'].items():
                 self.__import_library(sublib_name, sublibcfg,
-                                      job=job, clobber=clobber)
-
-            del libcfg['library']
+                                      job=job, clobber=clobber, keep_input=keep_input)
 
         if libname in cfg:
             if not clobber:
                 return
 
-        cfg[libname] = libcfg
         self.__import_data_sources(libcfg)
-
-        if 'pdk' in cfg[libname]:
-            del cfg[libname]['pdk']
+        cfg[libname] = {}
+
+        # Only keep some sections to avoid recursive bloat
+        keeps = ['asic', 'design', 'fpga', 'option', 'output', 'package']
+        if keep_input:
+            keeps.append('input')
+        for section in list(libcfg.keys()):
+            if section in keeps:
+                cfg[libname][section] = copy.deepcopy(libcfg[section])
 
     ###########################################################################
     def write_flowgraph(self, filename, flow=None,

siliconcompiler/flowgraph.py

@@ -423,7 +423,8 @@ def _get_flowgraph_information(chip, flow, io=True):
     from siliconcompiler.tools._common import input_provides, input_file_node_name
 
     # Save schema to avoid making permanent changes
-    org_schema = chip.schema.copy()
+    org_schema = chip.schema
+    chip.schema = chip.schema.copy()
 
     # Setup nodes
     node_exec_order = _get_flowgraph_execution_order(chip, flow)

siliconcompiler/flows/dvflow.py

@@ -1,6 +1,7 @@
 import siliconcompiler
 
 from siliconcompiler.tools.icarus import compile as icarus_compile
+from siliconcompiler.tools.verilator import compile as verilator_compile
 from siliconcompiler.tools.execute import exec_input
 
 
@@ -44,17 +45,21 @@ def setup(chip,
     if tool == 'icarus':
         tasks['compile'] = icarus_compile
         tasks['sim'] = exec_input
-        flowpipe = [
-            'compile',
-            'sim'
-        ]
-        flow_np = {
-            'compile': 1,
-            'sim': np
-        }
+    elif tool == 'verilator':
+        tasks['compile'] = verilator_compile
+        tasks['sim'] = exec_input
     else:
         raise ValueError(f'{tool} is not a supported tool for {flowname}: icarus')
 
+    flowpipe = [
+        'compile',
+        'sim'
+    ]
+    flow_np = {
+        'compile': 1,
+        'sim': np
+    }
+
     prevstep = None
     # Flow setup
     for step in flowpipe:

siliconcompiler/report/html_report.py

@@ -14,7 +14,7 @@ def _generate_html_report(chip, flow, flowgraph_nodes, results_html):
     '''
 
     # only report tool based steps functions
-    for (step, index) in flowgraph_nodes.copy():
+    for (step, index) in list(flowgraph_nodes):
         tool, task = get_tool_task(chip, step, '0', flow=flow)
         if tool == 'builtin':
             index = flowgraph_nodes.index((step, index))

siliconcompiler/report/summary_table.py

@@ -1,7 +1,9 @@
 import pandas
+import shutil
 
 from siliconcompiler.report.utils import _collect_data, _get_flowgraph_path
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.utils import truncate_text
 
 
 def _show_summary_table(chip, flow, flowgraph_nodes, show_all_indices):
@@ -10,9 +12,10 @@ def _show_summary_table(chip, flow, flowgraph_nodes, show_all_indices):
     '''
 
     # Display data
-    pandas.set_option('display.max_rows', 500)
-    pandas.set_option('display.max_columns', 500)
-    pandas.set_option('display.width', 100)
+    max_line_width = 135
+    column_width = 15
+
+    max_line_width = max(max_line_width, int(0.9*shutil.get_terminal_size((80, 20)).columns))
 
     nodes, _, metrics, metrics_unit, metrics_to_show, _ = \
         _collect_data(chip, flow, flowgraph_nodes)
@@ -21,7 +24,7 @@ def _show_summary_table(chip, flow, flowgraph_nodes, show_all_indices):
         _get_flowgraph_path(chip, flow, flowgraph_nodes, only_include_successful=True)
 
     # only report tool based steps functions
-    for (step, index) in flowgraph_nodes.copy():
+    for (step, index) in list(flowgraph_nodes):
         if get_tool_task(chip, step, index, flow=flow)[0] == 'builtin':
             del flowgraph_nodes[flowgraph_nodes.index((step, index))]
 
@@ -40,21 +43,30 @@ def _show_summary_table(chip, flow, flowgraph_nodes, show_all_indices):
     else:
         paramstr = "None"
 
-    colwidth = 8  # minimum col width
-    row_labels = [' ' + metric for metric in metrics_to_show]
-    column_labels = [f'{step}{index}'.center(colwidth)
-                     for step, index in nodes_to_show]
-    column_labels.insert(0, 'units')
+    # trim labels to column width
+    column_labels = []
+    labels = [f'{step}{index}' for step, index in nodes_to_show]
+    if labels:
+        column_width = min([column_width, max([len(label) for label in labels])])
+
+    for label in labels:
+        column_labels.append(truncate_text(label, column_width).center(column_width))
+
+    row_labels = []
+    if metrics_to_show:
+        row_label_len = max([len(metric) for metric in metrics_to_show])
+        row_unit_len = max([len(metrics_unit[metric]) for metric in metrics_to_show])
+        for metric in metrics_to_show:
+            row_labels.append(f'{metric:<{row_label_len}}  {metrics_unit[metric]:>{row_unit_len}}')
 
     data = []
     for metric in metrics_to_show:
         row = []
-        row.append(metrics_unit[metric])
         for node in nodes_to_show:
             value = metrics[node][metric]
             if value is None:
                 value = '---'
-            value = ' ' + value.center(colwidth)
+            value = ' ' + value.center(column_width)
             row.append(value)
         data.append(row)
 
@@ -82,12 +94,12 @@ def _show_summary_table(chip, flow, flowgraph_nodes, show_all_indices):
 
     info = '\n'.join(info_list)
 
-    print("-" * 135)
+    print("-" * max_line_width)
     print(info, "\n")
 
     df = pandas.DataFrame(data, row_labels, column_labels)
     if not df.empty:
-        print(df.to_string())
+        print(df.to_string(line_width=max_line_width, col_space=2))
     else:
         print(' No metrics to display!')
-    print("-" * 135)
+    print("-" * max_line_width)

siliconcompiler/report/utils.py

@@ -43,7 +43,7 @@ def _collect_data(chip, flow=None, flowgraph_nodes=None, format_as_string=True):
     if not flowgraph_nodes:
         flowgraph_nodes = nodes_to_execute(chip)
         # only report tool based steps functions
-        for (step, index) in flowgraph_nodes.copy():
+        for (step, index) in list(flowgraph_nodes):
             tool, task = get_tool_task(chip, step, '0', flow=flow)
             if tool == 'builtin':
                 index = flowgraph_nodes.index((step, index))

siliconcompiler/scheduler/__init__.py

@@ -1137,11 +1137,12 @@ def _hash_files(chip, step, index, setup=False):
         if not setup:
             # hash all outputs
             chip.hash_files('tool', tool, 'task', task, 'output',
-                            step=step, index=index, check=False)
+                            step=step, index=index, check=False, verbose=False)
         else:
             for task_key in ('refdir', 'prescript', 'postscript', 'script'):
                 chip.hash_files('tool', tool, 'task', task, task_key,
-                                step=step, index=index, check=False, allow_cache=True)
+                                step=step, index=index, check=False,
+                                allow_cache=True, verbose=False)
 
         # hash all requirements
         for item in set(chip.get('tool', tool, 'task', task, 'require', step=step, index=index)):
@@ -1153,12 +1154,13 @@ def _hash_files(chip, step, index, setup=False):
                     if not setup:
                         if chip.get(*args, field='filehash'):
                             continue
-                    chip.hash_files(*args, check=False, allow_cache=True)
+                    chip.hash_files(*args, check=False, allow_cache=True, verbose=False)
                 else:
                     if not setup:
                         if chip.get(*args, field='filehash', step=step, index=index):
                             continue
-                    chip.hash_files(*args, step=step, index=index, check=False, allow_cache=True)
+                    chip.hash_files(*args, step=step, index=index,
+                                    check=False, allow_cache=True, verbose=False)
 
 
 def _finalizenode(chip, step, index, replay):
@@ -1353,7 +1355,7 @@ def _check_node_dependencies(chip, node, deps, deps_was_successful):
     tool, task = get_tool_task(chip, step, index)
 
     # Clear any nodes that have finished from dependency list.
-    for in_step, in_index in deps.copy():
+    for in_step, in_index in list(deps):
         in_status = chip.get('record', 'status', step=in_step, index=in_index)
         if in_status != NodeStatus.PENDING:
             deps.remove((in_step, in_index))

siliconcompiler/schema/schema_cfg.py

@@ -1,7 +1,6 @@
 # Copyright 2022 Silicon Compiler Authors. All Rights Reserved.
 
 import json
-import re
 
 # Default import must be relative, to facilitate tools with Python interfaces
 # (such as KLayout) directly importing the schema package. However, the fallback
@@ -70,13 +69,14 @@ def scparam(cfg,
 
         # setting values based on types
         # note (bools are never lists)
-        if re.match(r'bool', sctype):
+        if sctype == 'bool':
             if defvalue is None:
                 defvalue = False
-        if re.match(r'\[', sctype) and signature is None:
-            signature = []
-        if re.match(r'\[', sctype) and defvalue is None:
-            defvalue = []
+        if '[' in sctype:
+            if signature is None:
+                signature = []
+            if defvalue is None:
+                defvalue = []
 
         # mandatory for all
         cfg['type'] = sctype
@@ -106,7 +106,7 @@ def scparam(cfg,
             cfg['unit'] = unit
 
         # file only values
-        if re.search(r'file', sctype):
+        if 'file' in sctype:
             cfg['hashalgo'] = hashalgo
             cfg['copy'] = copy
             cfg['node']['default']['default']['date'] = []
@@ -114,7 +114,7 @@ def scparam(cfg,
             cfg['node']['default']['default']['filehash'] = []
             cfg['node']['default']['default']['package'] = []
 
-        if re.search(r'dir', sctype):
+        if 'dir' in sctype:
             cfg['hashalgo'] = hashalgo
             cfg['copy'] = copy
             cfg['node']['default']['default']['filehash'] = []

siliconcompiler/schema/schema_obj.py

@@ -1008,7 +1008,7 @@ class Schema:
 
     ###########################################################################
     def write_json(self, fout):
-        localcfg = self.copy().cfg
+        localcfg = {**self.cfg}
         if self.__journal is not None:
             localcfg['__journal__'] = self.__journal
         fout.write(json.dumps(localcfg, indent=4))
@@ -1240,7 +1240,8 @@ class Schema:
         Reads a manifest and replays the journal
         '''
 
-        schema = Schema(manifest=filename, logger=self.logger)
+        schema = Schema(logger=self.logger)
+        _, schema.__journal = Schema.__read_manifest_file(str(filename))
         self._import_journal(schema)
 
     #######################################
@@ -1435,7 +1436,7 @@ class Schema:
                                             action='append',
                                             help=helpstr,
                                             default=argparse.SUPPRESS)
-                elif re.match(r'\[', typestr) or pernodestr != 'never':
+                elif '[' in typestr or pernodestr != 'never':
                     # list type arguments
                     parser.add_argument(*switchstrs,
                                         metavar=metavar,
@@ -1708,7 +1709,7 @@ class Schema:
             if 'default' in keylist:
                 continue
             typestr = schema.get(*keylist, field='type')
-            should_append = re.match(r'\[', typestr) and not clear
+            should_append = '[' in typestr and not clear
 
             if allow_missing_keys and not self.valid(*keylist, default_valid=True):
                 self.logger.warning(f'{keylist} not found in schema, skipping...')
@@ -1786,7 +1787,7 @@ class Schema:
                     self.logger.warning(f'Keypath {keylist} is not valid')
             if key_valid and 'default' not in keylist:
                 typestr = src.get(*keylist, field='type')
-                should_append = re.match(r'\[', typestr) and not clear
+                should_append = '[' in typestr and not clear
                 key_cfg = src.__search(*keylist)
                 for val, step, index in src._getvals(*keylist, return_defvalue=False):
                     # update value, handling scalars vs. lists

siliconcompiler/tools/verilator/compile.py

@@ -100,20 +100,26 @@ def runtime_options(chip):
 
     cmdlist.extend(['-o', f'../outputs/{design}.vexe'])
 
+    c_flags = chip.get('tool', tool, 'task', task, 'var', 'cflags', step=step, index=index)
+    c_includes = chip.find_files('tool', tool, 'task', task, 'dir', 'cincludes',
+                                 step=step, index=index)
+
     if chip.get('tool', tool, 'task', task, 'var', 'trace', step=step, index=index)[0] == 'true':
         trace_type = chip.get('tool', tool, 'task', task, 'var', 'trace_type',
                               step=step, index=index)
 
         if trace_type == ['vcd']:
+            ext = 'vcd'
             trace_opt = '--trace'
         elif trace_type == ['fst']:
+            ext = 'fst'
             trace_opt = '--trace-fst'
 
         cmdlist.append(trace_opt)
 
-    c_flags = chip.get('tool', tool, 'task', task, 'var', 'cflags', step=step, index=index)
-    c_includes = chip.find_files('tool', tool, 'task', task, 'dir', 'cincludes',
-                                 step=step, index=index)
+        # add siliconcompiler specific defines
+        c_flags.append("-DSILICONCOMPILER_TRACE_DIR=\\\"reports\\\"")
+        c_flags.append(f"-DSILICONCOMPILER_TRACE_FILE=\\\"reports/{design}.{ext}\\\"")
 
     if c_includes:
         c_flags.extend([f'-I{include}' for include in c_includes])

siliconcompiler/tools/yosys/syn_asic.py

@@ -208,9 +208,10 @@ def prepare_synthesis_libraries(chip):
     # mark dff libery file with dont use
     dff_liberty_file = chip.find_files('tool', tool, 'task', task, 'file', 'dff_liberty',
                                        step=step, index=index)[0]
+    yosys_dff_file = chip.get('tool', tool, 'task', task, 'file', 'dff_liberty_file',
+                              step=step, index=index)[0]
 
-    with open(chip.get('tool', tool, 'task', task, 'file', 'dff_liberty_file',
-                       step=step, index=index)[0], 'w') as f:
+    with open(yosys_dff_file, 'w') as f:
         f.write(prepareLib.processLibertyFile(
             dff_liberty_file,
             logger=None if chip.get('option', 'quiet', step=step, index=index) else chip.logger
@@ -250,6 +251,11 @@ def prepare_synthesis_libraries(chip):
                     lib_file_name = f'{lib_file_name_base}_{unique_ident}'
                     unique_ident += 1
 
+                if lib_file == dff_liberty_file:
+                    with sc_open(yosys_dff_file) as f:
+                        lib_content[lib_file_name] = f.read()
+                    continue
+
                 lib_content[lib_file_name] = prepareLib.processLibertyFile(
                         lib_file,
                         logger=None if chip.get('option', 'quiet',

siliconcompiler/utils/__init__.py

@@ -404,3 +404,20 @@ def get_plugins(system):
         plugins.append(plugin.load())
 
     return plugins
+
+
+def truncate_text(text, width):
+    if len(text) <= width:
+        return text
+
+    keep_end = 0
+    while text[-1 - keep_end].isnumeric():
+        if keep_end >= 2:
+            break
+        keep_end += 1
+
+    while len(text) > width:
+        break_at = len(text) - keep_end - 3
+        text = text[:break_at-1] + '...' + text[break_at+3:]
+
+    return text

{siliconcompiler-0.26.3.dist-info → siliconcompiler-0.26.4.post1.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.26.3
+Version: 0.26.4.post1
 Summary: A compiler framework that automates translation from source code to silicon.
 Home-page: https://siliconcompiler.com
 Author: Andreas Olofsson
@@ -43,6 +43,8 @@ Requires-Dist: sc-leflib>=0.2.0; extra == "docs"
 Provides-Extra: examples
 Requires-Dist: migen==0.9.2; extra == "examples"
 Requires-Dist: lambdalib==0.2.9; extra == "examples"
+Provides-Extra: profile
+Requires-Dist: gprof2dot==2024.6.6; extra == "profile"
 Provides-Extra: test
 Requires-Dist: pytest==8.3.2; extra == "test"
 Requires-Dist: pytest-xdist==3.6.1; extra == "test"

{siliconcompiler-0.26.3.dist-info → siliconcompiler-0.26.4.post1.dist-info}/RECORD

@@ -1,9 +1,9 @@
 siliconcompiler/__init__.py,sha256=5T-mWDc05v0FEdwg2btphrAb_W7XaXUmKrRSxuSMNUQ,535
 siliconcompiler/__main__.py,sha256=x5bzv4spw66iQOldUM-iCWw2j5NxXkkkC_Wd2hGAAgo,182
 siliconcompiler/_common.py,sha256=27VU0PqZkD6-qz20brjzj-Z8cpDt0oyE6ZA6wARZvrk,1283
-siliconcompiler/_metadata.py,sha256=iO0XbuLpdQ8M_UIUfaYtJpaP2jX2xzy1DsX5ysoAZW0,1300
-siliconcompiler/core.py,sha256=nEi-kSkVsI3LcaYHeKm7avXTUqQFvsBZlQ521ORVa1E,131000
-siliconcompiler/flowgraph.py,sha256=aQh0VO7LVwGNJbWZcBIgzGRv_pDH72_ilMQtK906Rqk,22502
+siliconcompiler/_metadata.py,sha256=7UWL37j0f1EGwXqC65d_g5vkEjwFTvCZX2FqQcV2xd0,1306
+siliconcompiler/core.py,sha256=Sakw_lwdW6aFwIeI3UtT40LI3rxT2ToVvj4FytkWcQU,132906
+siliconcompiler/flowgraph.py,sha256=1a6_hnAuxpGNevvF4EbrjW7PhhOjyQqQfeBuEiJXOUw,22533
 siliconcompiler/issue.py,sha256=wRRG3b5bz8IdcT__hJME1svZwbsh_fGQr4VR8sTnta8,11425
 siliconcompiler/package.py,sha256=Z2FqMRq8mtvmF6d_hyDOZN8DOZ8gu7zABDMWOfUGu-M,14463
 siliconcompiler/units.py,sha256=dYn185TzusMtBd69RFKhNlCky2td5jC__AJdPjqXELU,6069
@@ -27,7 +27,7 @@ siliconcompiler/flows/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3h
 siliconcompiler/flows/_common.py,sha256=xu2k8gzE0RznrhXblSWLiuhvAqYRI4wbmd0JPepu_J8,2214
 siliconcompiler/flows/asicflow.py,sha256=pWonmU0iqKyk4KW4unKdAfgadp0l659NKbhXFyn6DRc,6298
 siliconcompiler/flows/asictopflow.py,sha256=EGzqEwTJLC983xA7J9Dky32sZeHQ-Ptn5uKh2DOQ70E,1207
-siliconcompiler/flows/dvflow.py,sha256=iTrmw2dRYEDCwNZysLx4N1YIe5KiVbZOnCUhmSYUsHE,2252
+siliconcompiler/flows/dvflow.py,sha256=Wty9FQyPE3ssl0_Xf6UwpJu2Ow9RIPJK22zIM6jCzhk,2408
 siliconcompiler/flows/fpgaflow.py,sha256=_de2l4IqH3QQE0g1eWiXDgFsWfg5yy3gzTEPsBwgo-c,6679
 siliconcompiler/flows/generate_openroad_rcx.py,sha256=z3HcYFEyROqFe7QL3Bay16CrMvD7_BGB4DX8woiX9xU,2424
 siliconcompiler/flows/lintflow.py,sha256=Jg1WYVI4AXNybARXt-gbCi6KvxExQJYE0EKW7Tav3fU,1051
@@ -66,22 +66,22 @@ siliconcompiler/remote/server_schema/responses/delete_job.json,sha256=25qnemP53r
 siliconcompiler/remote/server_schema/responses/get_results.json,sha256=86jz_z3o8h-F3VEndX6Ap7YReTAmaEPOw07BI2Uz42U,409
 siliconcompiler/remote/server_schema/responses/remote_run.json,sha256=qOX3lAsm--aMqUNq3jCnspoyl4y-sv9xH64TeCMCKrg,500
 siliconcompiler/report/__init__.py,sha256=jdPkZx3csEPoWA_fJcdr5mSu5WOhrrGgcc1iot9fR1A,408
-siliconcompiler/report/html_report.py,sha256=82THDLkGhvOmnwgHnjgm958CfGdagCBdmJlSpyKn0FM,2672
+siliconcompiler/report/html_report.py,sha256=HWLnKs8t3Ve0Nduw9h4hLpMS6JjA8-zRo3ZQktl5P4Y,2671
 siliconcompiler/report/report.py,sha256=8kMGjsRoqELFtGjujfUFhmyrhjKYwA1EEznI8k5ivlk,13937
 siliconcompiler/report/streamlit_report.py,sha256=GUwHgeMVOuETz8ZvYsEYv-uIDcV8KdLQX4xKJFS2a0M,4179
 siliconcompiler/report/streamlit_viewer.py,sha256=WbwcEf2t1gQihUnxnefwlAXKThwcNd4iQmeC8uDRY5c,41965
 siliconcompiler/report/summary_image.py,sha256=r8GbFJgD0ZLfYFFl8nmUhsh87wWP7evCljWWHx7_L8U,3687
-siliconcompiler/report/summary_table.py,sha256=NfSB8yHFirSCxvBROXURLzZM4UrYN2M050CScjeuFYk,2997
-siliconcompiler/report/utils.py,sha256=Yr-vcCoylN3HvlqAK0l6LLgdHfauezCmAhCzVqiHHpU,6603
-siliconcompiler/scheduler/__init__.py,sha256=0vwjttIOHxMBJBtYKgP9i4JE9DqPjbJ5j-kvcTutx30,82254
+siliconcompiler/report/summary_table.py,sha256=WHzk710YeTZKzOVOYDtzoHMSnDRJ6GcCL5yO_q22NjE,3521
+siliconcompiler/report/utils.py,sha256=daMAoRrRhRKfsVbPO5SIz8cvpGkFV12nkDNCdmUJCTU,6602
+siliconcompiler/scheduler/__init__.py,sha256=mWbSq6oYAWUzBbwxWVVcAnqzs5w9qKAwheNQkDMSj28,82383
 siliconcompiler/scheduler/docker_runner.py,sha256=ZboFmi9C_TPkgQlizU3nLmdDUip5EqvN-1JoJZMFFTs,8318
 siliconcompiler/scheduler/run_node.py,sha256=Mmj2epARKCuwN6oW-PyvExwY3OzRxUrG0mPLr3SwQ6M,5201
 siliconcompiler/scheduler/send_messages.py,sha256=ZVO6923-EJWUMlDOOpLEhaSrsKtP-d4J_UcfRp6kJDo,6387
 siliconcompiler/scheduler/slurm.py,sha256=IaglZSvrHOqEDT46ZcJ19gXpJxiMm7AAO7EvVdrauZc,7305
 siliconcompiler/scheduler/validation/email_credentials.json,sha256=rJHUmTS0YyQVCeZpJI1D4WgxsXRHigZTJ6xToITziuo,1800
 siliconcompiler/schema/__init__.py,sha256=5MfwK7me_exH7qjcInSUSesM0kiGIx8FXQDj4Br2QAQ,127
-siliconcompiler/schema/schema_cfg.py,sha256=BXN-79sgYwA-pQLc7PlYwlQIA92jmvWNQWsGYC-pAV8,183570
-siliconcompiler/schema/schema_obj.py,sha256=R3rrGNgoyNakMmQ2HDW9XJwfar3WMKVyqWrClr38jR8,74403
+siliconcompiler/schema/schema_cfg.py,sha256=NjBklevKitriRGNgMoQdSfxOdkkeGYjpKb9Gpga3F_c,183517
+siliconcompiler/schema/schema_obj.py,sha256=7sQ7GfU0iWXqtGibp28sy2g7caKRnNinrEeu71QPcaE,74425
 siliconcompiler/schema/utils.py,sha256=KKWtwOkXcDjaxs2f4yIuE6JCFZaapGjdLG4dQLYmH08,4111
 siliconcompiler/sphinx_ext/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/sphinx_ext/dynamicgen.py,sha256=bfGLUzggDEvw0GtWzt73LStlh1m90224KCPFj8PRz4s,35531
@@ -200,12 +200,12 @@ siliconcompiler/tools/slang/__init__.py,sha256=BMJjbTWCumTBbshaTc5Wgjcl3kxPiPjwc
 siliconcompiler/tools/slang/lint.py,sha256=eNe82gmZgCMvLEKQJHagyP1yNWRQ23agBE3n709-Lz4,3080
 siliconcompiler/tools/surelog/parse.py,sha256=i7mU6xIWrSfuTb9ov1ZSJKipyyhvlGFFmKf8y--Qrns,6208
 siliconcompiler/tools/surelog/surelog.py,sha256=PlkIjrFGq1t8U2gxFSKPouDmcnS6LE1oTZDrXtVJh7M,5034
-siliconcompiler/tools/surelog/bin/surelog.exe,sha256=ipLxuZRUeeUCfqcjOidbBfVN3mNJhuwmoXBqrmq9aqk,6422528
+siliconcompiler/tools/surelog/bin/surelog.exe,sha256=4lIJbHFKDENE2nFR96oDSXzqHZjOElchVR6oiMA2SQ8,6422528
 siliconcompiler/tools/surelog/templates/output.v,sha256=NE9iQW-IEx0wanJSpbZQjRt-Qq2oIx78JOzlsBcd0Is,213
 siliconcompiler/tools/sv2v/convert.py,sha256=PG1cYSUil2sZDGh8Eb0dCvsTMnW7o2nUewv2LA23DCw,1837
 siliconcompiler/tools/sv2v/sv2v.py,sha256=AuMHqm109GJhz6oqvDyyrO9ICGI8FiDXKzBsdMFvDa0,1078
 siliconcompiler/tools/template/template.py,sha256=0UwvFxuNoop41gBgcP21AfmHL13C1HZOlCjPGEgz1S8,3531
-siliconcompiler/tools/verilator/compile.py,sha256=CrDpYqOPo7zgOWXAfadj4xI32OoJ3AJfU1KXXMqYGLs,5345
+siliconcompiler/tools/verilator/compile.py,sha256=gpUpivElPccHkne4UFg8lr5hLw8dT6yOLnJb4sfAkFk,5604
 siliconcompiler/tools/verilator/lint.py,sha256=YAlWcpeSbCdBSDLU5-eJnKWQUv3cM3lQaGBUyWYqN78,539
 siliconcompiler/tools/verilator/parse.py,sha256=J8yCqLJ6TZTkloRnMcJIhOmAxIfUZmtgnVY7N8RVSjs,833
 siliconcompiler/tools/verilator/verilator.py,sha256=CDbLZauBXFbh2yC1I02FIahBOB0Sm0EeCPjNwryhpUM,6115
@@ -232,7 +232,7 @@ siliconcompiler/tools/yosys/lec.py,sha256=7kUpdcNnl1_YVJzD6ZQY2RFHCaucxJHboPRkK1
 siliconcompiler/tools/yosys/prepareLib.py,sha256=HdgZVK-zSuKdMIsGmpgmFjKpIE0PA6IVAF1YsGOAG7c,2326
 siliconcompiler/tools/yosys/sc_lec.tcl,sha256=ZmgCEA_cuwBk1E9d2PEOsdO1595VCEFy1d6J5_61Pfo,2373
 siliconcompiler/tools/yosys/sc_syn.tcl,sha256=dXghNwdrzh_ry_hfmgBMlnJATEPCvN2YfdtInJShEOk,2519
-siliconcompiler/tools/yosys/syn_asic.py,sha256=OheWDbk6_ZJypSr-XecQWUdzd-jTWD0Mwb4xhIrw7F4,24198
+siliconcompiler/tools/yosys/syn_asic.py,sha256=p1adJk6-6hhf-T9CXPOeeSmwK95IpnbSuI1D-dtI9DY,24443
 siliconcompiler/tools/yosys/syn_asic.tcl,sha256=emAM1PS04Vw3dNK6M6D-pd7daOVKajxKHeey40AqYiQ,12262
 siliconcompiler/tools/yosys/syn_asic_fpga_shared.tcl,sha256=c9QcuhnYCkPWk-tO71TO3vrU1pDIx9jqomswpHAMKLY,746
 siliconcompiler/tools/yosys/syn_fpga.py,sha256=GZw4lI1veYn-LV8ELr9sPYpmENqPeMBRysqRD1o1poU,5533
@@ -241,12 +241,12 @@ siliconcompiler/tools/yosys/syn_strategies.tcl,sha256=lrjKiso1p5OfoyF-g6Eujt8aj3
 siliconcompiler/tools/yosys/yosys.py,sha256=xh1XmcA0liahy-QE6vSNbvjkcgOlKUk5BYAiAWDdwOk,5096
 siliconcompiler/tools/yosys/techmaps/lcu_kogge_stone.v,sha256=FqER4Zjjr5jC3TbM7ZX_pftAnlD4_uR6EJQpoII1WOU,812
 siliconcompiler/tools/yosys/templates/abc.const,sha256=2Ea7eZz2eHzar3RLf_l2Nb9dnr8A_Ax0Sxb8krA33hw,118
-siliconcompiler/utils/__init__.py,sha256=b3mhPeBb8HIqU-8w23h2IMLSxuDrXm53e5iSeqZrkDI,13168
+siliconcompiler/utils/__init__.py,sha256=32FMHXVJWtbmvjIEVm2-XwX4A4GPHSTvkWzs0Pw1HWc,13545
 siliconcompiler/utils/asic.py,sha256=knq-raDWs1FKtfqkUbLOecdSwXezlmqb8gk9QPZWdqY,5144
 siliconcompiler/utils/showtools.py,sha256=kNaw97U6tV_MwLvWb1dme_k9E6dQVqnTT6y2zzMcXJk,1158
-siliconcompiler-0.26.3.dist-info/LICENSE,sha256=UJh7mqgsPZN3gg37jhwYnrtCUs1m19vkIA6Px7jAOPY,10956
-siliconcompiler-0.26.3.dist-info/METADATA,sha256=dfjuEAkNiUygxzFUch_VhbXAsBmumNqMEQzxZB_TdRQ,9612
-siliconcompiler-0.26.3.dist-info/WHEEL,sha256=TYUDfHBZQod294as1x7ro928Hk-WSGPsPZPVYrwc_bI,101
-siliconcompiler-0.26.3.dist-info/entry_points.txt,sha256=M3cpZxvqanXhVU9CuLTRDzBdDKmKz-t0p4DT57TyysU,451
-siliconcompiler-0.26.3.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
-siliconcompiler-0.26.3.dist-info/RECORD,,
+siliconcompiler-0.26.4.post1.dist-info/LICENSE,sha256=UJh7mqgsPZN3gg37jhwYnrtCUs1m19vkIA6Px7jAOPY,10956
+siliconcompiler-0.26.4.post1.dist-info/METADATA,sha256=tLPcZlnq-IANGpk8VbV4hdfYNCD-LexQF8xmIIe84y0,9699
+siliconcompiler-0.26.4.post1.dist-info/WHEEL,sha256=TYUDfHBZQod294as1x7ro928Hk-WSGPsPZPVYrwc_bI,101
+siliconcompiler-0.26.4.post1.dist-info/entry_points.txt,sha256=M3cpZxvqanXhVU9CuLTRDzBdDKmKz-t0p4DT57TyysU,451
+siliconcompiler-0.26.4.post1.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
+siliconcompiler-0.26.4.post1.dist-info/RECORD,,