siliconcompiler 0.26.2__cp39-cp39-win_amd64.whl → 0.26.4.post1__cp39-cp39-win_amd64.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.26.2'
+version = '0.26.4.post1'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/apps/sc_issue.py

@@ -25,13 +25,13 @@ Restricted SC app that generates a sharable testcase from a
 failed flow or runs an issue generated with this program.
 
 To generate a testcase, use:
-    sc-issue -generate -cfg <stepdir>/outputs/<design>.pkg.json
+    sc-issue -cfg <stepdir>/outputs/<design>.pkg.json
 
     or include a different step/index than what the cfg_file is pointing to:
-    sc-issue -generate -cfg <otherdir>/outputs/<design>.pkg.json -arg_step <step> -arg_index <index>
+    sc-issue -cfg <otherdir>/outputs/<design>.pkg.json -arg_step <step> -arg_index <index>
 
     or include specific libraries while excluding others:
-    sc-issue -generate -cfg <stepdir>/outputs/<design>.pkg.json -exclude_libraries -add_library sram -add_library gpio
+    sc-issue -cfg <stepdir>/outputs/<design>.pkg.json -exclude_libraries -add_library sram -add_library gpio
 
 To run a testcase, use:
     sc-issue -run -file sc_issue_<...>.tar.gz
@@ -39,10 +39,6 @@ To run a testcase, use:
 """  # noqa E501
 
     issue_arguments = {
-        '-generate': {'action': 'store_true',
-                      'help': 'generate a testcase',
-                      'sc_print': False},
-
         '-exclude_libraries': {'action': 'store_true',
                                'help': 'flag to ensure libraries are excluded in the testcase',
                                'sc_print': False},
@@ -88,10 +84,7 @@ To run a testcase, use:
         chip.logger.error(e)
         return 1
 
-    if switches['generate'] and switches['run']:
-        raise ValueError('Only one of -generate or -run can be used')
-
-    if switches['generate']:
+    if not switches['run']:
         step = chip.get('arg', 'step')
         index = chip.get('arg', 'index')
 

siliconcompiler/apps/smake.py

@@ -41,7 +41,20 @@ def __process_file(path):
             arg_type = str
             if arg in func_spec.annotations:
                 arg_type = func_spec.annotations[arg]
-            func_args[arg] = arg_type
+            func_args[arg] = {
+                "type": arg_type
+            }
+
+        if func_spec.defaults:
+            for arg, defval in zip(reversed(func_spec.args), reversed(func_spec.defaults)):
+                func_args[arg]["default"] = defval
+
+                if defval is None:
+                    continue
+
+                if type(defval) is not func_args[arg]["type"]:
+                    if isinstance(defval, (bool, str, float, int)):
+                        func_args[arg]["type"] = type(defval)
 
         args[name] = {
             "function": func,
@@ -62,7 +75,7 @@ def __process_file(path):
     return args, default_arg, module_help
 
 
-def main():
+def main(source_file=None):
     progname = "smake"
     description = f"""-----------------------------------------------------------
 SC app that provides an Makefile like interface to python
@@ -90,16 +103,18 @@ To run a target with supported arguments, use:
 -----------------------------------------------------------"""
 
     # handle source file identification before arg parse
-    source_file = __default_source_file
-    file_args = ('--file', '-f')
-    for file_arg in file_args:
-        if file_arg in sys.argv:
-            source_file_idx = sys.argv.index(file_arg) + 1
-            if source_file_idx < len(sys.argv):
-                source_file = sys.argv[source_file_idx]
-            else:
-                source_file = None
-            break
+    file_args = None
+    if not source_file:
+        source_file = __default_source_file
+        file_args = ('--file', '-f')
+        for file_arg in file_args:
+            if file_arg in sys.argv:
+                source_file_idx = sys.argv.index(file_arg) + 1
+                if source_file_idx < len(sys.argv):
+                    source_file = sys.argv[source_file_idx]
+                else:
+                    source_file = None
+                break
 
     # handle directory identification before arg parse
     source_dir = os.getcwd()
@@ -135,10 +150,11 @@ To run a target with supported arguments, use:
         description=description,
         formatter_class=argparse.RawDescriptionHelpFormatter)
 
-    parser.add_argument(
-        *file_args,
-        metavar='<file>',
-        help=f'Use file as makefile, default is {__default_source_file}')
+    if file_args:
+        parser.add_argument(
+            *file_args,
+            metavar='<file>',
+            help=f'Use file as makefile, default is {__default_source_file}')
 
     parser.add_argument(
         *dir_args,
@@ -159,14 +175,38 @@ To run a target with supported arguments, use:
         subparse = targetparsers.add_parser(
             arg,
             description=info['full_help'],
-            help=info['help'])
+            help=info['help'],
+            formatter_class=argparse.RawDescriptionHelpFormatter)
+
+        for subarg, subarg_info in info['args'].items():
+            # print(subarg, subarg_info)
+            add_args = {}
+
+            if "default" not in subarg_info:
+                add_args["required"] = True
+            else:
+                if type(subarg_info["default"]) is subarg_info["type"]:
+                    add_args["default"] = subarg_info["default"]
+
+            if subarg_info["type"] is bool:
+                def str2bool(v):
+                    # modified from:
+                    # https://github.com/pypa/distutils/blob/8993718731b951ee36d08cb784f02aa13542ce15/distutils/util.py
+                    val = v.lower()
+                    if val in ('y', 'yes', 't', 'true', 'on', '1'):
+                        return True
+                    elif val in ('n', 'no', 'f', 'false', 'off', '0'):
+                        return False
+                    else:
+                        raise ValueError(f"invalid truth value {val!r}")
+                subarg_info["type"] = str2bool
 
-        for subarg, subarg_type in info['args'].items():
             subparse.add_argument(
                 f'--{subarg}',
                 dest=f'sub_{subarg}',
                 metavar=f'<{subarg}>',
-                type=subarg_type)
+                type=subarg_info["type"],
+                **add_args)
 
     args = parser.parse_args()
     target = args.target

siliconcompiler/core.py

@@ -15,6 +15,7 @@ import inspect
 import textwrap
 import graphviz
 import codecs
+import copy
 from siliconcompiler.remote import client
 from siliconcompiler.schema import Schema, SCHEMA_VERSION
 from siliconcompiler.schema import utils as schema_utils
@@ -234,6 +235,7 @@ class Chip:
             for future_step, future_index in nodes_to_run:
                 max_step_len = max(len(future_step), max_step_len)
                 max_index_len = max(len(future_index), max_index_len)
+            max_step_len = min(max_step_len, 20)
 
             jobname = self.get('option', 'jobname')
 
@@ -243,7 +245,7 @@ class Chip:
                 index = '-' * max(max_index_len // 4, 1)
 
             log_format.append(jobname)
-            log_format.append(f'{step: <{max_step_len}}')
+            log_format.append(f'{utils.truncate_text(step, max_step_len): <{max_step_len}}')
             log_format.append(f'{index: >{max_index_len}}')
 
         log_format.append('%(message)s')
@@ -555,7 +557,12 @@ class Chip:
 
             elif isinstance(use_module, (Library, Chip)):
                 self._loaded_modules['libs'].append(use_module.design)
-                self.__import_library(use_module.design, use_module.schema.cfg)
+                cfg = use_module.schema.cfg
+                keep_inputs = True
+                if not isinstance(use_module, Library):
+                    keep_inputs = False
+                self.__import_library(use_module.design, cfg,
+                                      keep_input=keep_inputs)
 
                 is_auto_enable = getattr(use_module, 'is_auto_enable', None)
                 if is_auto_enable:
@@ -1001,8 +1008,8 @@ class Chip:
             package (str): Name of package where this file can be found
         '''
 
-        self.__add_input_output('input', filename, fileset, filetype, iomap,
-                                step=step, index=index, package=package)
+        self._add_input_output('input', filename, fileset, filetype, iomap,
+                               step=step, index=index, package=package)
     # Replace {iotable} in __doc__ with actual table for fileset/filetype and extension mapping
     input.__doc__ = input.__doc__.replace("{iotable}",
                                           utils.format_fileset_type_table())
@@ -1012,14 +1019,14 @@ class Chip:
                step=None, index=None, package=None):
         '''Same as input'''
 
-        self.__add_input_output('output', filename, fileset, filetype, iomap,
-                                step=step, index=index, package=package)
+        self._add_input_output('output', filename, fileset, filetype, iomap,
+                               step=step, index=index, package=package)
     # Copy input functions __doc__ and replace 'input' with 'output' to make constant
     output.__doc__ = input.__doc__.replace("input", "output")
 
     ###########################################################################
-    def __add_input_output(self, category, filename, fileset, filetype, iomap,
-                           step=None, index=None, package=None):
+    def _add_input_output(self, category, filename, fileset, filetype, iomap,
+                          step=None, index=None, package=None, quiet=False):
         '''
         Adds file to input or output groups.
         Performs a lookup in the io map for the fileset and filetype
@@ -1051,12 +1058,13 @@ class Chip:
         if not use_fileset or not use_filetype:
             self.logger.error(f'Unable to infer {category} fileset and/or filetype for '
                               f'{filename} based on file extension.')
-        elif not fileset and not filetype:
-            self.logger.info(f'{filename} inferred as {use_fileset}/{use_filetype}')
-        elif not filetype:
-            self.logger.info(f'{filename} inferred as filetype {use_filetype}')
-        elif not fileset:
-            self.logger.info(f'{filename} inferred as fileset {use_fileset}')
+        elif not quiet:
+            if not fileset and not filetype:
+                self.logger.info(f'{filename} inferred as {use_fileset}/{use_filetype}')
+            elif not filetype:
+                self.logger.info(f'{filename} inferred as filetype {use_filetype}')
+            elif not fileset:
+                self.logger.info(f'{filename} inferred as fileset {use_fileset}')
 
         self.add(category, use_fileset, use_filetype, filename,
                  step=step, index=index, package=package)
@@ -1162,6 +1170,10 @@ class Chip:
 
         result = []
 
+        collection_dir = self._getcollectdir(jobname=job)
+        if not os.path.exists(collection_dir):
+            collection_dir = None
+
         # Special cases for various ['tool', ...] files that may be implicitly
         # under the workdir (or refdir in the case of scripts).
         # TODO: it may be cleaner to have a file resolution scope flag in schema
@@ -1190,10 +1202,8 @@ class Chip:
             search_paths = self.__convert_paths_to_posix(search_paths)
 
         for (dependency, path) in zip(dependencies, paths):
-            if not search_paths:
-                import_path = self.__find_sc_imported_file(path,
-                                                           dependency,
-                                                           self._getcollectdir(jobname=job))
+            if not search_paths and collection_dir:
+                import_path = self.__find_sc_imported_file(path, dependency, collection_dir)
                 if import_path:
                     result.append(import_path)
                     continue
@@ -1238,6 +1248,10 @@ class Chip:
         if not path:
             return None
 
+        collected_files = os.listdir(collected_dir)
+        if not collected_files:
+            return None
+
         path_paths = pathlib.PurePosixPath(path).parts
         for n in range(len(path_paths)):
             # Search through the path elements to see if any of the previous path parts
@@ -1247,7 +1261,11 @@ class Chip:
             basename = str(pathlib.PurePosixPath(*path_paths[0:n]))
             endname = str(pathlib.PurePosixPath(*path_paths[n:]))
 
-            abspath = os.path.join(collected_dir, self.__get_imported_filename(basename, package))
+            import_name = self.__get_imported_filename(basename, package)
+            if import_name not in collected_files:
+                continue
+
+            abspath = os.path.join(collected_dir, import_name)
             if endname:
                 abspath = os.path.join(abspath, endname)
             abspath = os.path.abspath(abspath)
@@ -1256,19 +1274,18 @@ class Chip:
 
         return None
 
-    ###########################################################################
-    def find_result(self, filetype, step, jobname=None, index='0'):
+    def find_node_file(self, path, step, jobname=None, index='0'):
         """
-        Returns the absolute path of a compilation result.
+        Returns the absolute path of a file from a particular node.
 
-        Utility function that returns the absolute path to a results
+        Utility function that returns the absolute path to a node
         file based on the provided arguments. The result directory
         structure is:
 
-        <dir>/<design>/<jobname>/<step>/<index>/outputs/<design>.filetype
+        <dir>/<design>/<jobname>/<step>/<index>/<path>
 
         Args:
-            filetype (str): File extension (v, def, etc)
+            path (str): Path to file inside node run directory
             step (str): Task step name ('syn', 'place', etc)
             jobname (str): Jobid directory name
             index (str): Task index
@@ -1277,23 +1294,54 @@ class Chip:
             Returns absolute path to file.
 
         Examples:
-            >>> manifest_filepath = chip.find_result('vg', 'syn')
-           Returns the absolute path to the manifest.
+            >>> manifest_filepath = chip.find_node_file('outputs/heartbeat.vg', 'syn')
+           Returns the absolute path to the gate level verilog.
         """
         if jobname is None:
             jobname = self.get('option', 'jobname')
 
         workdir = self.getworkdir(jobname, step, index)
-        design = self.top()
-        filename = f"{workdir}/outputs/{design}.{filetype}"
+        filename = f"{workdir}/{path}"
 
-        self.logger.debug("Finding result %s", filename)
+        self.logger.debug(f"Finding node file: {filename}")
 
         if os.path.exists(filename):
             return filename
         else:
             return None
 
+    ###########################################################################
+    def find_result(self, filetype, step, jobname=None, index='0'):
+        """
+        Returns the absolute path of a compilation result.
+
+        Utility function that returns the absolute path to a results
+        file based on the provided arguments. The result directory
+        structure is:
+
+        <dir>/<design>/<jobname>/<step>/<index>/outputs/<design>.filetype
+
+        Args:
+            filetype (str): File extension (v, def, etc)
+            step (str): Task step name ('syn', 'place', etc)
+            jobname (str): Jobid directory name
+            index (str): Task index
+
+        Returns:
+            Returns absolute path to file.
+
+        Examples:
+            >>> vg_filepath = chip.find_result('vg', 'syn')
+           Returns the absolute path to the gate level verilog.
+        """
+
+        design = self.top()
+        return self.find_node_file(
+            f"outputs/{design}.{filetype}",
+            step=step,
+            jobname=jobname,
+            index=index)
+
     ###########################################################################
     def __abspath(self):
         '''
@@ -1568,13 +1616,15 @@ class Chip:
         if not os.path.exists(os.path.dirname(filepath)):
             os.makedirs(os.path.dirname(filepath))
 
+        schema = self.schema
         # resolve absolute paths
         if abspath:
             schema = self.__abspath()
-        else:
-            schema = self.schema.copy()
 
         if prune:
+            if schema is self.schema:
+                schema = schema.copy()
+
             self.logger.debug('Pruning dictionary before writing file %s', filepath)
             schema.prune()
 
@@ -1797,7 +1847,7 @@ class Chip:
         return not error
 
     ###########################################################################
-    def __import_library(self, libname, libcfg, job=None, clobber=True):
+    def __import_library(self, libname, libcfg, job=None, clobber=True, keep_input=True):
         '''Helper to import library with config 'libconfig' as a library
         'libname' in current Chip object.'''
         if job:
@@ -1808,19 +1858,22 @@ class Chip:
         if 'library' in libcfg:
             for sublib_name, sublibcfg in libcfg['library'].items():
                 self.__import_library(sublib_name, sublibcfg,
-                                      job=job, clobber=clobber)
-
-            del libcfg['library']
+                                      job=job, clobber=clobber, keep_input=keep_input)
 
         if libname in cfg:
             if not clobber:
                 return
 
-        cfg[libname] = libcfg
         self.__import_data_sources(libcfg)
+        cfg[libname] = {}
 
-        if 'pdk' in cfg[libname]:
-            del cfg[libname]['pdk']
+        # Only keep some sections to avoid recursive bloat
+        keeps = ['asic', 'design', 'fpga', 'option', 'output', 'package']
+        if keep_input:
+            keeps.append('input')
+        for section in list(libcfg.keys()):
+            if section in keeps:
+                cfg[libname][section] = copy.deepcopy(libcfg[section])
 
     ###########################################################################
     def write_flowgraph(self, filename, flow=None,
@@ -1946,7 +1999,7 @@ class Chip:
 
     ###########################################################################
     def write_dependencygraph(self, filename, flow=None,
-                              fillcolor='#ffffff', fontcolor='#000000',
+                              fontcolor='#000000', color_scheme=None,
                               background='transparent', fontsize='14',
                               border=True, landscape=False):
         r'''
@@ -1964,8 +2017,9 @@ class Chip:
         Args:
             filename (filepath): Output filepath
             flow (str): Name of flowgraph to render
-            fillcolor(str): Node fill RGB color hex value
             fontcolor (str): Node font RGB color hex value
+            color_scheme (str): Name of the color scheme to apply to the nodes.
+                Valid choices are: "none", "simple", "detailed"
             background (str): Background color
             fontsize (str): Node text font size
             border (bool): Enables node border if True
@@ -1981,6 +2035,33 @@ class Chip:
         fileroot, ext = os.path.splitext(filepath)
         fileformat = ext.replace(".", "")
 
+        color_schemes = {
+            "none": {
+                "design": "white",
+                "library": "white",
+                "logiclib": "white",
+                "macrolib": "white"
+            },
+            "simple": {
+                "design": "lightgreen",
+                "library": "white",
+                "logiclib": "lightgreen",
+                "macrolib": "lightgreen"
+            },
+            "detailed": {
+                "design": "lightgreen",
+                "library": "white",
+                "logiclib": "lightskyblue",
+                "macrolib": "lightgoldenrod2"
+            },
+        }
+
+        if not color_scheme:
+            color_scheme = "none"
+
+        if color_scheme not in color_schemes:
+            raise ValueError(f'{color_scheme} is not a valid color scheme')
+
         # controlling border width
         if border:
             penwidth = '1'
@@ -2006,7 +2087,7 @@ class Chip:
             nodes.add(node)
             dot.node(node, label=node, bordercolor=fontcolor, style='filled',
                      fontcolor=fontcolor, fontsize=fontsize, ordering="in",
-                     penwidth=penwidth, fillcolor=fillcolor)
+                     penwidth=penwidth, fillcolor="white")
             return node
 
         nodes = {}
@@ -2019,32 +2100,53 @@ class Chip:
             if root_label in nodes:
                 return
 
-            in_libs = lib.get('option', 'library',
-                              step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY) + \
-                lib.get('asic', 'logiclib',
-                        step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY) + \
-                lib.get('asic', 'macrolib',
-                        step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY)
-
             in_labels = []
-            for in_lib in in_libs:
+            for in_lib in lib.get('option', 'library',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
                 in_labels.append(f'library-{in_lib}')
+            for in_lib in lib.get('asic', 'logiclib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                in_labels.append(f'logiclib-{in_lib}')
+            for in_lib in lib.get('asic', 'macrolib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                in_labels.append(f'macrolib-{in_lib}')
+
+            shape = "oval"
+            if root_type == "logiclib":
+                shape = "box"
+            elif root_type == "macrolib":
+                shape = "box"
+            elif root_type == "design":
+                shape = "box"
+
+            color = color_schemes[color_scheme][root_type]
 
             nodes[root_label] = {
                 "text": name,
-                "shape": "oval" if root_type == "library" else "box",
+                "shape": shape,
+                "color": color,
                 "connects_to": set(in_labels)
             }
 
-            for in_lib in in_libs:
-                collect_library("library", Schema(cfg=self.getdict('library', in_lib)), name=in_lib)
+            for in_lib in lib.get('option', 'library',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                collect_library("library", Schema(cfg=self.getdict('library', in_lib)),
+                                name=in_lib)
+            for in_lib in lib.get('asic', 'logiclib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                collect_library("logiclib", Schema(cfg=self.getdict('library', in_lib)),
+                                name=in_lib)
+            for in_lib in lib.get('asic', 'macrolib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                collect_library("macrolib", Schema(cfg=self.getdict('library', in_lib)),
+                                name=in_lib)
 
         collect_library("design", self)
 
         for label, info in nodes.items():
             dot.node(label, label=info['text'], bordercolor=fontcolor, style='filled',
                      fontcolor=fontcolor, fontsize=fontsize, ordering="in",
-                     penwidth=penwidth, fillcolor=fillcolor, shape=info['shape'])
+                     penwidth=penwidth, fillcolor=info["color"], shape=info['shape'])
 
             for conn in info['connects_to']:
                 dot.edge(label, conn, dir='back')
@@ -2086,7 +2188,7 @@ class Chip:
                              step=r_step, index=r_index)
                 else:
                     self.set(*key,
-                             list(map(lambda x: x.replace(org_library, new_library), val)),
+                             list(map(lambda x: new_library if x == org_library else x, val)),
                              step=r_step, index=r_index)
             else:
                 for val, r_step, r_index in self.schema._getvals(*key):
@@ -2100,7 +2202,7 @@ class Chip:
                                  step=r_step, index=r_index)
                     else:
                         self.set(*key,
-                                 list(map(lambda x: x.replace(org_library, new_library), val)),
+                                 list(map(lambda x: new_library if x == org_library else x, val)),
                                  step=r_step, index=r_index)
 
         swap('option', 'library')

siliconcompiler/flowgraph.py

@@ -423,7 +423,8 @@ def _get_flowgraph_information(chip, flow, io=True):
     from siliconcompiler.tools._common import input_provides, input_file_node_name
 
     # Save schema to avoid making permanent changes
-    org_schema = chip.schema.copy()
+    org_schema = chip.schema
+    chip.schema = chip.schema.copy()
 
     # Setup nodes
     node_exec_order = _get_flowgraph_execution_order(chip, flow)

siliconcompiler/flows/dvflow.py

@@ -1,6 +1,7 @@
 import siliconcompiler
 
 from siliconcompiler.tools.icarus import compile as icarus_compile
+from siliconcompiler.tools.verilator import compile as verilator_compile
 from siliconcompiler.tools.execute import exec_input
 
 
@@ -44,17 +45,21 @@ def setup(chip,
     if tool == 'icarus':
         tasks['compile'] = icarus_compile
         tasks['sim'] = exec_input
-        flowpipe = [
-            'compile',
-            'sim'
-        ]
-        flow_np = {
-            'compile': 1,
-            'sim': np
-        }
+    elif tool == 'verilator':
+        tasks['compile'] = verilator_compile
+        tasks['sim'] = exec_input
     else:
         raise ValueError(f'{tool} is not a supported tool for {flowname}: icarus')
 
+    flowpipe = [
+        'compile',
+        'sim'
+    ]
+    flow_np = {
+        'compile': 1,
+        'sim': np
+    }
+
     prevstep = None
     # Flow setup
     for step in flowpipe:

siliconcompiler/issue.py

@@ -153,6 +153,8 @@ def generate_testcase(chip,
     os.chdir(new_work_dir)
 
     # Rewrite replay.sh
+    prev_quiet = chip.get('option', 'quiet', step=step, index=index)
+    chip.set('option', 'quiet', True, step=step, index=index)
     from siliconcompiler import SiliconCompilerError
     try:
         # Rerun setup
@@ -167,6 +169,7 @@ def generate_testcase(chip,
                 pass
     except SiliconCompilerError:
         pass
+    chip.set('option', 'quiet', prev_quiet, step=step, index=index)
 
     flow = chip.get('option', 'flow')
     is_python_tool = hasattr(chip._get_task_module(step, index, flow=flow), 'run')

siliconcompiler/report/html_report.py

@@ -14,7 +14,7 @@ def _generate_html_report(chip, flow, flowgraph_nodes, results_html):
     '''
 
     # only report tool based steps functions
-    for (step, index) in flowgraph_nodes.copy():
+    for (step, index) in list(flowgraph_nodes):
         tool, task = get_tool_task(chip, step, '0', flow=flow)
         if tool == 'builtin':
             index = flowgraph_nodes.index((step, index))