siliconcompiler 0.26.2__cp38-cp38-win_amd64.whl → 0.26.3__cp38-cp38-win_amd64.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.26.2'
+version = '0.26.3'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/apps/sc_issue.py

@@ -25,13 +25,13 @@ Restricted SC app that generates a sharable testcase from a
 failed flow or runs an issue generated with this program.
 
 To generate a testcase, use:
-    sc-issue -generate -cfg <stepdir>/outputs/<design>.pkg.json
+    sc-issue -cfg <stepdir>/outputs/<design>.pkg.json
 
     or include a different step/index than what the cfg_file is pointing to:
-    sc-issue -generate -cfg <otherdir>/outputs/<design>.pkg.json -arg_step <step> -arg_index <index>
+    sc-issue -cfg <otherdir>/outputs/<design>.pkg.json -arg_step <step> -arg_index <index>
 
     or include specific libraries while excluding others:
-    sc-issue -generate -cfg <stepdir>/outputs/<design>.pkg.json -exclude_libraries -add_library sram -add_library gpio
+    sc-issue -cfg <stepdir>/outputs/<design>.pkg.json -exclude_libraries -add_library sram -add_library gpio
 
 To run a testcase, use:
     sc-issue -run -file sc_issue_<...>.tar.gz
@@ -39,10 +39,6 @@ To run a testcase, use:
 """  # noqa E501
 
     issue_arguments = {
-        '-generate': {'action': 'store_true',
-                      'help': 'generate a testcase',
-                      'sc_print': False},
-
         '-exclude_libraries': {'action': 'store_true',
                                'help': 'flag to ensure libraries are excluded in the testcase',
                                'sc_print': False},
@@ -88,10 +84,7 @@ To run a testcase, use:
         chip.logger.error(e)
         return 1
 
-    if switches['generate'] and switches['run']:
-        raise ValueError('Only one of -generate or -run can be used')
-
-    if switches['generate']:
+    if not switches['run']:
         step = chip.get('arg', 'step')
         index = chip.get('arg', 'index')
 

siliconcompiler/apps/smake.py

@@ -41,7 +41,20 @@ def __process_file(path):
             arg_type = str
             if arg in func_spec.annotations:
                 arg_type = func_spec.annotations[arg]
-            func_args[arg] = arg_type
+            func_args[arg] = {
+                "type": arg_type
+            }
+
+        if func_spec.defaults:
+            for arg, defval in zip(reversed(func_spec.args), reversed(func_spec.defaults)):
+                func_args[arg]["default"] = defval
+
+                if defval is None:
+                    continue
+
+                if type(defval) is not func_args[arg]["type"]:
+                    if isinstance(defval, (bool, str, float, int)):
+                        func_args[arg]["type"] = type(defval)
 
         args[name] = {
             "function": func,
@@ -62,7 +75,7 @@ def __process_file(path):
     return args, default_arg, module_help
 
 
-def main():
+def main(source_file=None):
     progname = "smake"
     description = f"""-----------------------------------------------------------
 SC app that provides an Makefile like interface to python
@@ -90,16 +103,18 @@ To run a target with supported arguments, use:
 -----------------------------------------------------------"""
 
     # handle source file identification before arg parse
-    source_file = __default_source_file
-    file_args = ('--file', '-f')
-    for file_arg in file_args:
-        if file_arg in sys.argv:
-            source_file_idx = sys.argv.index(file_arg) + 1
-            if source_file_idx < len(sys.argv):
-                source_file = sys.argv[source_file_idx]
-            else:
-                source_file = None
-            break
+    file_args = None
+    if not source_file:
+        source_file = __default_source_file
+        file_args = ('--file', '-f')
+        for file_arg in file_args:
+            if file_arg in sys.argv:
+                source_file_idx = sys.argv.index(file_arg) + 1
+                if source_file_idx < len(sys.argv):
+                    source_file = sys.argv[source_file_idx]
+                else:
+                    source_file = None
+                break
 
     # handle directory identification before arg parse
     source_dir = os.getcwd()
@@ -135,10 +150,11 @@ To run a target with supported arguments, use:
         description=description,
         formatter_class=argparse.RawDescriptionHelpFormatter)
 
-    parser.add_argument(
-        *file_args,
-        metavar='<file>',
-        help=f'Use file as makefile, default is {__default_source_file}')
+    if file_args:
+        parser.add_argument(
+            *file_args,
+            metavar='<file>',
+            help=f'Use file as makefile, default is {__default_source_file}')
 
     parser.add_argument(
         *dir_args,
@@ -159,14 +175,38 @@ To run a target with supported arguments, use:
         subparse = targetparsers.add_parser(
             arg,
             description=info['full_help'],
-            help=info['help'])
+            help=info['help'],
+            formatter_class=argparse.RawDescriptionHelpFormatter)
+
+        for subarg, subarg_info in info['args'].items():
+            # print(subarg, subarg_info)
+            add_args = {}
+
+            if "default" not in subarg_info:
+                add_args["required"] = True
+            else:
+                if type(subarg_info["default"]) is subarg_info["type"]:
+                    add_args["default"] = subarg_info["default"]
+
+            if subarg_info["type"] is bool:
+                def str2bool(v):
+                    # modified from:
+                    # https://github.com/pypa/distutils/blob/8993718731b951ee36d08cb784f02aa13542ce15/distutils/util.py
+                    val = v.lower()
+                    if val in ('y', 'yes', 't', 'true', 'on', '1'):
+                        return True
+                    elif val in ('n', 'no', 'f', 'false', 'off', '0'):
+                        return False
+                    else:
+                        raise ValueError(f"invalid truth value {val!r}")
+                subarg_info["type"] = str2bool
 
-        for subarg, subarg_type in info['args'].items():
             subparse.add_argument(
                 f'--{subarg}',
                 dest=f'sub_{subarg}',
                 metavar=f'<{subarg}>',
-                type=subarg_type)
+                type=subarg_info["type"],
+                **add_args)
 
     args = parser.parse_args()
     target = args.target

siliconcompiler/core.py

@@ -1001,8 +1001,8 @@ class Chip:
             package (str): Name of package where this file can be found
         '''
 
-        self.__add_input_output('input', filename, fileset, filetype, iomap,
-                                step=step, index=index, package=package)
+        self._add_input_output('input', filename, fileset, filetype, iomap,
+                               step=step, index=index, package=package)
     # Replace {iotable} in __doc__ with actual table for fileset/filetype and extension mapping
     input.__doc__ = input.__doc__.replace("{iotable}",
                                           utils.format_fileset_type_table())
@@ -1012,14 +1012,14 @@ class Chip:
                step=None, index=None, package=None):
         '''Same as input'''
 
-        self.__add_input_output('output', filename, fileset, filetype, iomap,
-                                step=step, index=index, package=package)
+        self._add_input_output('output', filename, fileset, filetype, iomap,
+                               step=step, index=index, package=package)
     # Copy input functions __doc__ and replace 'input' with 'output' to make constant
     output.__doc__ = input.__doc__.replace("input", "output")
 
     ###########################################################################
-    def __add_input_output(self, category, filename, fileset, filetype, iomap,
-                           step=None, index=None, package=None):
+    def _add_input_output(self, category, filename, fileset, filetype, iomap,
+                          step=None, index=None, package=None, quiet=False):
         '''
         Adds file to input or output groups.
         Performs a lookup in the io map for the fileset and filetype
@@ -1051,12 +1051,13 @@ class Chip:
         if not use_fileset or not use_filetype:
             self.logger.error(f'Unable to infer {category} fileset and/or filetype for '
                               f'{filename} based on file extension.')
-        elif not fileset and not filetype:
-            self.logger.info(f'{filename} inferred as {use_fileset}/{use_filetype}')
-        elif not filetype:
-            self.logger.info(f'{filename} inferred as filetype {use_filetype}')
-        elif not fileset:
-            self.logger.info(f'{filename} inferred as fileset {use_fileset}')
+        elif not quiet:
+            if not fileset and not filetype:
+                self.logger.info(f'{filename} inferred as {use_fileset}/{use_filetype}')
+            elif not filetype:
+                self.logger.info(f'{filename} inferred as filetype {use_filetype}')
+            elif not fileset:
+                self.logger.info(f'{filename} inferred as fileset {use_fileset}')
 
         self.add(category, use_fileset, use_filetype, filename,
                  step=step, index=index, package=package)
@@ -1946,7 +1947,7 @@ class Chip:
 
     ###########################################################################
     def write_dependencygraph(self, filename, flow=None,
-                              fillcolor='#ffffff', fontcolor='#000000',
+                              fontcolor='#000000', color_scheme=None,
                               background='transparent', fontsize='14',
                               border=True, landscape=False):
         r'''
@@ -1964,8 +1965,9 @@ class Chip:
         Args:
             filename (filepath): Output filepath
             flow (str): Name of flowgraph to render
-            fillcolor(str): Node fill RGB color hex value
             fontcolor (str): Node font RGB color hex value
+            color_scheme (str): Name of the color scheme to apply to the nodes.
+                Valid choices are: "none", "simple", "detailed"
             background (str): Background color
             fontsize (str): Node text font size
             border (bool): Enables node border if True
@@ -1981,6 +1983,33 @@ class Chip:
         fileroot, ext = os.path.splitext(filepath)
         fileformat = ext.replace(".", "")
 
+        color_schemes = {
+            "none": {
+                "design": "white",
+                "library": "white",
+                "logiclib": "white",
+                "macrolib": "white"
+            },
+            "simple": {
+                "design": "lightgreen",
+                "library": "white",
+                "logiclib": "lightgreen",
+                "macrolib": "lightgreen"
+            },
+            "detailed": {
+                "design": "lightgreen",
+                "library": "white",
+                "logiclib": "lightskyblue",
+                "macrolib": "lightgoldenrod2"
+            },
+        }
+
+        if not color_scheme:
+            color_scheme = "none"
+
+        if color_scheme not in color_schemes:
+            raise ValueError(f'{color_scheme} is not a valid color scheme')
+
         # controlling border width
         if border:
             penwidth = '1'
@@ -2006,7 +2035,7 @@ class Chip:
             nodes.add(node)
             dot.node(node, label=node, bordercolor=fontcolor, style='filled',
                      fontcolor=fontcolor, fontsize=fontsize, ordering="in",
-                     penwidth=penwidth, fillcolor=fillcolor)
+                     penwidth=penwidth, fillcolor="white")
             return node
 
         nodes = {}
@@ -2019,32 +2048,53 @@ class Chip:
             if root_label in nodes:
                 return
 
-            in_libs = lib.get('option', 'library',
-                              step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY) + \
-                lib.get('asic', 'logiclib',
-                        step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY) + \
-                lib.get('asic', 'macrolib',
-                        step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY)
-
             in_labels = []
-            for in_lib in in_libs:
+            for in_lib in lib.get('option', 'library',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
                 in_labels.append(f'library-{in_lib}')
+            for in_lib in lib.get('asic', 'logiclib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                in_labels.append(f'logiclib-{in_lib}')
+            for in_lib in lib.get('asic', 'macrolib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                in_labels.append(f'macrolib-{in_lib}')
+
+            shape = "oval"
+            if root_type == "logiclib":
+                shape = "box"
+            elif root_type == "macrolib":
+                shape = "box"
+            elif root_type == "design":
+                shape = "box"
+
+            color = color_schemes[color_scheme][root_type]
 
             nodes[root_label] = {
                 "text": name,
-                "shape": "oval" if root_type == "library" else "box",
+                "shape": shape,
+                "color": color,
                 "connects_to": set(in_labels)
             }
 
-            for in_lib in in_libs:
-                collect_library("library", Schema(cfg=self.getdict('library', in_lib)), name=in_lib)
+            for in_lib in lib.get('option', 'library',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                collect_library("library", Schema(cfg=self.getdict('library', in_lib)),
+                                name=in_lib)
+            for in_lib in lib.get('asic', 'logiclib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                collect_library("logiclib", Schema(cfg=self.getdict('library', in_lib)),
+                                name=in_lib)
+            for in_lib in lib.get('asic', 'macrolib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                collect_library("macrolib", Schema(cfg=self.getdict('library', in_lib)),
+                                name=in_lib)
 
         collect_library("design", self)
 
         for label, info in nodes.items():
             dot.node(label, label=info['text'], bordercolor=fontcolor, style='filled',
                      fontcolor=fontcolor, fontsize=fontsize, ordering="in",
-                     penwidth=penwidth, fillcolor=fillcolor, shape=info['shape'])
+                     penwidth=penwidth, fillcolor=info["color"], shape=info['shape'])
 
             for conn in info['connects_to']:
                 dot.edge(label, conn, dir='back')
@@ -2086,7 +2136,7 @@ class Chip:
                              step=r_step, index=r_index)
                 else:
                     self.set(*key,
-                             list(map(lambda x: x.replace(org_library, new_library), val)),
+                             list(map(lambda x: new_library if x == org_library else x, val)),
                              step=r_step, index=r_index)
             else:
                 for val, r_step, r_index in self.schema._getvals(*key):
@@ -2100,7 +2150,7 @@ class Chip:
                                  step=r_step, index=r_index)
                     else:
                         self.set(*key,
-                                 list(map(lambda x: x.replace(org_library, new_library), val)),
+                                 list(map(lambda x: new_library if x == org_library else x, val)),
                                  step=r_step, index=r_index)
 
         swap('option', 'library')

siliconcompiler/issue.py

@@ -153,6 +153,8 @@ def generate_testcase(chip,
     os.chdir(new_work_dir)
 
     # Rewrite replay.sh
+    prev_quiet = chip.get('option', 'quiet', step=step, index=index)
+    chip.set('option', 'quiet', True, step=step, index=index)
     from siliconcompiler import SiliconCompilerError
     try:
         # Rerun setup
@@ -167,6 +169,7 @@ def generate_testcase(chip,
                 pass
     except SiliconCompilerError:
         pass
+    chip.set('option', 'quiet', prev_quiet, step=step, index=index)
 
     flow = chip.get('option', 'flow')
     is_python_tool = hasattr(chip._get_task_module(step, index, flow=flow), 'run')

siliconcompiler/scheduler/__init__.py

@@ -201,7 +201,10 @@ def _local_process(chip, flow):
                                     f'{chip.design}.pkg.json')
             if os.path.exists(manifest):
                 # ensure we setup these nodes again
-                extra_setup_nodes[(step, index)] = Schema(manifest=manifest, logger=chip.logger)
+                try:
+                    extra_setup_nodes[(step, index)] = Schema(manifest=manifest, logger=chip.logger)
+                except Exception:
+                    pass
 
     # Setup tools for all nodes to run.
     nodes = nodes_to_execute(chip, flow)

siliconcompiler/templates/tcl/manifest.tcl.j2

@@ -83,3 +83,55 @@ proc sc_section_banner { text { method puts } } {
     $method "| $text"
     $method "============================================================"
 }
+
+# Get list of soft libraries
+proc sc_get_libraries { {library {}} {libraries {}} } {
+    set key []
+    if { [llength $library] != 0 } {
+        lappend key library $library
+    }
+    lappend key option library
+
+    set libs []
+    foreach lib [sc_cfg_get {*}$key] {
+        if { [lsearch -exact $libs $lib] != -1 || [lsearch -exact $libraries $lib] != -1 } {
+            continue
+        }
+
+        lappend libs $lib
+
+        foreach sublib [sc_get_libraries $lib $libs] {
+            lappend libs $sublib
+        }
+    }
+
+    return [lsort -unique $libs]
+}
+
+# Get list of asic libraries
+proc sc_get_asic_libraries { type } {
+    set libs []
+
+    foreach lib [sc_cfg_get asic ${type}lib] {
+        if { [lsearch -exact $libs $lib] != -1 } {
+            continue
+        }
+        lappend libs $lib
+    }
+
+    foreach lib [sc_get_libraries] {
+        if { ![sc_cfg_exists library $lib asic ${type}lib] } {
+            continue
+        }
+
+        foreach sublib [sc_cfg_get library $lib asic ${type}lib] {
+            if { [lsearch -exact $libs $sublib] != -1 } {
+                continue
+            }
+
+            lappend libs $sublib
+        }
+    }
+
+    return $libs
+}

siliconcompiler/tools/_common/__init__.py

@@ -1,7 +1,5 @@
 import os
 import pkgutil
-from siliconcompiler.utils import get_file_ext
-from siliconcompiler import units, SiliconCompilerError, NodeStatus
 
 
 def get_libraries(chip, include_asic=True, library=None, libraries=None):
@@ -159,6 +157,8 @@ def __get_keys(chip, *key, include_library_files=True):
 
 
 def __assert_support(chip, opt_keys, supports):
+    from siliconcompiler import SiliconCompilerError
+
     if not supports:
         supports = []
 
@@ -255,6 +255,8 @@ def get_frontend_options(chip, supports=None):
 
 
 def find_incoming_ext(chip, support_exts, default_ext):
+    from siliconcompiler.utils import get_file_ext
+
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
     flow = chip.get('option', 'flow')
@@ -302,6 +304,8 @@ def pick_key(chip, check_keys, step=None, index=None):
 
 
 def input_provides(chip, step, index, flow=None):
+    from siliconcompiler import NodeStatus
+
     if not flow:
         flow = chip.get('option', 'flow')
 
@@ -323,6 +327,8 @@ def input_provides(chip, step, index, flow=None):
 
 
 def input_file_node_name(filename, step, index):
+    from siliconcompiler.utils import get_file_ext
+
     file_type = get_file_ext(filename)
 
     base = filename
@@ -408,6 +414,8 @@ def record_metric(chip, step, index, metric, value, source, source_unit=None):
         Records the metric cell area under 'floorplan0' and notes the source as
         'reports/metrics.json'
     '''
+    from siliconcompiler import units
+
     metric_unit = None
     if chip.schema.has_field('metric', metric, 'unit'):
         metric_unit = chip.get('metric', metric, field='unit')

siliconcompiler/tools/_common/asic.py

@@ -1,12 +1,32 @@
-from siliconcompiler.tools._common import pick_key
-from siliconcompiler.tools._common import get_tool_task
+from .. import _common
 
 
 def get_mainlib(chip):
+    return get_libraries(chip, 'logic')[0]
+
+
+def get_libraries(chip, type):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    logiclibs = chip.get('asic', 'logiclib', step=step, index=index)
-    return logiclibs[0]
+
+    if type not in ('logic', 'macro'):
+        raise ValueError(f'Cannot collect {type} libraries')
+
+    libs = []
+    for lib in chip.get('asic', f'{type}lib', step=step, index=index):
+        if lib in libs:
+            continue
+        libs.append(lib)
+
+    for lib in _common.get_libraries(chip, include_asic=False):
+        if not chip.valid('library', lib, 'asic', f'{type}lib'):
+            continue
+        for sublib in chip.get('library', lib, 'asic', f'{type}lib', step=step, index=index):
+            if sublib in libs:
+                continue
+            libs.append(sublib)
+
+    return libs
 
 
 def get_timing_modes(chip):
@@ -33,7 +53,7 @@ def set_tool_task_var(chip,
     '''
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    tool, task = get_tool_task(chip, step, index)
+    tool, task = _common.get_tool_task(chip, step, index)
     pdkname = chip.get('option', 'pdk')
     stackup = chip.get('option', 'stackup')
     mainlib = get_mainlib(chip)
@@ -72,7 +92,7 @@ def set_tool_task_var(chip,
                  ','.join(check_keys[-1]),
                  step=step, index=index)
 
-    require_key, value = pick_key(chip, reversed(check_keys), step=step, index=index)
+    require_key, value = _common.pick_key(chip, reversed(check_keys), step=step, index=index)
     if not value:
         value = default_value
 

siliconcompiler/tools/klayout/export.py

@@ -2,6 +2,7 @@
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
 from siliconcompiler.tools.klayout.screenshot import setup_gui_screenshot
 from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools._common.asic import get_libraries
 
 
 def setup(chip):
@@ -23,7 +24,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=clobber)
 
-    targetlibs = chip.get('asic', 'logiclib', step=step, index=index)
+    targetlibs = get_libraries(chip, 'logic')
     stackup = chip.get('option', 'stackup')
     pdk = chip.get('option', 'pdk')
 
@@ -39,7 +40,7 @@ def setup(chip):
     sc_stream_order = [default_stream, *[s for s in streams if s != default_stream]]
 
     if stackup and targetlibs:
-        macrolibs = chip.get('asic', 'macrolib', step=step, index=index)
+        macrolibs = get_libraries(chip, 'macro')
 
         chip.add('tool', tool, 'task', task, 'require', ",".join(['asic', 'logiclib']),
                  step=step, index=index)

siliconcompiler/tools/klayout/klayout_export.py

@@ -124,7 +124,8 @@ def main():
         save_technology,
         get_schema
     )
-    from tools.klayout.klayout_show import show  # noqa E402
+    from tools.klayout.klayout_show import show
+    from tools._common.asic import get_libraries
 
     schema = get_schema(manifest='sc_manifest.json')
 
@@ -158,9 +159,8 @@ def main():
 
     out_file = os.path.join('outputs', f'{design}.{sc_stream}')
 
-    libs = schema.get('asic', 'logiclib', step=sc_step, index=sc_index)
-    if 'macrolib' in schema.getkeys('asic'):
-        libs += schema.get('asic', 'macrolib', step=sc_step, index=sc_index)
+    libs = get_libraries(schema, 'logic')
+    libs += get_libraries(schema, 'macro')
 
     in_files = []
     for lib in libs:

siliconcompiler/tools/klayout/klayout_utils.py

@@ -21,6 +21,8 @@ def get_streams(schema):
 
 
 def technology(design, schema):
+    from tools._common.asic import get_libraries
+
     sc_step = schema.get('arg', 'step')
     sc_index = schema.get('arg', 'index')
     sc_pdk = schema.get('option', 'pdk')
@@ -33,10 +35,8 @@ def technology(design, schema):
     sc_libtype = schema.get('library', sc_mainlib, 'asic', 'libarch', step=sc_step, index=sc_index)
 
     sc_libs = []
-    if 'logiclib' in schema.getkeys('asic'):
-        sc_libs.extend(schema.get('asic', 'logiclib', step=sc_step, index=sc_index))
-    if 'macrolib' in schema.getkeys('asic'):
-        sc_libs.extend(schema.get('asic', 'macrolib', step=sc_step, index=sc_index))
+    sc_libs += get_libraries(schema, 'logic')
+    sc_libs += get_libraries(schema, 'macro')
 
     local_files = {
         'lyt': f'inputs/{design}.lyt',

siliconcompiler/tools/magic/sc_drc.tcl

@@ -20,7 +20,7 @@ set sc_index   [sc_cfg_get arg index]
 set sc_task    $sc_step
 
 set sc_design    [sc_top]
-set sc_macrolibs [sc_cfg_get asic macrolib]
+set sc_macrolibs [sc_get_asic_libraries macro]
 set sc_stackup   [sc_cfg_get option stackup]
 
 if { [sc_cfg_tool_task_exists var exclude] } {

siliconcompiler/tools/magic/sc_extspice.tcl

@@ -5,13 +5,14 @@ set sc_index   [sc_cfg_get arg index]
 set sc_task    $sc_step
 
 set sc_design [sc_top]
-set sc_mainlib [sc_cfg_get asic logiclib]
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_mainlib [lindex $sc_logiclibs 0]
 set sc_stackup [sc_cfg_get option stackup]
 set sc_pdk [sc_cfg_get option pdk]
 set sc_libtype [sc_cfg_get library $sc_mainlib asic libarch]
 set sc_techlef [sc_cfg_get pdk $sc_pdk aprtech magic $sc_stackup $sc_libtype lef]
 set sc_liblef [sc_cfg_get library $sc_mainlib output $sc_stackup lef]
-set sc_macrolibs [sc_cfg_get asic macrolib]
+set sc_macrolibs [sc_get_asic_libraries macro]
 
 if { [sc_cfg_tool_task_exists var exclude] } {
     set sc_exclude [sc_cfg_tool_task_get var exclude]

siliconcompiler/tools/netgen/sc_lvs.tcl

@@ -5,7 +5,7 @@ set sc_index   [sc_cfg_get arg index]
 set sc_task    $sc_step
 
 set sc_design [sc_top]
-set sc_macrolibs [sc_cfg_get asic macrolib]
+set sc_macrolibs [sc_get_asic_libraries macro]
 set sc_stackup [sc_cfg_get option stackup]
 set sc_pdk [sc_cfg_get option pdk]
 set sc_runset [sc_cfg_get pdk $sc_pdk lvs runset netgen $sc_stackup basic]

siliconcompiler/tools/openroad/export.py

@@ -3,7 +3,7 @@ from siliconcompiler.tools.openroad.openroad import setup as setup_tool
 from siliconcompiler.tools.openroad.openroad import build_pex_corners
 from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
 from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
-from siliconcompiler.tools._common.asic import set_tool_task_var
+from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries
 from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
 from siliconcompiler.tools._common import get_tool_task
 
@@ -34,8 +34,8 @@ def setup(chip):
     stackup = chip.get('option', 'stackup')
     pdk = chip.get('option', 'pdk')
 
-    targetlibs = chip.get('asic', 'logiclib', step=step, index=index)
-    macrolibs = chip.get('asic', 'macrolib', step=step, index=index)
+    targetlibs = get_libraries(chip, 'logic')
+    macrolibs = get_libraries(chip, 'macro')
 
     # Determine if exporting the cdl
     set_tool_task_var(chip, param_key='write_cdl',

siliconcompiler/tools/openroad/openroad.py

@@ -17,7 +17,7 @@ from siliconcompiler import sc_open
 from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, add_common_file, \
     get_tool_task, record_metric
-from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var
+from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var, get_libraries
 
 
 ####################################################################
@@ -61,9 +61,9 @@ def setup(chip):
     index = chip.get('arg', 'index')
     _, task = get_tool_task(chip, step, index)
     pdkname = chip.get('option', 'pdk')
-    targetlibs = chip.get('asic', 'logiclib', step=step, index=index)
+    targetlibs = get_libraries(chip, 'logic')
     mainlib = get_mainlib(chip)
-    macrolibs = chip.get('asic', 'macrolib', step=step, index=index)
+    macrolibs = get_libraries(chip, 'macro')
     stackup = chip.get('option', 'stackup')
     delaymodel = chip.get('asic', 'delaymodel', step=step, index=index)
     libtype = chip.get('library', mainlib, 'asic', 'libarch', step=step, index=index)
@@ -210,8 +210,8 @@ def pre_process(chip):
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
     pdkname = chip.get('option', 'pdk')
-    targetlibs = chip.get('asic', 'logiclib', step=step, index=index)
-    macrolibs = chip.get('asic', 'macrolib', step=step, index=index)
+    targetlibs = get_libraries(chip, 'logic')
+    macrolibs = get_libraries(chip, 'macro')
     mainlib = get_mainlib(chip)
     stackup = chip.get('option', 'stackup')
     libtype = chip.get('library', mainlib, 'asic', 'libarch', step=step, index=index)

siliconcompiler/tools/openroad/scripts/sc_apr.tcl

@@ -69,7 +69,7 @@ set sc_pdk        [sc_cfg_get option pdk]
 set sc_stackup    [sc_cfg_get option stackup]
 
 # APR Parameters
-set sc_targetlibs  [sc_cfg_get asic logiclib]
+set sc_targetlibs  [sc_get_asic_libraries logic]
 set sc_mainlib     [lindex $sc_targetlibs 0]
 set sc_delaymodel  [sc_cfg_get asic delaymodel]
 set sc_pdk_vars    [sc_cfg_get pdk $sc_pdk {var} $sc_tool]
@@ -117,7 +117,7 @@ if { [sc_cfg_tool_task_exists {var} dont_touch] } {
 ###############################
 
 # MACROS
-set sc_macrolibs [sc_cfg_get asic macrolib]
+set sc_macrolibs [sc_get_asic_libraries macro]
 
 ###############################
 # Setup debugging if requested

siliconcompiler/tools/opensta/__init__.py

@@ -11,6 +11,7 @@ Installation: https://github.com/The-OpenROAD-Project/OpenSTA (also installed wi
 import os
 from siliconcompiler.tools.openroad.openroad import get_library_timing_keypaths
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools._common.asic import get_libraries
 
 
 ####################################################################
@@ -33,8 +34,8 @@ def setup(chip):
     chip.set('tool', tool, 'version', '>=v2.5.0', clobber=False)
     chip.set('tool', tool, 'format', 'tcl')
 
-    targetlibs = chip.get('asic', 'logiclib', step=step, index=index)
-    macrolibs = chip.get('asic', 'macrolib', step=step, index=index)
+    targetlibs = get_libraries(chip, 'logic')
+    macrolibs = get_libraries(chip, 'macro')
     delaymodel = chip.get('asic', 'delaymodel', step=step, index=index)
 
     # Input/Output requirements for default asicflow steps

siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl

@@ -20,7 +20,7 @@ set sc_refdir [sc_cfg_tool_task_get refdir]
 set sc_design [sc_top]
 
 # APR Parameters
-set sc_targetlibs [sc_cfg_get asic logiclib]
+set sc_targetlibs [sc_get_asic_libraries logic]
 set sc_delaymodel [sc_cfg_get asic delaymodel]
 set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
 
@@ -29,7 +29,7 @@ set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
 ###############################
 
 # MACROS
-set sc_macrolibs [sc_cfg_get asic macrolib]
+set sc_macrolibs [sc_get_asic_libraries macro]
 
 ###############################
 # Read Files

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -20,7 +20,7 @@ set sc_refdir [sc_cfg_tool_task_get refdir]
 set sc_design [sc_top]
 
 # APR Parameters
-set sc_targetlibs [sc_cfg_get asic logiclib]
+set sc_targetlibs [sc_get_asic_libraries logic]
 set sc_mainlib [lindex $sc_targetlibs 0]
 set sc_delaymodel [sc_cfg_get asic delaymodel]
 set sc_timing_mode [lindex [sc_cfg_tool_task_get var timing_mode] 0]
@@ -36,7 +36,7 @@ foreach corner [dict keys [sc_cfg_get constraint timing]] {
 ###############################
 
 # MACROS
-set sc_macrolibs [sc_cfg_get asic macrolib]
+set sc_macrolibs [sc_get_asic_libraries macro]
 
 ###############################
 # Read Files

siliconcompiler/tools/yosys/sc_lec.tcl

@@ -13,7 +13,7 @@ set sc_task   [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
 set sc_refdir [sc_cfg_tool_task_get refdir ]
 
 set sc_design      [sc_top]
-set sc_targetlibs  [sc_cfg_get asic logiclib]
+set sc_targetlibs  [sc_get_asic_libraries logic]
 
 # TODO: properly handle complexity here
 set lib [lindex $sc_targetlibs 0]

siliconcompiler/tools/yosys/syn_asic.py

@@ -5,7 +5,7 @@ import re
 import siliconcompiler.tools.yosys.prepareLib as prepareLib
 from siliconcompiler import sc_open
 from siliconcompiler import utils
-from siliconcompiler.tools._common.asic import set_tool_task_var
+from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib
 from siliconcompiler.tools._common import get_tool_task
 
 
@@ -47,13 +47,13 @@ def setup_asic(chip):
 
     if syn_corners is not None:
         # add timing library requirements
-        for lib in chip.get('asic', 'logiclib', step=step, index=index):
+        for lib in get_libraries(chip, 'logic'):
             # mandatory for logiclibs
             chip.add('tool', tool, 'task', task, 'require',
                      ",".join(_get_synthesis_library_key(chip, lib, syn_corners)),
                      step=step, index=index)
 
-        for lib in chip.get('asic', 'macrolib', step=step, index=index):
+        for lib in get_libraries(chip, 'macro'):
             # optional for macrolibs
             if chip.valid(*_get_synthesis_library_key(chip, lib, syn_corners)):
                 chip.add('tool', tool, 'task', task, 'require',
@@ -70,8 +70,7 @@ def setup_asic(chip):
                  step=step, index=index)
 
     # set default control knobs
-    logiclibs = chip.get('asic', 'logiclib', step=step, index=index)
-    mainlib = logiclibs[0]
+    mainlib = get_mainlib(chip)
     for option, value in [
             ('flatten', "true"),
             ('hier_iterations', "10"),
@@ -233,8 +232,8 @@ def prepare_synthesis_libraries(chip):
             return chip.find_files(*keypath, step=step, index=index)
         return []
 
-    for libtype in ('logiclib', 'macrolib'):
-        for lib in chip.get('asic', libtype, step=step, index=index):
+    for libtype in ('logic', 'macro'):
+        for lib in get_libraries(chip, libtype):
             lib_content = {}
             # Mark dont use
             for lib_file in get_synthesis_libraries(lib):
@@ -260,7 +259,7 @@ def prepare_synthesis_libraries(chip):
                 continue
 
             var_name = 'synthesis_libraries'
-            if libtype == "macrolib":
+            if libtype == "macro":
                 var_name = 'synthesis_libraries_macros'
 
             for file, content in lib_content.items():
@@ -380,7 +379,7 @@ def get_dff_liberty_file(chip):
         if dff_liberty:
             return dff_liberty[0]
 
-    mainlib = chip.get('asic', 'logiclib', step=step, index=index)[0]
+    mainlib = get_mainlib(chip)
     if chip.valid('library', mainlib, 'option', 'file', 'yosys_dff_liberty'):
         dff_liberty = chip.find_files('library', mainlib, 'option', 'file', 'yosys_dff_liberty')
         if dff_liberty:
@@ -391,7 +390,7 @@ def get_dff_liberty_file(chip):
         return None
 
     # if dff liberty file is not set, use the first liberty file defined
-    for lib in chip.get('asic', 'logiclib', step=step, index=index):
+    for lib in get_libraries(chip, 'logic'):
         if not chip.valid(*_get_synthesis_library_key(chip, lib, corners)):
             continue
 
@@ -410,8 +409,7 @@ def get_abc_period(chip):
     index = chip.get('arg', 'index')
     _, task = get_tool_task(chip, step, index)
 
-    logiclibs = chip.get('asic', 'logiclib', step=step, index=index)
-    mainlib = logiclibs[0]
+    mainlib = get_mainlib(chip)
 
     abc_clock_period = chip.get('tool', tool, 'task', task, 'var', 'abc_clock_period',
                                 step=step, index=index)
@@ -507,7 +505,7 @@ def get_abc_driver(chip):
 
     abc_driver = None
     # get the first driver defined in the logic lib
-    for lib in chip.get('asic', 'logiclib', step=step, index=index):
+    for lib in get_libraries(chip, 'logic'):
         if chip.valid('library', lib, 'option', 'var', 'yosys_driver_cell') and not abc_driver:
             abc_driver = chip.get('library', lib, 'option', 'var', 'yosys_driver_cell')[0]
 
@@ -524,8 +522,8 @@ def pre_process(chip):
     tool, task = get_tool_task(chip, step, index)
 
     # copy techmapping from libraries
-    logiclibs = chip.get('asic', 'logiclib', step=step, index=index)
-    macrolibs = chip.get('asic', 'macrolib', step=step, index=index)
+    logiclibs = get_libraries(chip, 'logic')
+    macrolibs = get_libraries(chip, 'macro')
     for lib in logiclibs + macrolibs:
         if not chip.valid('library', lib, 'option', 'file', 'yosys_techmap'):
             continue

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -82,8 +82,8 @@ proc determine_keep_hierarchy { iter cell_limit } {
 # DESIGNER's CHOICE
 ####################
 
-set sc_logiclibs        [sc_cfg_get asic logiclib]
-set sc_macrolibs        [sc_cfg_get asic macrolib]
+set sc_logiclibs        [sc_get_asic_libraries logic]
+set sc_macrolibs        [sc_get_asic_libraries macro]
 
 set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
 if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
@@ -100,7 +100,7 @@ set sc_abc_constraints \
     [lindex [sc_cfg_tool_task_get {file} abc_constraint_file] 0]
 
 set sc_blackboxes []
-foreach lib [sc_cfg_get asic macrolib] {
+foreach lib $sc_macrolibs {
     if { [sc_cfg_exists library $lib output blackbox verilog] } {
         foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
             lappend sc_blackboxes $lib_f

siliconcompiler/use.py

@@ -61,6 +61,18 @@ class PackageChip(Chip):
         super().set(*args, field=field, clobber=clobber, step=step,
                     index=index, package=package)
 
+    def input(self, filename, fileset=None, filetype=None, iomap=None,
+              step=None, index=None, package=None):
+        self._add_input_output('input', filename, fileset, filetype, iomap,
+                               step=step, index=index, package=package,
+                               quiet=True)
+
+    def output(self, filename, fileset=None, filetype=None, iomap=None,
+               step=None, index=None, package=None):
+        self._add_input_output('output', filename, fileset, filetype, iomap,
+                               step=step, index=index, package=package,
+                               quiet=True)
+
 
 class PDK(PackageChip):
     """

{siliconcompiler-0.26.2.dist-info → siliconcompiler-0.26.3.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.26.2
+Version: 0.26.3
 Summary: A compiler framework that automates translation from source code to silicon.
 Home-page: https://siliconcompiler.com
 Author: Andreas Olofsson
@@ -13,7 +13,7 @@ Project-URL: Forum, https://github.com/siliconcompiler/siliconcompiler/discussio
 Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
-Requires-Dist: aiohttp==3.10.3
+Requires-Dist: aiohttp==3.10.4
 Requires-Dist: requests==2.32.3
 Requires-Dist: PyYAML==6.0.2
 Requires-Dist: pandas>=1.1.5

{siliconcompiler-0.26.2.dist-info → siliconcompiler-0.26.3.dist-info}/RECORD

@@ -1,22 +1,22 @@
 siliconcompiler/__init__.py,sha256=5T-mWDc05v0FEdwg2btphrAb_W7XaXUmKrRSxuSMNUQ,535
 siliconcompiler/__main__.py,sha256=x5bzv4spw66iQOldUM-iCWw2j5NxXkkkC_Wd2hGAAgo,182
 siliconcompiler/_common.py,sha256=27VU0PqZkD6-qz20brjzj-Z8cpDt0oyE6ZA6wARZvrk,1283
-siliconcompiler/_metadata.py,sha256=5iZ0pjqLzkXPlr1gUJdCplJcnKsEV2H2WFx6X6P9-e4,1300
-siliconcompiler/core.py,sha256=fnA9eJ7BAuPLuugRglbmjSM38OXIWzrYJDmaEeEjC8U,128904
+siliconcompiler/_metadata.py,sha256=iO0XbuLpdQ8M_UIUfaYtJpaP2jX2xzy1DsX5ysoAZW0,1300
+siliconcompiler/core.py,sha256=nEi-kSkVsI3LcaYHeKm7avXTUqQFvsBZlQ521ORVa1E,131000
 siliconcompiler/flowgraph.py,sha256=aQh0VO7LVwGNJbWZcBIgzGRv_pDH72_ilMQtK906Rqk,22502
-siliconcompiler/issue.py,sha256=jrQnDKY9G-k-KF61XkhPyLSDmOSBoWA2GHRxB4auKNA,11223
+siliconcompiler/issue.py,sha256=wRRG3b5bz8IdcT__hJME1svZwbsh_fGQr4VR8sTnta8,11425
 siliconcompiler/package.py,sha256=Z2FqMRq8mtvmF6d_hyDOZN8DOZ8gu7zABDMWOfUGu-M,14463
 siliconcompiler/units.py,sha256=dYn185TzusMtBd69RFKhNlCky2td5jC__AJdPjqXELU,6069
-siliconcompiler/use.py,sha256=InIDvKtlr3iwo8w3hVxzATjTyN8JQGzelZbs5tioMqo,5630
+siliconcompiler/use.py,sha256=U0-GMomi5y5uS6yYtAyZ7ZcpMElK61glyscXhrMq8nA,6275
 siliconcompiler/apps/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/apps/_common.py,sha256=368PjPwz0yw4baJOXPOhkgVq0uP_G77j5C6ei_eIaPs,2565
 siliconcompiler/apps/sc.py,sha256=2LT0rvky_3SRpsvbmZ68asAvGdagIIEW7fwMoCqVpUE,2876
 siliconcompiler/apps/sc_dashboard.py,sha256=paGJ07MQBOzekEs1mZ2mMsl-snt5qaLwHQ36rNU5FRo,3269
-siliconcompiler/apps/sc_issue.py,sha256=BJSj9kgwvtJQCsudjiuHfPguLpZR1QAuQRTyxfEAKHE,7410
+siliconcompiler/apps/sc_issue.py,sha256=9p4QW297Fmc9rY1wBahJbuLjks2IsMTEW0bhfRW6uww,7110
 siliconcompiler/apps/sc_remote.py,sha256=9m6g79STJG784NqzMHyxoPzexZ7ihZaYxxxLlg7cnQk,7522
 siliconcompiler/apps/sc_server.py,sha256=aeW9wldn_qO6yyv9j5drx2wv0KMk8f6s9XSZgPCerhY,933
 siliconcompiler/apps/sc_show.py,sha256=ykP-yUOViD64DRb2jR-E-v4cI6OOCw57XdWYLze-yBM,4702
-siliconcompiler/apps/smake.py,sha256=uN8COdCcvlpRp-TBA2oqC5t4-ISg7YB5XWOBXC_r6Vw,5663
+siliconcompiler/apps/smake.py,sha256=ZXv3HoouVhYewkmZ4Zu0e-3zeSq7NBnPbbpbaFP1AGg,7356
 siliconcompiler/checklists/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/checklists/oh_tapeout.py,sha256=ZJsCktTZ9uX94IQEWwxt9gBKGeXXsWQKXg0rM9fpKc0,1492
 siliconcompiler/data/heartbeat.v,sha256=1hOB1OhZOEF7f8WKTzOYgYtkdVL6yNI4Ou4fmVuApPU,438
@@ -73,7 +73,7 @@ siliconcompiler/report/streamlit_viewer.py,sha256=WbwcEf2t1gQihUnxnefwlAXKThwcNd
 siliconcompiler/report/summary_image.py,sha256=r8GbFJgD0ZLfYFFl8nmUhsh87wWP7evCljWWHx7_L8U,3687
 siliconcompiler/report/summary_table.py,sha256=NfSB8yHFirSCxvBROXURLzZM4UrYN2M050CScjeuFYk,2997
 siliconcompiler/report/utils.py,sha256=Yr-vcCoylN3HvlqAK0l6LLgdHfauezCmAhCzVqiHHpU,6603
-siliconcompiler/scheduler/__init__.py,sha256=4ab-Wc4LSy8HTWAkxYn474pTudHyvZq8q2a_s42k7-Y,82167
+siliconcompiler/scheduler/__init__.py,sha256=0vwjttIOHxMBJBtYKgP9i4JE9DqPjbJ5j-kvcTutx30,82254
 siliconcompiler/scheduler/docker_runner.py,sha256=ZboFmi9C_TPkgQlizU3nLmdDUip5EqvN-1JoJZMFFTs,8318
 siliconcompiler/scheduler/run_node.py,sha256=Mmj2epARKCuwN6oW-PyvExwY3OzRxUrG0mPLr3SwQ6M,5201
 siliconcompiler/scheduler/send_messages.py,sha256=ZVO6923-EJWUMlDOOpLEhaSrsKtP-d4J_UcfRp6kJDo,6387
@@ -103,10 +103,10 @@ siliconcompiler/templates/report/bootstrap.min.js,sha256=SUzPu-ewjZCj6CtwVs9sNh6
 siliconcompiler/templates/report/bootstrap_LICENSE.md,sha256=TJ-04Mng2-4AwtDgSPSE83IR6NWZ5M3I4IwvAsGM6Bg,1237
 siliconcompiler/templates/report/sc_report.j2,sha256=o6S1pwkPEYSIcw2fJaOVSflkGsFaX4uqr3A-paJeogw,17553
 siliconcompiler/templates/slurm/run.sh,sha256=Il7hoBLXXaCU6gSELRUkmFYh98CLUNt0-rw1e26CCOE,223
-siliconcompiler/templates/tcl/manifest.tcl.j2,sha256=EMTCgHgEje8r0G1ZuYrCtq0A7xgAQSwrvMvgcalXx7o,2376
+siliconcompiler/templates/tcl/manifest.tcl.j2,sha256=z9ewphEvJmV4156-Kw17Ikl4EZQsV8Jopg7TCkALUHY,3601
 siliconcompiler/tools/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
-siliconcompiler/tools/_common/__init__.py,sha256=l2LYD0tSOUY283Z5Ib3RXfKky9IgiP0KIsPrH2xI9aY,13839
-siliconcompiler/tools/_common/asic.py,sha256=2VqtNV-o0lmCNMT7wm-i_IbfbTA6Qxr3wXfopuGTNWQ,3163
+siliconcompiler/tools/_common/__init__.py,sha256=uJ1Nlee8QK_X-MqbgBrkr-MvQZivydpK1ngnxfxjXGA,13973
+siliconcompiler/tools/_common/asic.py,sha256=Cj8f88kLfMaHZhbbJHLGL1V9Tp1WCjpFr_1VrT2uNjE,3705
 siliconcompiler/tools/_common/sdc/sc_constraints.sdc,sha256=4Pmema9zkVpHHRGkLUZxnz9RIW4flfq2MfwEirBv-CY,2903
 siliconcompiler/tools/_common/tcl/sc_pin_constraints.tcl,sha256=nHzkcos2sjI-ENYmvB03lLsS9YHcfvC_Aute16vTJqg,2134
 siliconcompiler/tools/bambu/bambu.py,sha256=_rYmzIeQZKa_9inG5tNMotB8c6mngG7QKTxwTR7aLvI,1191
@@ -136,36 +136,36 @@ siliconcompiler/tools/icarus/compile.py,sha256=BWpGQeaTTlmuk28_oZa3IhTnlUanxglKX
 siliconcompiler/tools/icarus/icarus.py,sha256=d2yeS8Jww1iWa8xn2aQrkgDxzUwVLZiHw_q7mvk-TOY,947
 siliconcompiler/tools/icepack/bitstream.py,sha256=o61FD4wiz27yc-GkI50omeQ7mbvQoV6ZwZMQEJ03fTs,661
 siliconcompiler/tools/icepack/icepack.py,sha256=-ExNT8VEY8Qqe4XOvEa_L9POYCxlZz0kPm1e_fS3HJ8,1052
-siliconcompiler/tools/klayout/export.py,sha256=3qz8xVLBGhvWHk8F8C_Nw9p81UlC6hy4FL4gArX1Dxo,5325
+siliconcompiler/tools/klayout/export.py,sha256=_oe4w5oMUaqzU5rr_0RSsfrZpK3ZNN18z00TCILoebI,5339
 siliconcompiler/tools/klayout/klayout.py,sha256=ybAoS172902Sg0hw_ltNxTPTrwMSkgPJae4-V4mVdlI,4630
-siliconcompiler/tools/klayout/klayout_export.py,sha256=frVYGhHNPhSkVxT63Ls6KnyQNYCNfKAZIBHaYBvWtUY,8204
+siliconcompiler/tools/klayout/klayout_export.py,sha256=HqWakb2wUc5XNyidxCT9pTUrYspNNopUgs2coQyPjBE,8131
 siliconcompiler/tools/klayout/klayout_operations.py,sha256=hWBWuoNCIvadD1twAEF-N9E422cl3GYgARv_Id82Kl8,13417
 siliconcompiler/tools/klayout/klayout_show.py,sha256=Mvy1uQc57ul_OdGiBdquKWU7IYT6lrom7H51Wty8HmY,9369
-siliconcompiler/tools/klayout/klayout_utils.py,sha256=hCFzRZiXMlIQrKNvcns3U_F_rSvM5TcqgiOrsPuviRQ,6699
+siliconcompiler/tools/klayout/klayout_utils.py,sha256=8-Go3yYlRD1MU5wfBXzeT27DiDwoEb13N_34MbCfuwM,6581
 siliconcompiler/tools/klayout/operations.py,sha256=QxvlqPfGNv0WZs-b4qycMkrb4y69ft4Bctcsi5sVRQk,7947
 siliconcompiler/tools/klayout/screenshot.py,sha256=SpesVl1jUXDHudIJ3tLMTVrka6aaln5JETW5EjUt1Oc,3891
 siliconcompiler/tools/klayout/show.py,sha256=PtiD8aXeU8t1xbSghwHK4F3slcH3ZFipeWbHQhrvbVQ,3938
 siliconcompiler/tools/magic/drc.py,sha256=BT9jbELdUJDW0-WrDsK_nX-jDkFv-MC738bG0BIYCU0,1300
 siliconcompiler/tools/magic/extspice.py,sha256=3043bLVCHYEed_Kj_CjpMEXgX9OyNJEQTni9GzkkrvI,543
 siliconcompiler/tools/magic/magic.py,sha256=MRdRO9bXRMPAOECuxquVQxuFnYckiWljwD-GE5PS_HI,2813
-siliconcompiler/tools/magic/sc_drc.tcl,sha256=ia-bl4QKK-_V7G_M0PYKVibdXKeoyBJagSWA7cf4W0g,3021
-siliconcompiler/tools/magic/sc_extspice.tcl,sha256=xj-qlcdcxBpLmycqsUPE6bKGr3xT5zm2GexwD3feFuI,1449
+siliconcompiler/tools/magic/sc_drc.tcl,sha256=wcsOLdqeDtrSViXyUPVSftJ4YzweBGVW4xF6jHhyRgo,3024
+siliconcompiler/tools/magic/sc_extspice.tcl,sha256=HeCMxnn7SnqdG05Qu2Hee9DhOVxK98SqhfEm_ftq1aU,1498
 siliconcompiler/tools/magic/sc_magic.tcl,sha256=10pU1o2bCsjoT8eAZsO0HmrSlVUViNpQeX1PrAAVyZ4,1184
 siliconcompiler/tools/montage/montage.py,sha256=tbezLe1PK9rdKnijBnBEjf0BhshgwGtpKG_SY-NLCuw,982
 siliconcompiler/tools/montage/tile.py,sha256=Sh8APUQMA-G2s8l54dTm5X1BaDPkOtSg1qzCtdXNOzE,2386
 siliconcompiler/tools/netgen/count_lvs.py,sha256=O-zMY4gxfnCH97UX0gOiZlIym87AN5dx8IrM54PkKTg,4787
 siliconcompiler/tools/netgen/lvs.py,sha256=W4OU16dcX6ZxWWtcEBrFJPvcgjsBxYcY58P_ku71CFk,3485
 siliconcompiler/tools/netgen/netgen.py,sha256=PTR5SLoB8n2r4ts4XVOGsTfL5bAeGqycXNW4kKqKhHQ,986
-siliconcompiler/tools/netgen/sc_lvs.tcl,sha256=nDvOM76PaLOhKqdF05W9edHPTbEOTFVsbh7V3UjLzY0,1430
+siliconcompiler/tools/netgen/sc_lvs.tcl,sha256=4s8QujtdKQWZw-B-k9Y9S33PT3JQ2FCwCBfyod4r3OU,1433
 siliconcompiler/tools/nextpnr/apr.py,sha256=S51ubWAT7toR9TwIj9Eny-Z77tWe-qAVyh_GW-PSBzI,826
 siliconcompiler/tools/nextpnr/nextpnr.py,sha256=DgfIEUQ6KJtnSuFx-6rHYg9GXFHmixuNl3nlEzVK3yQ,1771
 siliconcompiler/tools/openfpgaloader/openfpgaloader.py,sha256=9t7N03lF8QEQ1UiWTQRWgTK8IfTwJOkvDh4ILTSK4s8,1248
 siliconcompiler/tools/openroad/__init__.py,sha256=47DEQpj8HBSa-_TImW-5JCeuQeRkm5NMpJWZG3hSuFU,0
 siliconcompiler/tools/openroad/cts.py,sha256=Xyw2Hc_FGllndTiCSuiNiaxWKGXM8tmjYxR7oNzU4vE,1125
 siliconcompiler/tools/openroad/dfm.py,sha256=9To-Rva-iFilMgpaki3yGOUd9KgZqJ7_PlLFc4WiP8E,2310
-siliconcompiler/tools/openroad/export.py,sha256=naKYFilx3F_oERZvtQdKmQ5RU3QWPECV2ktaJ--wmF0,5437
+siliconcompiler/tools/openroad/export.py,sha256=0SlecZCUhBsAu5I4YoHS94c_rRNnwSx2y0yCLxzX4wY,5404
 siliconcompiler/tools/openroad/floorplan.py,sha256=r2-Qlob-51dgKHUP1Ya71HDz3PPRtF0bQSmlwqhdDxI,2635
-siliconcompiler/tools/openroad/openroad.py,sha256=cQkHLN8YTQ2TAOTW4biPsE0fErwTnaN4LnEn01UO9ZE,44372
+siliconcompiler/tools/openroad/openroad.py,sha256=jPA2vxJyTsQUFEKVlGL24sL8sdXRQ5JCyZEHFTbcbB0,44291
 siliconcompiler/tools/openroad/physyn.py,sha256=GKSPV8Q8-dHC7_PsDIdGV-PXVvE8uiidY_q1uX8u718,709
 siliconcompiler/tools/openroad/place.py,sha256=amXbYqJ2EWxTVzSEBh2WJp9ULX80rW1SYGJZtMOpNDo,1059
 siliconcompiler/tools/openroad/rcx_bench.py,sha256=81Y1Nca4zr6mThMrr2rGLZcxSkoOq7ts4wK1OCXx9Bg,3753
@@ -173,7 +173,7 @@ siliconcompiler/tools/openroad/rcx_extract.py,sha256=ib-1B36fVJ7SqgHcoTeSOmlKbg9
 siliconcompiler/tools/openroad/route.py,sha256=BSTMJ3RuMNwoGtEag6JM1qhOXuJ_sufOqwu-RF2_gkk,1158
 siliconcompiler/tools/openroad/screenshot.py,sha256=2rq4geF4XHwNjqttw5_J6qnay0TvS6QtC5PQh2O4PMI,2030
 siliconcompiler/tools/openroad/show.py,sha256=8eeNT32oJl8uOo7NS8DaMH376inoPWkfIyRr1PE1ODk,3825
-siliconcompiler/tools/openroad/scripts/sc_apr.tcl,sha256=5EkGsBOId_oJxGh0lWmKwLo5zZPDaHpD32asf6OYsSI,19835
+siliconcompiler/tools/openroad/scripts/sc_apr.tcl,sha256=6cfgQtGe2rbqw7BcOwFod0CBzobWi3cV4gIVT5_PicM,19841
 siliconcompiler/tools/openroad/scripts/sc_cts.tcl,sha256=e6zEyNQYmecrtmdcsfY4oVKcb_3faez5tWG-B7E_ZNk,1858
 siliconcompiler/tools/openroad/scripts/sc_dfm.tcl,sha256=kGYuqJ1XN1YVmrOcuZaBuRVbSradTzEEVG-uzaGomG4,610
 siliconcompiler/tools/openroad/scripts/sc_export.tcl,sha256=I76JByDu2O21SVDwyYEkF0T6beJ7927M6wAhHfGJZKg,2932
@@ -190,17 +190,17 @@ siliconcompiler/tools/openroad/scripts/sc_screenshot.tcl,sha256=Hti1kTDsPOSWvNbI
 siliconcompiler/tools/openroad/scripts/sc_write.tcl,sha256=1Ow-JEY1W4skHjYvH18fMHUZSyhHSa2N3lmbh0PKzGI,173
 siliconcompiler/tools/openroad/scripts/sc_write_images.tcl,sha256=qZOX1WFWNvTC5ruFIuditq-d8o-O51bXM78KCvsv2rM,9705
 siliconcompiler/tools/openroad/templates/pex.tcl,sha256=xPwuYLykhN55EQL2eem1QA3Hb4XteHOB5E4NEK137b8,307
-siliconcompiler/tools/opensta/__init__.py,sha256=OHTg1n_4l6LENkiWs7uB9xWZuw9J9LHEUUR1fa0M6XY,3729
+siliconcompiler/tools/opensta/__init__.py,sha256=FbHa5ts2oIHymtEFOdO4IFEEvxLxqfoqS8KmeL3b8rw,3743
 siliconcompiler/tools/opensta/report_libraries.py,sha256=ukr50cwxg2MXUIbMUCzQ4TKmfPsIxaMcL5faLwb6DYo,856
 siliconcompiler/tools/opensta/timing.py,sha256=3fZ45sLe3tpmcLlSBePCPxBGyq6qO3SYCWSPfbQRv90,8956
 siliconcompiler/tools/opensta/scripts/sc_procs.tcl,sha256=8Jb5QLdhCtuIwXIFIdslgxnk28ML0Wd6DWMimR1c5jU,1166
-siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl,sha256=dI2VarFIKZdqXK8lhWqTAZpKhNvx8UUI9KNE7k_H7d4,2351
-siliconcompiler/tools/opensta/scripts/sc_timing.tcl,sha256=SxbXsMPySHRhIZ-DPYHPgav3jJ244Df-qmFr0HIJp-Q,8229
+siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl,sha256=EFPxc0YByBYCuCoT68tpXEzMWTX4fIu8aAaQxufqc_o,2357
+siliconcompiler/tools/opensta/scripts/sc_timing.tcl,sha256=X1Q9zS_KeSkdNDseTS6Fapf4ctFftNZm5aLi4PMLk0M,8235
 siliconcompiler/tools/slang/__init__.py,sha256=BMJjbTWCumTBbshaTc5Wgjcl3kxPiPjwc_vnvdFrRms,1656
 siliconcompiler/tools/slang/lint.py,sha256=eNe82gmZgCMvLEKQJHagyP1yNWRQ23agBE3n709-Lz4,3080
 siliconcompiler/tools/surelog/parse.py,sha256=i7mU6xIWrSfuTb9ov1ZSJKipyyhvlGFFmKf8y--Qrns,6208
 siliconcompiler/tools/surelog/surelog.py,sha256=PlkIjrFGq1t8U2gxFSKPouDmcnS6LE1oTZDrXtVJh7M,5034
-siliconcompiler/tools/surelog/bin/surelog.exe,sha256=E9dQKPPpKWlfUo1Z41k1DXf7rjQHo6NrVe6tPc1GtJQ,6422528
+siliconcompiler/tools/surelog/bin/surelog.exe,sha256=ipLxuZRUeeUCfqcjOidbBfVN3mNJhuwmoXBqrmq9aqk,6422528
 siliconcompiler/tools/surelog/templates/output.v,sha256=NE9iQW-IEx0wanJSpbZQjRt-Qq2oIx78JOzlsBcd0Is,213
 siliconcompiler/tools/sv2v/convert.py,sha256=PG1cYSUil2sZDGh8Eb0dCvsTMnW7o2nUewv2LA23DCw,1837
 siliconcompiler/tools/sv2v/sv2v.py,sha256=AuMHqm109GJhz6oqvDyyrO9ICGI8FiDXKzBsdMFvDa0,1078
@@ -230,10 +230,10 @@ siliconcompiler/tools/vpr/vpr.py,sha256=6ZTmNo31CPkT_R_J1gy-qcBGi29ocibSDmNIH4uG
 siliconcompiler/tools/xyce/xyce.py,sha256=ggkAJe2Rs8q47yoOaQ2hGcmNa_GNglFFgm-A8lovRu8,1118
 siliconcompiler/tools/yosys/lec.py,sha256=7kUpdcNnl1_YVJzD6ZQY2RFHCaucxJHboPRkK1Pp5xs,1962
 siliconcompiler/tools/yosys/prepareLib.py,sha256=HdgZVK-zSuKdMIsGmpgmFjKpIE0PA6IVAF1YsGOAG7c,2326
-siliconcompiler/tools/yosys/sc_lec.tcl,sha256=CtS3CzrW8VKU4nx7v9lHn2kr9r8hWgBfFqwI4WD_ywY,2370
+siliconcompiler/tools/yosys/sc_lec.tcl,sha256=ZmgCEA_cuwBk1E9d2PEOsdO1595VCEFy1d6J5_61Pfo,2373
 siliconcompiler/tools/yosys/sc_syn.tcl,sha256=dXghNwdrzh_ry_hfmgBMlnJATEPCvN2YfdtInJShEOk,2519
-siliconcompiler/tools/yosys/syn_asic.py,sha256=uY2BMRI1794mMXV0O7DIbxA0p7Q2sMUVRjg9zp6dsXs,24512
-siliconcompiler/tools/yosys/syn_asic.tcl,sha256=XLZilDnJUeJQl7i85aJxITg4C_F7DXrSR0uIBE_Onf0,12269
+siliconcompiler/tools/yosys/syn_asic.py,sha256=OheWDbk6_ZJypSr-XecQWUdzd-jTWD0Mwb4xhIrw7F4,24198
+siliconcompiler/tools/yosys/syn_asic.tcl,sha256=emAM1PS04Vw3dNK6M6D-pd7daOVKajxKHeey40AqYiQ,12262
 siliconcompiler/tools/yosys/syn_asic_fpga_shared.tcl,sha256=c9QcuhnYCkPWk-tO71TO3vrU1pDIx9jqomswpHAMKLY,746
 siliconcompiler/tools/yosys/syn_fpga.py,sha256=GZw4lI1veYn-LV8ELr9sPYpmENqPeMBRysqRD1o1poU,5533
 siliconcompiler/tools/yosys/syn_fpga.tcl,sha256=AcypYnOzLvGHdA1cR7cgRxc2aUgi9FPXfs59TNLQ-BY,8244
@@ -244,9 +244,9 @@ siliconcompiler/tools/yosys/templates/abc.const,sha256=2Ea7eZz2eHzar3RLf_l2Nb9dn
 siliconcompiler/utils/__init__.py,sha256=b3mhPeBb8HIqU-8w23h2IMLSxuDrXm53e5iSeqZrkDI,13168
 siliconcompiler/utils/asic.py,sha256=knq-raDWs1FKtfqkUbLOecdSwXezlmqb8gk9QPZWdqY,5144
 siliconcompiler/utils/showtools.py,sha256=kNaw97U6tV_MwLvWb1dme_k9E6dQVqnTT6y2zzMcXJk,1158
-siliconcompiler-0.26.2.dist-info/LICENSE,sha256=UJh7mqgsPZN3gg37jhwYnrtCUs1m19vkIA6Px7jAOPY,10956
-siliconcompiler-0.26.2.dist-info/METADATA,sha256=zoV0fR6QfnbD-XCUjw5X6Zh4NcDFihCz8wJtARm2Fpk,9612
-siliconcompiler-0.26.2.dist-info/WHEEL,sha256=6DUGimnTtl3rU6RGwkmZI1NHXBFbwPul6M-9UShD9rs,99
-siliconcompiler-0.26.2.dist-info/entry_points.txt,sha256=M3cpZxvqanXhVU9CuLTRDzBdDKmKz-t0p4DT57TyysU,451
-siliconcompiler-0.26.2.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
-siliconcompiler-0.26.2.dist-info/RECORD,,
+siliconcompiler-0.26.3.dist-info/LICENSE,sha256=UJh7mqgsPZN3gg37jhwYnrtCUs1m19vkIA6Px7jAOPY,10956
+siliconcompiler-0.26.3.dist-info/METADATA,sha256=dfjuEAkNiUygxzFUch_VhbXAsBmumNqMEQzxZB_TdRQ,9612
+siliconcompiler-0.26.3.dist-info/WHEEL,sha256=7gvl0dCbVTebghm43aP3y0WeizA_ShLQd9uyJMZ-IUI,99
+siliconcompiler-0.26.3.dist-info/entry_points.txt,sha256=M3cpZxvqanXhVU9CuLTRDzBdDKmKz-t0p4DT57TyysU,451
+siliconcompiler-0.26.3.dist-info/top_level.txt,sha256=H8TOYhnEUZAV1RJTa8JRtjLIebwHzkQUhA2wkNU2O6M,16
+siliconcompiler-0.26.3.dist-info/RECORD,,

{siliconcompiler-0.26.2.dist-info → siliconcompiler-0.26.3.dist-info}/WHEEL

@@ -1,5 +1,5 @@
 Wheel-Version: 1.0
-Generator: setuptools (72.2.0)
+Generator: setuptools (73.0.1)
 Root-Is-Purelib: false
 Tag: cp38-cp38-win_amd64