siliconcompiler 0.26.1__cp39-cp39-win_amd64.whl → 0.26.3__cp39-cp39-win_amd64.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.26.1'
+version = '0.26.3'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/apps/sc_issue.py

@@ -25,13 +25,13 @@ Restricted SC app that generates a sharable testcase from a
 failed flow or runs an issue generated with this program.
 
 To generate a testcase, use:
-    sc-issue -generate -cfg <stepdir>/outputs/<design>.pkg.json
+    sc-issue -cfg <stepdir>/outputs/<design>.pkg.json
 
     or include a different step/index than what the cfg_file is pointing to:
-    sc-issue -generate -cfg <otherdir>/outputs/<design>.pkg.json -arg_step <step> -arg_index <index>
+    sc-issue -cfg <otherdir>/outputs/<design>.pkg.json -arg_step <step> -arg_index <index>
 
     or include specific libraries while excluding others:
-    sc-issue -generate -cfg <stepdir>/outputs/<design>.pkg.json -exclude_libraries -add_library sram -add_library gpio
+    sc-issue -cfg <stepdir>/outputs/<design>.pkg.json -exclude_libraries -add_library sram -add_library gpio
 
 To run a testcase, use:
     sc-issue -run -file sc_issue_<...>.tar.gz
@@ -39,10 +39,6 @@ To run a testcase, use:
 """  # noqa E501
 
     issue_arguments = {
-        '-generate': {'action': 'store_true',
-                      'help': 'generate a testcase',
-                      'sc_print': False},
-
         '-exclude_libraries': {'action': 'store_true',
                                'help': 'flag to ensure libraries are excluded in the testcase',
                                'sc_print': False},
@@ -88,10 +84,7 @@ To run a testcase, use:
         chip.logger.error(e)
         return 1
 
-    if switches['generate'] and switches['run']:
-        raise ValueError('Only one of -generate or -run can be used')
-
-    if switches['generate']:
+    if not switches['run']:
         step = chip.get('arg', 'step')
         index = chip.get('arg', 'index')
 

siliconcompiler/apps/smake.py

@@ -41,7 +41,20 @@ def __process_file(path):
             arg_type = str
             if arg in func_spec.annotations:
                 arg_type = func_spec.annotations[arg]
-            func_args[arg] = arg_type
+            func_args[arg] = {
+                "type": arg_type
+            }
+
+        if func_spec.defaults:
+            for arg, defval in zip(reversed(func_spec.args), reversed(func_spec.defaults)):
+                func_args[arg]["default"] = defval
+
+                if defval is None:
+                    continue
+
+                if type(defval) is not func_args[arg]["type"]:
+                    if isinstance(defval, (bool, str, float, int)):
+                        func_args[arg]["type"] = type(defval)
 
         args[name] = {
             "function": func,
@@ -62,7 +75,7 @@ def __process_file(path):
     return args, default_arg, module_help
 
 
-def main():
+def main(source_file=None):
     progname = "smake"
     description = f"""-----------------------------------------------------------
 SC app that provides an Makefile like interface to python
@@ -90,16 +103,18 @@ To run a target with supported arguments, use:
 -----------------------------------------------------------"""
 
     # handle source file identification before arg parse
-    source_file = __default_source_file
-    file_args = ('--file', '-f')
-    for file_arg in file_args:
-        if file_arg in sys.argv:
-            source_file_idx = sys.argv.index(file_arg) + 1
-            if source_file_idx < len(sys.argv):
-                source_file = sys.argv[source_file_idx]
-            else:
-                source_file = None
-            break
+    file_args = None
+    if not source_file:
+        source_file = __default_source_file
+        file_args = ('--file', '-f')
+        for file_arg in file_args:
+            if file_arg in sys.argv:
+                source_file_idx = sys.argv.index(file_arg) + 1
+                if source_file_idx < len(sys.argv):
+                    source_file = sys.argv[source_file_idx]
+                else:
+                    source_file = None
+                break
 
     # handle directory identification before arg parse
     source_dir = os.getcwd()
@@ -135,10 +150,11 @@ To run a target with supported arguments, use:
         description=description,
         formatter_class=argparse.RawDescriptionHelpFormatter)
 
-    parser.add_argument(
-        *file_args,
-        metavar='<file>',
-        help=f'Use file as makefile, default is {__default_source_file}')
+    if file_args:
+        parser.add_argument(
+            *file_args,
+            metavar='<file>',
+            help=f'Use file as makefile, default is {__default_source_file}')
 
     parser.add_argument(
         *dir_args,
@@ -159,14 +175,38 @@ To run a target with supported arguments, use:
         subparse = targetparsers.add_parser(
             arg,
             description=info['full_help'],
-            help=info['help'])
+            help=info['help'],
+            formatter_class=argparse.RawDescriptionHelpFormatter)
+
+        for subarg, subarg_info in info['args'].items():
+            # print(subarg, subarg_info)
+            add_args = {}
+
+            if "default" not in subarg_info:
+                add_args["required"] = True
+            else:
+                if type(subarg_info["default"]) is subarg_info["type"]:
+                    add_args["default"] = subarg_info["default"]
+
+            if subarg_info["type"] is bool:
+                def str2bool(v):
+                    # modified from:
+                    # https://github.com/pypa/distutils/blob/8993718731b951ee36d08cb784f02aa13542ce15/distutils/util.py
+                    val = v.lower()
+                    if val in ('y', 'yes', 't', 'true', 'on', '1'):
+                        return True
+                    elif val in ('n', 'no', 'f', 'false', 'off', '0'):
+                        return False
+                    else:
+                        raise ValueError(f"invalid truth value {val!r}")
+                subarg_info["type"] = str2bool
 
-        for subarg, subarg_type in info['args'].items():
             subparse.add_argument(
                 f'--{subarg}',
                 dest=f'sub_{subarg}',
                 metavar=f'<{subarg}>',
-                type=subarg_type)
+                type=subarg_info["type"],
+                **add_args)
 
     args = parser.parse_args()
     target = args.target

siliconcompiler/core.py

@@ -1001,8 +1001,8 @@ class Chip:
             package (str): Name of package where this file can be found
         '''
 
-        self.__add_input_output('input', filename, fileset, filetype, iomap,
-                                step=step, index=index, package=package)
+        self._add_input_output('input', filename, fileset, filetype, iomap,
+                               step=step, index=index, package=package)
     # Replace {iotable} in __doc__ with actual table for fileset/filetype and extension mapping
     input.__doc__ = input.__doc__.replace("{iotable}",
                                           utils.format_fileset_type_table())
@@ -1012,14 +1012,14 @@ class Chip:
                step=None, index=None, package=None):
         '''Same as input'''
 
-        self.__add_input_output('output', filename, fileset, filetype, iomap,
-                                step=step, index=index, package=package)
+        self._add_input_output('output', filename, fileset, filetype, iomap,
+                               step=step, index=index, package=package)
     # Copy input functions __doc__ and replace 'input' with 'output' to make constant
     output.__doc__ = input.__doc__.replace("input", "output")
 
     ###########################################################################
-    def __add_input_output(self, category, filename, fileset, filetype, iomap,
-                           step=None, index=None, package=None):
+    def _add_input_output(self, category, filename, fileset, filetype, iomap,
+                          step=None, index=None, package=None, quiet=False):
         '''
         Adds file to input or output groups.
         Performs a lookup in the io map for the fileset and filetype
@@ -1051,12 +1051,13 @@ class Chip:
         if not use_fileset or not use_filetype:
             self.logger.error(f'Unable to infer {category} fileset and/or filetype for '
                               f'{filename} based on file extension.')
-        elif not fileset and not filetype:
-            self.logger.info(f'{filename} inferred as {use_fileset}/{use_filetype}')
-        elif not filetype:
-            self.logger.info(f'{filename} inferred as filetype {use_filetype}')
-        elif not fileset:
-            self.logger.info(f'{filename} inferred as fileset {use_fileset}')
+        elif not quiet:
+            if not fileset and not filetype:
+                self.logger.info(f'{filename} inferred as {use_fileset}/{use_filetype}')
+            elif not filetype:
+                self.logger.info(f'{filename} inferred as filetype {use_filetype}')
+            elif not fileset:
+                self.logger.info(f'{filename} inferred as fileset {use_fileset}')
 
         self.add(category, use_fileset, use_filetype, filename,
                  step=step, index=index, package=package)
@@ -1946,7 +1947,7 @@ class Chip:
 
     ###########################################################################
     def write_dependencygraph(self, filename, flow=None,
-                              fillcolor='#ffffff', fontcolor='#000000',
+                              fontcolor='#000000', color_scheme=None,
                               background='transparent', fontsize='14',
                               border=True, landscape=False):
         r'''
@@ -1964,8 +1965,9 @@ class Chip:
         Args:
             filename (filepath): Output filepath
             flow (str): Name of flowgraph to render
-            fillcolor(str): Node fill RGB color hex value
             fontcolor (str): Node font RGB color hex value
+            color_scheme (str): Name of the color scheme to apply to the nodes.
+                Valid choices are: "none", "simple", "detailed"
             background (str): Background color
             fontsize (str): Node text font size
             border (bool): Enables node border if True
@@ -1981,6 +1983,33 @@ class Chip:
         fileroot, ext = os.path.splitext(filepath)
         fileformat = ext.replace(".", "")
 
+        color_schemes = {
+            "none": {
+                "design": "white",
+                "library": "white",
+                "logiclib": "white",
+                "macrolib": "white"
+            },
+            "simple": {
+                "design": "lightgreen",
+                "library": "white",
+                "logiclib": "lightgreen",
+                "macrolib": "lightgreen"
+            },
+            "detailed": {
+                "design": "lightgreen",
+                "library": "white",
+                "logiclib": "lightskyblue",
+                "macrolib": "lightgoldenrod2"
+            },
+        }
+
+        if not color_scheme:
+            color_scheme = "none"
+
+        if color_scheme not in color_schemes:
+            raise ValueError(f'{color_scheme} is not a valid color scheme')
+
         # controlling border width
         if border:
             penwidth = '1'
@@ -2006,7 +2035,7 @@ class Chip:
             nodes.add(node)
             dot.node(node, label=node, bordercolor=fontcolor, style='filled',
                      fontcolor=fontcolor, fontsize=fontsize, ordering="in",
-                     penwidth=penwidth, fillcolor=fillcolor)
+                     penwidth=penwidth, fillcolor="white")
             return node
 
         nodes = {}
@@ -2019,32 +2048,53 @@ class Chip:
             if root_label in nodes:
                 return
 
-            in_libs = lib.get('option', 'library',
-                              step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY) + \
-                lib.get('asic', 'logiclib',
-                        step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY) + \
-                lib.get('asic', 'macrolib',
-                        step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY)
-
             in_labels = []
-            for in_lib in in_libs:
+            for in_lib in lib.get('option', 'library',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
                 in_labels.append(f'library-{in_lib}')
+            for in_lib in lib.get('asic', 'logiclib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                in_labels.append(f'logiclib-{in_lib}')
+            for in_lib in lib.get('asic', 'macrolib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                in_labels.append(f'macrolib-{in_lib}')
+
+            shape = "oval"
+            if root_type == "logiclib":
+                shape = "box"
+            elif root_type == "macrolib":
+                shape = "box"
+            elif root_type == "design":
+                shape = "box"
+
+            color = color_schemes[color_scheme][root_type]
 
             nodes[root_label] = {
                 "text": name,
-                "shape": "oval" if root_type == "library" else "box",
+                "shape": shape,
+                "color": color,
                 "connects_to": set(in_labels)
             }
 
-            for in_lib in in_libs:
-                collect_library("library", Schema(cfg=self.getdict('library', in_lib)), name=in_lib)
+            for in_lib in lib.get('option', 'library',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                collect_library("library", Schema(cfg=self.getdict('library', in_lib)),
+                                name=in_lib)
+            for in_lib in lib.get('asic', 'logiclib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                collect_library("logiclib", Schema(cfg=self.getdict('library', in_lib)),
+                                name=in_lib)
+            for in_lib in lib.get('asic', 'macrolib',
+                                  step=Schema.GLOBAL_KEY, index=Schema.GLOBAL_KEY):
+                collect_library("macrolib", Schema(cfg=self.getdict('library', in_lib)),
+                                name=in_lib)
 
         collect_library("design", self)
 
         for label, info in nodes.items():
             dot.node(label, label=info['text'], bordercolor=fontcolor, style='filled',
                      fontcolor=fontcolor, fontsize=fontsize, ordering="in",
-                     penwidth=penwidth, fillcolor=fillcolor, shape=info['shape'])
+                     penwidth=penwidth, fillcolor=info["color"], shape=info['shape'])
 
             for conn in info['connects_to']:
                 dot.edge(label, conn, dir='back')
@@ -2059,7 +2109,7 @@ class Chip:
         '''
         Recursively changes a library in ['option', 'library'] from a previous
         value to a new value. If the library is not present then nothing is
-        changed.
+        changed. If the new library is None, the original library will be removed.
 
         Args:
             org_library (str): Name of old library
@@ -2081,8 +2131,13 @@ class Chip:
                     r_index = Schema.GLOBAL_KEY
 
                 val = self.get(*key, step=r_step, index=r_index)
-                self.set(*key, list(map(lambda x: x.replace(org_library, new_library), val)),
-                         step=r_step, index=r_index)
+                if new_library is None:
+                    self.set(*key, [v for v in val if v != org_library],
+                             step=r_step, index=r_index)
+                else:
+                    self.set(*key,
+                             list(map(lambda x: new_library if x == org_library else x, val)),
+                             step=r_step, index=r_index)
             else:
                 for val, r_step, r_index in self.schema._getvals(*key):
                     if r_step is None:
@@ -2090,8 +2145,13 @@ class Chip:
                     if r_index is None:
                         r_index = Schema.GLOBAL_KEY
 
-                    self.set(*key, list(map(lambda x: x.replace(org_library, new_library), val)),
-                             step=r_step, index=r_index)
+                    if new_library is None:
+                        self.set(*key, [v for v in val if v != org_library],
+                                 step=r_step, index=r_index)
+                    else:
+                        self.set(*key,
+                                 list(map(lambda x: new_library if x == org_library else x, val)),
+                                 step=r_step, index=r_index)
 
         swap('option', 'library')
         for lib in all_libraries:

siliconcompiler/issue.py

@@ -153,6 +153,8 @@ def generate_testcase(chip,
     os.chdir(new_work_dir)
 
     # Rewrite replay.sh
+    prev_quiet = chip.get('option', 'quiet', step=step, index=index)
+    chip.set('option', 'quiet', True, step=step, index=index)
     from siliconcompiler import SiliconCompilerError
     try:
         # Rerun setup
@@ -167,6 +169,7 @@ def generate_testcase(chip,
                 pass
     except SiliconCompilerError:
         pass
+    chip.set('option', 'quiet', prev_quiet, step=step, index=index)
 
     flow = chip.get('option', 'flow')
     is_python_tool = hasattr(chip._get_task_module(step, index, flow=flow), 'run')

siliconcompiler/report/report.py

@@ -59,7 +59,7 @@ def get_flowgraph_nodes(chip, step, index):
         if value is not None:
             if key == 'inputnode':
                 value = ", ".join([f'{step}{index}' for step, index in value])
-            nodes[key] = value
+            nodes[key] = str(value)
     return nodes
 
 

siliconcompiler/scheduler/__init__.py

@@ -201,7 +201,10 @@ def _local_process(chip, flow):
                                     f'{chip.design}.pkg.json')
             if os.path.exists(manifest):
                 # ensure we setup these nodes again
-                extra_setup_nodes[(step, index)] = Schema(manifest=manifest, logger=chip.logger)
+                try:
+                    extra_setup_nodes[(step, index)] = Schema(manifest=manifest, logger=chip.logger)
+                except Exception:
+                    pass
 
     # Setup tools for all nodes to run.
     nodes = nodes_to_execute(chip, flow)

siliconcompiler/schema/schema_cfg.py

@@ -11,7 +11,7 @@ try:
 except ImportError:
     from siliconcompiler.schema.utils import trim
 
-SCHEMA_VERSION = '0.44.2'
+SCHEMA_VERSION = '0.44.3'
 
 #############################################################################
 # PARAM DEFINITION
@@ -1273,12 +1273,21 @@ def schema_datasheet(cfg, name='default', mode='default'):
 
     scparam(cfg, ['datasheet', 'package', name, 'netname', name],
             sctype='str',
-            shorthelp="Datasheet: package pin netname",
+            shorthelp="Datasheet: package pin net name",
             switch="-datasheet_package_netname 'name name <str>'",
             example=[
                 "cli: -datasheet_package_netname 'abcd B1 VDD'",
                 "api: chip.set('datasheet', 'package', 'abcd', 'netname', 'B1', 'VDD')"],
-            schelp="""Datsheet: Net name connected to package pin.""")
+            schelp="""Datsheet: Device net connected to the pin.""")
+
+    scparam(cfg, ['datasheet', 'package', name, 'portname', name],
+            sctype='str',
+            shorthelp="Datasheet: package pin port name",
+            switch="-datasheet_package_portname 'name name <str>'",
+            example=[
+                "cli: -datasheet_package_portname 'abcd B1 VDD'",
+                "api: chip.set('datasheet', 'package', 'abcd', 'portname', 'B1', 'VDD')"],
+            schelp="""Datsheet: Device port connected to the pin.""")
 
     ######################
     # Pin Specifications

siliconcompiler/templates/tcl/manifest.tcl.j2

@@ -83,3 +83,55 @@ proc sc_section_banner { text { method puts } } {
     $method "| $text"
     $method "============================================================"
 }
+
+# Get list of soft libraries
+proc sc_get_libraries { {library {}} {libraries {}} } {
+    set key []
+    if { [llength $library] != 0 } {
+        lappend key library $library
+    }
+    lappend key option library
+
+    set libs []
+    foreach lib [sc_cfg_get {*}$key] {
+        if { [lsearch -exact $libs $lib] != -1 || [lsearch -exact $libraries $lib] != -1 } {
+            continue
+        }
+
+        lappend libs $lib
+
+        foreach sublib [sc_get_libraries $lib $libs] {
+            lappend libs $sublib
+        }
+    }
+
+    return [lsort -unique $libs]
+}
+
+# Get list of asic libraries
+proc sc_get_asic_libraries { type } {
+    set libs []
+
+    foreach lib [sc_cfg_get asic ${type}lib] {
+        if { [lsearch -exact $libs $lib] != -1 } {
+            continue
+        }
+        lappend libs $lib
+    }
+
+    foreach lib [sc_get_libraries] {
+        if { ![sc_cfg_exists library $lib asic ${type}lib] } {
+            continue
+        }
+
+        foreach sublib [sc_cfg_get library $lib asic ${type}lib] {
+            if { [lsearch -exact $libs $sublib] != -1 } {
+                continue
+            }
+
+            lappend libs $sublib
+        }
+    }
+
+    return $libs
+}

siliconcompiler/tools/_common/__init__.py

@@ -1,7 +1,5 @@
 import os
 import pkgutil
-from siliconcompiler.utils import get_file_ext
-from siliconcompiler import units, SiliconCompilerError, NodeStatus
 
 
 def get_libraries(chip, include_asic=True, library=None, libraries=None):
@@ -159,6 +157,8 @@ def __get_keys(chip, *key, include_library_files=True):
 
 
 def __assert_support(chip, opt_keys, supports):
+    from siliconcompiler import SiliconCompilerError
+
     if not supports:
         supports = []
 
@@ -255,6 +255,8 @@ def get_frontend_options(chip, supports=None):
 
 
 def find_incoming_ext(chip, support_exts, default_ext):
+    from siliconcompiler.utils import get_file_ext
+
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
     flow = chip.get('option', 'flow')
@@ -302,6 +304,8 @@ def pick_key(chip, check_keys, step=None, index=None):
 
 
 def input_provides(chip, step, index, flow=None):
+    from siliconcompiler import NodeStatus
+
     if not flow:
         flow = chip.get('option', 'flow')
 
@@ -323,6 +327,8 @@ def input_provides(chip, step, index, flow=None):
 
 
 def input_file_node_name(filename, step, index):
+    from siliconcompiler.utils import get_file_ext
+
     file_type = get_file_ext(filename)
 
     base = filename
@@ -408,6 +414,8 @@ def record_metric(chip, step, index, metric, value, source, source_unit=None):
         Records the metric cell area under 'floorplan0' and notes the source as
         'reports/metrics.json'
     '''
+    from siliconcompiler import units
+
     metric_unit = None
     if chip.schema.has_field('metric', metric, 'unit'):
         metric_unit = chip.get('metric', metric, field='unit')

siliconcompiler/tools/_common/asic.py

@@ -1,12 +1,32 @@
-from siliconcompiler.tools._common import pick_key
-from siliconcompiler.tools._common import get_tool_task
+from .. import _common
 
 
 def get_mainlib(chip):
+    return get_libraries(chip, 'logic')[0]
+
+
+def get_libraries(chip, type):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    logiclibs = chip.get('asic', 'logiclib', step=step, index=index)
-    return logiclibs[0]
+
+    if type not in ('logic', 'macro'):
+        raise ValueError(f'Cannot collect {type} libraries')
+
+    libs = []
+    for lib in chip.get('asic', f'{type}lib', step=step, index=index):
+        if lib in libs:
+            continue
+        libs.append(lib)
+
+    for lib in _common.get_libraries(chip, include_asic=False):
+        if not chip.valid('library', lib, 'asic', f'{type}lib'):
+            continue
+        for sublib in chip.get('library', lib, 'asic', f'{type}lib', step=step, index=index):
+            if sublib in libs:
+                continue
+            libs.append(sublib)
+
+    return libs
 
 
 def get_timing_modes(chip):
@@ -33,7 +53,7 @@ def set_tool_task_var(chip,
     '''
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    tool, task = get_tool_task(chip, step, index)
+    tool, task = _common.get_tool_task(chip, step, index)
     pdkname = chip.get('option', 'pdk')
     stackup = chip.get('option', 'stackup')
     mainlib = get_mainlib(chip)
@@ -72,7 +92,7 @@ def set_tool_task_var(chip,
                  ','.join(check_keys[-1]),
                  step=step, index=index)
 
-    require_key, value = pick_key(chip, reversed(check_keys), step=step, index=index)
+    require_key, value = _common.pick_key(chip, reversed(check_keys), step=step, index=index)
     if not value:
         value = default_value
 

siliconcompiler/tools/klayout/export.py

@@ -2,6 +2,7 @@
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
 from siliconcompiler.tools.klayout.screenshot import setup_gui_screenshot
 from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools._common.asic import get_libraries
 
 
 def setup(chip):
@@ -23,7 +24,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=clobber)
 
-    targetlibs = chip.get('asic', 'logiclib', step=step, index=index)
+    targetlibs = get_libraries(chip, 'logic')
     stackup = chip.get('option', 'stackup')
     pdk = chip.get('option', 'pdk')
 
@@ -39,7 +40,7 @@ def setup(chip):
     sc_stream_order = [default_stream, *[s for s in streams if s != default_stream]]
 
     if stackup and targetlibs:
-        macrolibs = chip.get('asic', 'macrolib', step=step, index=index)
+        macrolibs = get_libraries(chip, 'macro')
 
         chip.add('tool', tool, 'task', task, 'require', ",".join(['asic', 'logiclib']),
                  step=step, index=index)

siliconcompiler/tools/klayout/klayout_export.py

@@ -124,7 +124,8 @@ def main():
         save_technology,
         get_schema
     )
-    from tools.klayout.klayout_show import show  # noqa E402
+    from tools.klayout.klayout_show import show
+    from tools._common.asic import get_libraries
 
     schema = get_schema(manifest='sc_manifest.json')
 
@@ -158,9 +159,8 @@ def main():
 
     out_file = os.path.join('outputs', f'{design}.{sc_stream}')
 
-    libs = schema.get('asic', 'logiclib', step=sc_step, index=sc_index)
-    if 'macrolib' in schema.getkeys('asic'):
-        libs += schema.get('asic', 'macrolib', step=sc_step, index=sc_index)
+    libs = get_libraries(schema, 'logic')
+    libs += get_libraries(schema, 'macro')
 
     in_files = []
     for lib in libs: