sentinel-cpu 0.1.0b2.dev52__py3-none-any.whl

sentinel_cpu/__init__.py

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+"""The Sentinel RISC-V CPU Package.
+
+There is no ``__all__``; star imports are not presently supported. Users will
+likely want to import or run one of the following modules directly:
+
+.. testcode::
+
+    from sentinel_cpu.top import Top
+
+::
+
+    python -m sentinel_cpu.gen --help
+"""

sentinel_cpu/align.py

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+"""Components to align external data going in/out of the Sentinel Core."""
+
+from amaranth import Signal, Module
+from amaranth.lib.wiring import Component, In, Out
+
+from .ucodefields import MemSel, MemExtend, MemReq, InsnFetch
+
+
+class AddressAlign(Component):
+    """Align internal address data before driving external address lines.
+
+    This :class:`~amaranth:amaranth.lib.wiring.Component` is pure combinational
+    logic that splits a 32-bit input address for a memory or I/O transfer into
+    two parts:
+
+    * A :attr:`30-bit address <wb_adr>` to/from which to write/read 32-bit
+      data. This directly drives Wishbone signal ``ADR_O``.
+    * :attr:`4 select lines <wb_sel>` which determine which bytes of the 32-bit
+      :attr:`write <WriteDataAlign.wb_dat_w>` or
+      :attr:`read data <ReadDataAlign.wb_dat_r>` are valid/meaningful for the
+      current transfer. These lines directly drive Wishbone signal ``SEL_O``.
+
+    If :attr:`insn_fetch` is asserted:
+
+    * The 30-bit address comes directly from the
+      :class:`~sentinel_cpu.datapath.ProgramCounter`.
+    * All select lines are asserted.
+
+    If :attr:`insn_fetch` is not asserted:
+
+    * The 30-bit address comes from the top 30 bits of :attr:`latched_adr`.
+    * The bottom two bits of :attr:`latched_adr` and the :attr:`mem_sel`
+      signals calculate the proper select lines to assert (all for a 32-bit
+      transfer, top two or bottom two for 16-bit transfers, and one-hot for an
+      8-bit transfer).
+
+    For space reasons, :class:`AddressAlign` does *not* qualify
+    :attr:`insn_fetch` by the *de-assertion* of
+    :data:`~sentinel_cpu.ucodefields.WriteMem`, even though an instruction
+    write transfer doesn't make really sense.
+    """
+
+    #: In(:data:`~sentinel_cpu.ucodefields.MemReq`): If set, indicates a memory
+    #: transfer over the Wishbone bus is occurring. Outputs are qualified by
+    #: this signal.
+    mem_req: In(MemReq)
+    #: In(MemSel): Select whether to do an 8-bit, 16-bit, or 32-bit read, or
+    #: ignore.
+    mem_sel: In(MemSel)
+    #: In(:data:`~sentinel_cpu.ucodefields.InsnFetch`): If set, the current
+    #: memory read is an instruction fetch.
+    insn_fetch: In(InsnFetch)
+    #: Current value of the :class:`~sentinel_cpu.datapath.ProgramCounter`,
+    #: used to generate :attr:`wb_adr` when :attr:`insn_fetch` is asserted.
+    pc: In(30)
+    #: Registered address of the memory transfer, latched on a previous
+    #: cycle. Raw address before alignment used to generate :attr:`wb_adr` when
+    #: and :attr:`wb_sel` when :attr:`insn_fetch` is *not* asserted.
+    latched_adr: In(32)
+    #: 32-bit aligned address, which directly drives Wishbone ``ADR_O``.
+    wb_adr: Out(30)
+    #: Data select lines, which qualify which bytes in the 32-bit ``DAT_I`` and
+    #: ``DAT_O`` are valid for the current memory transfer. Directly drives
+    #: Wishbone ``SEL_O``.
+    wb_sel: Out(4)
+
+    def elaborate(self, platform):  # noqa: D102
+        m = Module()
+
+        # DataPath.dat_w constantly has traffic. We only want to latch
+        # the address once per mem access, and we want it the address to be
+        # valid synchronous with ready assertion.
+        with m.If(self.mem_req):
+            with m.If(self.insn_fetch):
+                m.d.comb += [self.wb_adr.eq(self.pc),
+                             self.wb_sel.eq(0xf)]
+            with m.Else():
+                m.d.comb += self.wb_adr.eq(self.latched_adr[2:])
+
+                # TODO: Misaligned accesses
+                with m.Switch(self.mem_sel):
+                    with m.Case(MemSel.BYTE):
+                        with m.If(self.latched_adr[0:2] == 0):
+                            m.d.comb += self.wb_sel.eq(1)
+                        with m.Elif(self.latched_adr[0:2] == 1):
+                            m.d.comb += self.wb_sel.eq(2)
+                        with m.Elif(self.latched_adr[0:2] == 2):
+                            m.d.comb += self.wb_sel.eq(4)
+                        with m.Else():
+                            m.d.comb += self.wb_sel.eq(8)
+                    with m.Case(MemSel.HWORD):
+                        with m.If(self.latched_adr[1] == 0):
+                            m.d.comb += self.wb_sel.eq(3)
+                        with m.Else():
+                            m.d.comb += self.wb_sel.eq(0xc)
+                    with m.Case(MemSel.WORD):
+                        m.d.comb += self.wb_sel.eq(0xf)
+
+        return m
+
+
+class ReadDataAlign(Component):
+    """Align external read data before latching internally.
+
+    This :class:`~amaranth:amaranth.lib.wiring.Component` is pure combinational
+    logic that aligns and then extends read data to 32-bits:
+
+    * If :attr:`mem_sel` is :attr:`~sentinel_cpu.ucodefields.MemSel.BYTE`, pass
+      any of the 4 bytes of :attr:`wb_dat_r` to an data extension circuit,
+      depending on :attr:`address <latched_adr>` alignment. Then
+      either zero or sign-extend the selected byte to 32-bits, depending on
+      :attr:`mem_extend`. Finally, pass the extender output to :attr:`data`.
+
+    * If :attr:`mem_sel` is :attr:`~sentinel_cpu.ucodefields.MemSel.HWORD`,
+      pass either the low 16-bits or high 16-bits of :attr:`wb_dat_r` to a data
+      extension circuit, depending on :attr:`address <latched_adr>`
+      alignment. Then, either zero or sign-extend these 16-bits to 32-bits,
+      depending on :attr:`mem_extend`. Finally, pass the extender output
+      to :attr:`data`.
+
+    * If :attr:`mem_sel` is :attr:`~sentinel_cpu.ucodefields.MemSel.WORD`, pass
+      :attr:`wb_dat_r` to :attr:`data` unaltered. The extension circuit is
+      not used.
+
+    Because I found it to be a size win, I physically implement
+    :class:`ReadDataAlign` as part of :class:`sentinel_cpu.alu.BSrcMux`; the
+    :attr:`sentinel_cpu.alu.BSrcMux.dat_r` input feeds directly into
+    :class:`ReadDataAlign`.
+
+    :class:`AddressAlign` ensures that the appropriate ``SEL_O`` lines
+    are asserted for the read.
+    """
+
+    #: In(MemSel): Select whether to do an 8-bit, 16-bit, or 32-bit read, or
+    #: ignore.
+    mem_sel: In(MemSel)
+    #: In(MemExtend): Zero or sign-extend reads of less than 32-bits.
+    mem_extend: In(MemExtend)
+    #: Registered address from which data will be read, latched on a previous
+    #: cycle.
+    latched_adr: In(32)
+    #: Unregistered raw input data, directly from Wishbone ``DAT_I``.
+    wb_dat_r: In(32)
+    #: Aligned and extended data output.
+    data: Out(32)
+
+    def elaborate(self, platform):  # noqa: D102
+        m = Module()
+
+        selected_dat = Signal.like(self.wb_dat_r)
+
+        with m.Switch(self.mem_sel):
+            with m.Case(MemSel.BYTE):
+                with m.If(self.latched_adr[0:2] == 0):
+                    m.d.comb += selected_dat.eq(self.wb_dat_r[0:8])
+                with m.Elif(self.latched_adr[0:2] == 1):
+                    m.d.comb += selected_dat.eq(self.wb_dat_r[8:16])
+                with m.Elif(self.latched_adr[0:2] == 2):
+                    m.d.comb += selected_dat.eq(self.wb_dat_r[16:24])
+                with m.Else():
+                    m.d.comb += selected_dat.eq(self.wb_dat_r[24:])
+
+                with m.If(self.mem_extend == MemExtend.SIGN):
+                    m.d.comb += self.data.eq(selected_dat[0:8].as_signed())
+                with m.Else():
+                    m.d.comb += self.data.eq(selected_dat[0:8])
+            with m.Case(MemSel.HWORD):
+                with m.If(self.latched_adr[1] == 0):
+                    m.d.comb += selected_dat.eq(self.wb_dat_r[0:16])
+                with m.Else():
+                    m.d.comb += selected_dat.eq(self.wb_dat_r[16:])
+
+                with m.If(self.mem_extend == MemExtend.SIGN):
+                    m.d.comb += self.data.eq(selected_dat[0:16].as_signed())
+                with m.Else():
+                    m.d.comb += self.data.eq(selected_dat[0:16])
+            with m.Case(MemSel.WORD):
+                m.d.comb += self.data.eq(self.wb_dat_r)
+
+        return m
+
+
+class WriteDataAlign(Component):
+    """Align internal write data before sending to external peripherals.
+
+    This :class:`~amaranth:amaranth.lib.wiring.Component` is pure combinational
+    logic that aligns write data to an appropriate offset within 32-bits:
+
+    * If :attr:`mem_sel` is :attr:`~sentinel_cpu.ucodefields.MemSel.BYTE`, move
+      the low byte of :attr:`data` to one of the 4 constituent bytes of
+      :attr:`wb_dat_w`, depending on :attr:`address <latched_adr>`
+      alignment. The other bytes of :attr:`wb_dat_w` are invalid.
+
+    * If :attr:`mem_sel` is :attr:`~sentinel_cpu.ucodefields.MemSel.HWORD`, the
+      low 16-bits :attr:`data` move into either the low 16-bits or high
+      16-bits of :attr:`wb_dat_w`, depending on :attr:`address <latched_adr>`
+      alignment. The other 16-bits of :attr:`wb_dat_w` is invalid.
+
+    * If :attr:`mem_sel` is :attr:`~sentinel_cpu.ucodefields.MemSel.WORD`, pass
+      :attr:`data` to :attr:`wb_dat_w` unaltered. All bits are valid.
+
+    Since not all 32-bits of ``DAT_O`` will necessarily be valid for a given
+    write, :class:`AddressAlign` ensures that the appropriate ``SEL_O`` lines
+    are asserted for the write.
+    """
+
+    #: In(MemSel): Select whether to do an 8-bit, 16-bit, or 32-bit write, or
+    #: ignore.
+    mem_sel: In(MemSel)
+    #: Registered address to which data will be written, latched on a previous
+    #: cycle.
+    latched_adr: In(32)
+    #: Data to be written externally, before alignment.
+    data: In(32)
+    #: Aligned data to be :data:`latched <sentinel_cpu.ucodefields.LatchData>`,
+    #: which then drives Wishbone ``DAT_O``.
+    wb_dat_w: Out(32)
+
+    def elaborate(self, platform):  # noqa: D102
+        m = Module()
+
+        # TODO: Misaligned accesses
+        with m.Switch(self.mem_sel):
+            with m.Case(MemSel.BYTE):
+                with m.If(self.latched_adr[0:2] == 0):
+                    m.d.comb += self.wb_dat_w[0:8].eq(self.data[0:8])
+                with m.Elif(self.latched_adr[0:2] == 1):
+                    m.d.comb += self.wb_dat_w[8:16].eq(self.data[0:8])
+                with m.Elif(self.latched_adr[0:2] == 2):
+                    m.d.comb += self.wb_dat_w[16:24].eq(self.data[0:8])
+                with m.Else():
+                    m.d.comb += self.wb_dat_w[24:].eq(self.data[0:8])
+            with m.Case(MemSel.HWORD):
+                with m.If(self.latched_adr[1] == 0):
+                    m.d.comb += self.wb_dat_w[0:16].eq(self.data[0:16])
+                with m.Else():
+                    m.d.comb += self.wb_dat_w[16:].eq(self.data[0:16])
+            with m.Case(MemSel.WORD):
+                m.d.comb += self.wb_dat_w.eq(self.data)
+
+        return m

sentinel_cpu/alu.py

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+"""Arithmetic Logic Unit (ALU) Components."""
+
+from .align import ReadDataAlign
+from .csr import MCause
+from .ucodefields import OpType, ALUIMod, ALUOMod, ASrc, BSrc, MemSel, \
+    MemExtend, LatchA, LatchB
+
+from amaranth import Elaboratable, Signal, Module, C, Cat
+from amaranth.lib.wiring import Component, Signature, In, Out
+
+
+class ASrcMux(Component):
+    """Latch one of many :attr:`ALU A input <sentinel_cpu.alu.ALU.a>` sources.
+
+    The ALU does not have registered inputs; the
+    :attr:`~sentinel_cpu.alu.ASrcMux.data` output is registered and feeds
+    immediately into the ALU A input.
+    """
+
+    #: When asserted, latch the :attr:`selected <sentinel_cpu.alu.ASrcMux.sel>`
+    #: input into :attr:`~sentinel_cpu.alu.ASrcMux.data` on the next clock
+    #: edge.
+    latch: In(1)
+    #: In(ASrc): Select input.
+    sel: In(ASrc)
+    #: Input source. Register from the
+    #: :class:`register file <sentinel_cpu.datapath.RegFile>`
+    #: whose value is currently on the read port (e.g. the read address was
+    #: supplied on the previous clock cycle).
+    gp: In(32)
+    #: Input source. :attr:`Decoded immediate <sentinel_cpu.decode.Decode.imm>`
+    #: from current instruction.
+    imm: In(32)
+    #: Input source. :attr:`Decoded immediate <sentinel_cpu.decode.Decode.imm>`
+    #: from current instruction.
+    alu: In(32)
+    #: The output. When :attr:`~sentinel_cpu.alu.ASrcMux.latch` is asserted,
+    #: the data input selected by :attr:`~sentinel_cpu.alu.ASrcMux.sel` will
+    #: appear here on the next clock cycle.
+    data: Out(32)
+
+    def elaborate(self, platform):  # noqa: D102
+        m = Module()
+
+        with m.If(self.latch):
+            with m.Switch(self.sel):
+                with m.Case(ASrc.GP):
+                    m.d.sync += self.data.eq(self.gp)
+                with m.Case(ASrc.IMM):
+                    m.d.sync += self.data.eq(self.imm)
+                with m.Case(ASrc.ZERO):
+                    m.d.sync += self.data.eq(0)
+                with m.Case(ASrc.ALU_O):
+                    m.d.sync += self.data.eq(self.alu)
+                with m.Case(ASrc.FOUR):
+                    m.d.sync += self.data.eq(4)
+                with m.Case(ASrc.THIRTY_ONE):
+                    m.d.sync += self.data.eq(31)
+
+        return m
+
+
+class BSrcMux(Component):
+    """Latch one of many :attr:`ALU B input <sentinel_cpu.alu.ALU.b>` sources.
+
+    The ALU does not have registered inputs; the
+    :attr:`~sentinel_cpu.alu.BSrcMux.data` output is registered and feeds
+    immediately into the ALU B input.
+
+    When requested, this module will automatically
+    :class:`move/align <sentinel_cpu.align.ReadDataAlign>` the top 16-bits
+    of the 32-bit :attr:`read data bus input <BSrcMux.dat_r>` to the bottom
+    16-bits, or any of of 3 high bytes into the bottom 8-bits. The mux will
+    latch the aligned data when :attr:`selected <sentinel_cpu.alu.BSrcMux.sel>`
+    rather than the original input data.
+    """
+
+    #: When asserted, latch the :attr:`selected <sentinel_cpu.alu.BSrcMux.sel>`
+    #: input into :attr:`~sentinel_cpu.alu.BSrcMux.data` on the next clock
+    #: edge.
+    latch: In(1)
+    #: In(BSrc): Select input.
+    sel: In(BSrc)
+
+    #: In(MemSel): Choose which slice of the input :attr:`dat_r` appears on the
+    #: `~BSrcMux.data` output when
+    #: :attr:`selected <sentinel_cpu.alu.BSrcMux.sel>`.
+    mem_sel: In(MemSel)
+    #: In(MemExtend): When :attr:`mem_sel` is less than word width, choose
+    #: whether to sign or zero-extend :attr:`dat_r` when it's output onto
+    #: :attr:`data`.
+    mem_extend: In(MemExtend)
+    #: Contents of the internal address register latched by
+    #: :class:`~sentinel_cpu.ucodefields.LatchAdr`. Used for deciding how to
+    #: align :attr:`dat_r`.
+    data_adr: In(32)
+
+    #: Input source. Register from the
+    #: :class:`register file <sentinel_cpu.datapath.RegFile>`
+    #: whose value is currently on the read port (e.g. the read address was
+    #: supplied on the previous clock cycle).
+    gp: In(32)
+    #: Input source. :attr:`Decoded immediate <sentinel_cpu.decode.Decode.imm>`
+    #: from current instruction.
+    imm: In(32)
+    #: Input source. Current contents of the
+    #: :class:`Program Counter <sentinel_cpu.datapath.ProgramCounter>`.
+    pc: In(30)
+    #: Input source. Current contents of the *unregistered* ``DAT_I``
+    #: in :attr:`Top's Wishbone Bus <sentinel_cpu.top.Top.bus>`. Only valid
+    #: when qualified by :attr:`~sentinel_cpu.ucodefields.CondTest.MEM_VALID`.
+    #:
+    #: As an input, ``DAT_I`` is always 32-bit aligned. The mux contains
+    #: :class:`internal alignment circuitry <sentinel_cpu.align.ReadDataAlign>`
+    #: when a read of 8 or 16-bits on a less-than-32-bit alignment is
+    #: requested. When :attr:`selected <sentinel_cpu.alu.BSrcMux.sel>`, the mux
+    #: will latched this modified/aligned data into :attr:`~BSrcMux.data`.
+    dat_r: In(32)
+    #: Input source. :attr:`Decoded src_a <sentinel_cpu.decode.Decode.src_a>`
+    #: from the current instruction, which for CSR instructions is reused
+    #: for specifying 5-bit CSR immediates.
+    csr_imm: In(5)
+    #: Input source. Register from the
+    #: :class:`CSR file <sentinel_cpu.datapath.CSRFile>`
+    #: whose value is currently on the read port (e.g. the read address was
+    #: supplied on the previous clock cycle).
+    csr: In(32)
+    #: In(MCause): Input source. Current ``MCAUSE`` as determined by
+    #: :class:`~sentinel_cpu.exception.ExceptionRouter`.
+    mcause: In(MCause)
+    #: The output. When :attr:`~sentinel_cpu.alu.BSrcMux.latch` is asserted,
+    #: the data input selected by :attr:`~sentinel_cpu.alu.BSrcMux.sel` will
+    #: appear here on the next clock cycle.
+    data: Out(32)
+
+    def __init__(self):
+        self.rdata_align = ReadDataAlign()
+        super().__init__()
+
+    def elaborate(self, platform):  # noqa: D102
+        m = Module()
+
+        m.submodules.rdata_align = self.rdata_align
+
+        m.d.comb += [
+            self.rdata_align.mem_sel.eq(self.mem_sel),
+            self.rdata_align.mem_extend.eq(self.mem_extend),
+            self.rdata_align.latched_adr.eq(self.data_adr),
+            self.rdata_align.wb_dat_r.eq(self.dat_r)
+        ]
+
+        with m.If(self.latch):
+            with m.Switch(self.sel):
+                with m.Case(BSrc.GP):
+                    m.d.sync += self.data.eq(self.gp)
+                with m.Case(BSrc.IMM):
+                    m.d.sync += self.data.eq(self.imm)
+                with m.Case(BSrc.ONE):
+                    m.d.sync += self.data.eq(1)
+                with m.Case(BSrc.PC):
+                    m.d.sync += self.data.eq(Cat(C(0, 2), self.pc))
+                with m.Case(BSrc.DAT_R):
+                    m.d.sync += self.data.eq(self.rdata_align.data)
+                with m.Case(BSrc.CSR_IMM):
+                    m.d.sync += self.data.eq(self.csr_imm)
+                with m.Case(BSrc.CSR):
+                    m.d.sync += self.data.eq(self.csr)
+                with m.Case(BSrc.MCAUSE_LATCH):
+                    m.d.sync += self.data.eq(self.mcause)
+
+        return m
+
+
+class ALU(Component):
+    """Basic Arithmetic Logic Unit.
+
+    The ALU Performs "A OP B", where "OP" is chosen by :attr:`ctrl`. More
+    operations can be synthesized from the ones directly supported by
+    :class:`sentinel_cpu.ucodefields.OpType` by using :attr:`ctrl` modifiers.
+
+    Parameters
+    ----------
+    width: int
+        Width in bits of the ALU inputs and output.
+
+    Attributes
+    ----------
+    a: In(width)
+        ALU A input.
+    b: In(width)
+        ALU B input.
+    o: Out(width)
+        ALU output. Valid 1 clock cycle after inputs.
+    ctrl: In(:attr:`~sentinel_cpu.alu.ALU.ControlSignature`)
+        Choose the ALU op to perform this cycle, possibly modifying the input
+        or output. Also check if the ALU op on the previous cycle was ``0``.
+    """
+
+    #: Signature: ALU microcode signals and useful state.
+    #:
+    #: The signature is of the form
+    #:
+    #: .. code-block::
+    #:
+    #:    Signature({
+    #:        "op": Out(OpType),
+    #:        "imod": Out(ALUIMod),
+    #:        "omod": Out(ALUOMod),
+    #:        "zero": In(1)
+    #:    })
+    #:
+    #: where
+    #:
+    #: .. py:attribute:: op
+    #:    :type: Out(~sentinel_cpu.ucodefields.OpType)
+    #:
+    #:    ALU operation to perform this cycle.
+    #:
+    #: .. py:attribute:: imod
+    #:    :type: Out(~sentinel_cpu.ucodefields.ALUIMod)
+    #:
+    #:    Modify the inputs :attr:`a` and :attr:`b` before doing ALU
+    #:    operation.
+    #:
+    #: .. py:attribute:: omod
+    #:    :type: Out(~sentinel_cpu.ucodefields.ALUOMod)
+    #:
+    #:    Modify the output after doing ALU operation, but before latching
+    #:    the ALU output into :attr:`o` (for next cycle).
+    #:
+    #: .. py:attribute:: zero
+    #:    :type: In(1)
+    #:
+    #:    Set if  the current :attr:`output <o>` (i.e. the result of the ALU
+    #:    operation done *last* cycle) is ``0``.
+    ControlSignature = Signature({
+        "op": Out(OpType),
+        "imod": Out(ALUIMod),
+        "omod": Out(ALUOMod),
+        "zero": In(1)
+    })
+
+    #: Signature: Useful microcode signals concerned with routing to the ALU.
+    #:
+    #: The ALU does not directly use this
+    #: :class:`~amaranth:amaranth.lib.wiring.Signature`; it is provided for
+    #: convenience to route data sources to the :class:`ASrcMux` and
+    #: :class:`BSrcMux`.
+    #:
+    #: The signature is of the form
+    #:
+    #: .. code-block::
+    #:
+    #:    Signature({
+    #:        "a_src": Out(ASrc),
+    #:        "b_src": Out(BSrc),
+    #:        "latch_a": Out(LatchA),
+    #:        "latch_b": Out(LatchB),
+    #:    })
+    #:
+    #: where
+    #:
+    #: .. py:attribute:: a_src
+    #:    :type: Out(~sentinel_cpu.ucodefields.ASrc)
+    #:
+    #:    :class:`ASrcMux` source to pass through this clock cycle.
+    #:
+    #: .. py:attribute:: b_src
+    #:    :type: Out(~sentinel_cpu.ucodefields.BSrc)
+    #:
+    #:    :class:`BSrcMux` source to pass through this clock cycle.
+    #:
+    #: .. py:attribute:: latch_a
+    #:    :type: Out(~sentinel_cpu.ucodefields.LatchA)
+    #:
+    #:    If set, latch the :attr:`selected <a_src>` source to the
+    #:    :attr:`ASrcMux output <ASrcMux.data>` this cycle.
+    #:
+    #:    :type: Out(:data:`~sentinel_cpu.ucodefields.LatchA`)
+    #:
+    #: .. py:attribute:: latch_b
+    #:    :type: Out(~sentinel_cpu.ucodefields.LatchB)
+    #:
+    #:    If set, latch the :attr:`selected <b_src>` source to the
+    #:    :attr:`BSrcMux output <BSrcMux.data>` this cycle.
+    #:
+    #:    :type: Out(:data:`~sentinel_cpu.ucodefields.LatchB`)
+    RoutingSignature = Signature({
+        "a_src": Out(ASrc),
+        "b_src": Out(BSrc),
+        "latch_a": Out(LatchA),
+        "latch_b": Out(LatchB),
+    })
+
+    class _Unit(Elaboratable):
+        """Wrapper class for implementing basic arithmetic/logic ops."""
+
+        def __init__(self, width, op):
+            self.a = Signal(width)
+            self.b = Signal(width)
+            self.o = Signal(width)
+            self.op = op
+
+        def elaborate(self, platform):
+            m = Module()
+            m.d.comb += self.o.eq(self.op(self.a, self.b))
+            return m
+
+    # Assumes: op is held steady for duration of op.
+    def __init__(self, width: int):
+        self.width = width
+        super().__init__(Signature({
+            "a": Out(self.width),
+            "b": Out(self.width),
+            "o": In(self.width),
+            "ctrl": Out(ALU.ControlSignature),
+        }).flip())
+
+        ###
+
+        self.o_mux = Signal(width)
+        self.add = ALU._Unit(width, lambda a, b: a + b)
+        self.sub = ALU._Unit(width + 1, lambda a, b: a - b)  # width + 1 for borrow bit.  # noqa: E501
+        self.and_ = ALU._Unit(width, lambda a, b: a & b)
+        self.or_ = ALU._Unit(width, lambda a, b: a | b)
+        self.xor = ALU._Unit(width, lambda a, b: a ^ b)
+        self.sll = ALU._Unit(width, lambda a, _: a << 1)
+        self.srl = ALU._Unit(width, lambda a, _: a >> 1)
+        self.sar = ALU._Unit(width, lambda a, _: a.as_signed() >> 1)
+
+    def elaborate(self, platform):  # noqa: D102
+        m = Module()
+        m.submodules.add = self.add
+        m.submodules.sub = self.sub
+        m.submodules.and_ = self.and_
+        m.submodules.or_ = self.or_
+        m.submodules.xor = self.xor
+        m.submodules.sll = self.sll
+        m.submodules.srl = self.srl
+        m.submodules.sal = self.sar
+
+        mod_a = Signal.like(self.a)
+        mod_b = Signal.like(self.b)
+
+        m.d.comb += [
+            mod_a.eq(self.a),
+            mod_b.eq(self.b)
+        ]
+
+        with m.If(self.ctrl.imod == ALUIMod.INV_MSB_A_B):
+            m.d.comb += [
+                mod_a[-1].eq(~self.a[-1]),
+                mod_b[-1].eq(~self.b[-1]),
+            ]
+
+        for submod in [self.add, self.sub, self.and_, self.or_, self.xor,
+                       self.sll, self.srl, self.sar]:
+            m.d.comb += [
+                submod.a.eq(mod_a),
+                submod.b.eq(mod_b),
+            ]
+
+        with m.Switch(self.ctrl.op):
+            with m.Case(OpType.ADD):
+                m.d.comb += self.o_mux.eq(self.add.o)
+            with m.Case(OpType.SUB):
+                m.d.comb += self.o_mux.eq(self.sub.o)
+            with m.Case(OpType.AND):
+                m.d.comb += self.o_mux.eq(self.and_.o)
+            with m.Case(OpType.OR):
+                m.d.comb += self.o_mux.eq(self.or_.o)
+            with m.Case(OpType.XOR):
+                m.d.comb += self.o_mux.eq(self.xor.o)
+            with m.Case(OpType.SLL):
+                m.d.comb += self.o_mux.eq(self.sll.o)
+            with m.Case(OpType.SRL):
+                m.d.comb += self.o_mux.eq(self.srl.o)
+            with m.Case(OpType.SRA):
+                m.d.comb += self.o_mux.eq(self.sar.o)
+            with m.Case(OpType.CMP_LTU):
+                m.d.comb += self.o_mux.eq(self.sub.o[32])
+
+        m.d.sync += self.o.eq(self.o_mux)
+        with m.If(self.ctrl.omod == ALUOMod.INV_LSB_O):
+            m.d.sync += self.o[0].eq(~self.o_mux[0])
+        with m.Elif(self.ctrl.omod == ALUOMod.CLEAR_LSB_O):
+            m.d.sync += self.o[0].eq(0)
+
+        # TODO: LSBS_2_ZERO for JALR/JAL misaligned exceptions?
+        m.d.comb += self.ctrl.zero.eq(self.o == 0)
+
+        return m