qiskit 2.0.2__cp39-abi3-macosx_11_0_arm64.whl → 2.1.0__cp39-abi3-macosx_11_0_arm64.whl

qiskit/synthesis/multi_controlled/multi_control_rotation_gates.py

@@ -171,30 +171,29 @@ def _mcsu2_real_diagonal(
     k_1 = math.ceil(num_controls / 2.0)
     k_2 = math.floor(num_controls / 2.0)
 
-    circuit = QuantumCircuit(num_controls + 1, name="MCSU2")
     controls = list(range(num_controls))  # control indices, defined for code legibility
     target = num_controls  # target index, defined for code legibility
 
+    mcx1 = synth_mcx_n_dirty_i15(num_ctrl_qubits=k_1)
+    mcx1_num_ancillas = mcx1.num_qubits - k_1 - 1
+    mcx1_qubits = controls[:k_1] + [target] + controls[k_1 : k_1 + mcx1_num_ancillas]
+
+    mcx2 = synth_mcx_n_dirty_i15(num_ctrl_qubits=k_2)
+    mcx2_num_ancillas = mcx2.num_qubits - k_2 - 1
+    mcx2_qubits = controls[k_1:] + [target] + controls[k_1 - mcx2_num_ancillas : k_1]
+
+    circuit = QuantumCircuit(num_controls + 1, name="MCSU2")
+
     if not is_secondary_diag_real:
         circuit.h(target)
 
-    mcx_1 = synth_mcx_n_dirty_i15(num_ctrl_qubits=k_1)
-    circuit.compose(mcx_1, controls[:k_1] + [target] + controls[k_1 : 2 * k_1 - 2], inplace=True)
+    circuit.compose(mcx1, mcx1_qubits, inplace=True)
     circuit.append(s_gate, [target])
-
-    # TODO: improve CX count by using action_only=True (based on #9687)
-    mcx_2 = synth_mcx_n_dirty_i15(num_ctrl_qubits=k_2).to_gate()
-    circuit.compose(
-        mcx_2.inverse(), controls[k_1:] + [target] + controls[k_1 - k_2 + 2 : k_1], inplace=True
-    )
+    circuit.compose(mcx2, mcx2_qubits, inplace=True)
     circuit.append(s_gate.inverse(), [target])
-
-    mcx_3 = synth_mcx_n_dirty_i15(num_ctrl_qubits=k_1).to_gate()
-    circuit.compose(mcx_3, controls[:k_1] + [target] + controls[k_1 : 2 * k_1 - 2], inplace=True)
+    circuit.compose(mcx1, mcx1_qubits, inplace=True)
     circuit.append(s_gate, [target])
-
-    mcx_4 = synth_mcx_n_dirty_i15(num_ctrl_qubits=k_2).to_gate()
-    circuit.compose(mcx_4, controls[k_1:] + [target] + controls[k_1 - k_2 + 2 : k_1], inplace=True)
+    circuit.compose(mcx2, mcx2_qubits, inplace=True)
     circuit.append(s_gate.inverse(), [target])
 
     if not is_secondary_diag_real:

qiskit/synthesis/qft/qft_decompose_lnn.py

@@ -13,9 +13,9 @@
 Circuit synthesis for a QFT circuit.
 """
 
-import numpy as np
 from qiskit.circuit import QuantumCircuit
-from qiskit.synthesis.permutation.permutation_reverse_lnn import _append_reverse_permutation_lnn_kms
+from qiskit._accelerate.synthesis.qft import synth_qft_line as _synth_qft_line
+
 from .qft_decompose_full import _warn_if_precision_loss
 
 
@@ -53,27 +53,9 @@ def synth_qft_line(
            `arXiv:quant-ph/0402196 [quant-ph] <https://arxiv.org/abs/quant-ph/0402196>`_
     """
     _warn_if_precision_loss(num_qubits - approximation_degree - 1)
-    qc = QuantumCircuit(num_qubits)
-
-    for i in range(num_qubits):
-        qc.h(num_qubits - 1)
-
-        for j in range(i, num_qubits - 1):
-            if j - i + 2 < num_qubits - approximation_degree + 1:
-                qc.p(np.pi / 2 ** (j - i + 2), num_qubits - j + i - 1)
-                qc.cx(num_qubits - j + i - 1, num_qubits - j + i - 2)
-                qc.p(-np.pi / 2 ** (j - i + 2), num_qubits - j + i - 2)
-                qc.cx(num_qubits - j + i - 2, num_qubits - j + i - 1)
-                qc.cx(num_qubits - j + i - 1, num_qubits - j + i - 2)
-                qc.p(np.pi / 2 ** (j - i + 2), num_qubits - j + i - 1)
-            else:
-                qc.cx(num_qubits - j + i - 1, num_qubits - j + i - 2)
-                qc.cx(num_qubits - j + i - 2, num_qubits - j + i - 1)
-                qc.cx(num_qubits - j + i - 1, num_qubits - j + i - 2)
-
-    if not do_swaps:
-        # Add a reversal network for LNN connectivity in depth 2*n+2,
-        # based on Kutin at al., https://arxiv.org/abs/quant-ph/0701194, Section 5.
-        _append_reverse_permutation_lnn_kms(qc, num_qubits)
 
-    return qc
+    return QuantumCircuit._from_circuit_data(
+        # From rust
+        _synth_qft_line(num_qubits, do_swaps, approximation_degree),
+        add_regs=True,
+    )

qiskit/synthesis/unitary/qsd.py

@@ -15,7 +15,6 @@ Quantum Shannon Decomposition.
 Method is described in arXiv:quant-ph/0406176.
 """
 from __future__ import annotations
-import math
 from typing import Callable
 import scipy
 import numpy as np
@@ -31,6 +30,7 @@ from qiskit.circuit.library.generalized_gates.uc_pauli_rot import UCPauliRotGate
 from qiskit.circuit.library.generalized_gates.ucry import UCRYGate
 from qiskit.circuit.library.generalized_gates.ucrz import UCRZGate
 from qiskit._accelerate.two_qubit_decompose import two_qubit_decompose_up_to_diagonal
+from qiskit._accelerate.cos_sin_decomp import cossin
 
 
 def qs_decomposition(
@@ -96,7 +96,8 @@ def qs_decomposition(
     """
     #  _depth (int): Internal use parameter to track recursion depth.
     dim = mat.shape[0]
-    nqubits = int(math.log2(dim))
+    nqubits = dim.bit_length() - 1
+
     if np.allclose(np.identity(dim), mat):
         return QuantumCircuit(nqubits)
     if dim == 2:
@@ -121,11 +122,25 @@ def qs_decomposition(
                 decomposer_2q = TwoQubitBasisDecomposer(CXGate())
         circ = decomposer_2q(mat)
     else:
+        # check whether matrix is equivalent to block diagonal wrt ctrl_index
+        if opt_a2 is False:
+            for ctrl_index in range(nqubits):
+                um00, um11, um01, um10 = _extract_multiplex_blocks(mat, ctrl_index)
+                # the ctrl_index is reversed here
+                if _off_diagonals_are_zero(um01, um10):
+                    decirc = _demultiplex(
+                        um00,
+                        um11,
+                        opt_a1=opt_a1,
+                        opt_a2=opt_a2,
+                        _depth=_depth,
+                        _ctrl_index=nqubits - 1 - ctrl_index,
+                    )
+                    return decirc
         qr = QuantumRegister(nqubits)
         circ = QuantumCircuit(qr)
-        dim_o2 = dim // 2
         # perform cosine-sine decomposition
-        (u1, u2), vtheta, (v1h, v2h) = scipy.linalg.cossin(mat, separate=True, p=dim_o2, q=dim_o2)
+        (u1, u2), vtheta, (v1h, v2h) = cossin(np.asarray(mat, dtype=complex))
         # left circ
         left_circ = _demultiplex(v1h, v2h, opt_a1=opt_a1, opt_a2=opt_a2, _depth=_depth)
         circ.append(left_circ.to_instruction(), qr)
@@ -150,7 +165,7 @@ def qs_decomposition(
     return circ
 
 
-def _demultiplex(um0, um1, opt_a1=False, opt_a2=False, *, _depth=0):
+def _demultiplex(um0, um1, opt_a1=False, opt_a2=False, *, _depth=0, _ctrl_index=None):
     """Decompose a generic multiplexer.
 
           ────□────
@@ -183,12 +198,17 @@ def _demultiplex(um0, um1, opt_a1=False, opt_a2=False, *, _depth=0):
           unitaries into a diagonal gate and a two cx unitary and reduces overall cx count by
           4^(n-2) - 1.
        _depth (int): This is an internal variable to track the recursion depth.
+       _ctrl_index (int): The index wrt which um0 and um1 are controlled.
 
     Returns:
         QuantumCircuit: decomposed circuit
     """
     dim = um0.shape[0] + um1.shape[0]  # these should be same dimension
-    nqubits = int(math.log2(dim))
+    nqubits = dim.bit_length() - 1
+    if _ctrl_index is None:
+        _ctrl_index = nqubits - 1
+    layout = list(range(0, _ctrl_index)) + list(range(_ctrl_index + 1, nqubits)) + [_ctrl_index]
+
     um0um1 = um0 @ um1.T.conjugate()
     if is_hermitian_matrix(um0um1):
         eigvals, vmat = scipy.linalg.eigh(um0um1)
@@ -205,18 +225,18 @@ def _demultiplex(um0, um1, opt_a1=False, opt_a2=False, *, _depth=0):
     left_gate = qs_decomposition(
         wmat, opt_a1=opt_a1, opt_a2=opt_a2, _depth=_depth + 1
     ).to_instruction()
-    circ.append(left_gate, range(nqubits - 1))
+    circ.append(left_gate, layout[: nqubits - 1])
 
     # multiplexed Rz
     angles = 2 * np.angle(np.conj(dvals))
     ucrz = UCRZGate(angles.tolist())
-    circ.append(ucrz, [nqubits - 1] + list(range(nqubits - 1)))
+    circ.append(ucrz, [layout[-1]] + layout[: nqubits - 1])
 
     # right gate
     right_gate = qs_decomposition(
         vmat, opt_a1=opt_a1, opt_a2=opt_a2, _depth=_depth + 1
     ).to_instruction()
-    circ.append(right_gate, range(nqubits - 1))
+    circ.append(right_gate, layout[: nqubits - 1])
 
     return circ
 
@@ -286,3 +306,54 @@ def _apply_a2(circ):
     qc3 = two_qubit_decompose.two_qubit_cnot_decompose(mat2)
     ccirc.data[ind2] = ccirc.data[ind2].replace(operation=qc3.to_gate())
     return ccirc
+
+
+def _extract_multiplex_blocks(umat, k):
+    """
+    A block diagonal gate is represented as:
+    [ um00 | um01 ]
+    [ ---- | ---- ]
+    [ um10 | um11 ]
+    Args:
+       umat (ndarray): unitary matrix
+       k (integer): qubit which indicates the ctrl index
+    Returns:
+       um00 (ndarray): upper left block
+       um01 (ndarray): upper right block
+       um10 (ndarray): lower left block
+       um11 (ndarray): lower right block
+    """
+    dim = umat.shape[0]
+    nqubits = dim.bit_length() - 1
+    halfdim = dim // 2
+
+    utensor = umat.reshape((2,) * (2 * nqubits))
+
+    # Move qubit k to top
+    if k != 0:
+        utensor = np.moveaxis(utensor, k, 0)
+        utensor = np.moveaxis(utensor, k + nqubits, nqubits)
+
+    # reshape for extraction
+    ud4 = utensor.reshape(2, halfdim, 2, halfdim)
+    # block for qubit k = |0>
+    um00 = ud4[0, :, 0, :]
+    # block for qubit k = |1>
+    um11 = ud4[1, :, 1, :]
+    # off diagonal blocks
+    um01 = ud4[0, :, 1, :]
+    um10 = ud4[1, :, 0, :]
+    return um00, um11, um01, um10
+
+
+def _off_diagonals_are_zero(um01, um10, atol=1e-12):
+    """
+    Checks whether off-diagonal blocks are zero.
+    Args:
+       um01 (ndarray): upper right block
+       um10 (ndarray): lower left block
+       atol (float): absolute tolerance
+    Returns:
+       bool: whether both blocks are zero within tolerance
+    """
+    return np.allclose(um01, 0, atol=atol) and np.allclose(um10, 0, atol=atol)

qiskit/transpiler/__init__.py

@@ -237,7 +237,7 @@ Initialization stage
 --------------------
 
 .. seealso::
-    `Init stage explanation <https://docs.quantum.ibm.com/guides/transpiler-stages#init-stage>`__
+    `Init stage explanation <https://quantum.cloud.ibm.com/docs/guides/transpiler-stages#init-stage>`__
         Higher-level user-facing explanation of the init stage in the IBM Quantum guide.
 
 The ``init`` stage is responsible for high-level, logical optimizations on abstract circuits, and
@@ -291,9 +291,11 @@ Layout stage
 ------------
 
 .. seealso::
-    `Layout stage explanation <https://docs.quantum.ibm.com/guides/transpiler-stages#layout-stage>`__
+    `Layout stage explanation`__
         Higher-level user-facing explanation of the layout stage in the IBM Quantum guide.
 
+__ https://quantum.cloud.ibm.com/docs/guides/transpiler-stages#layout-stage
+
 The layout stage is responsible for making an initial mapping between the virtual qubits of the
 input circuit, and the hardware qubits of the target.  This includes expanding the input circuit
 with explicit ancillas so it has as many qubits as the target has, and rewriting all operations in
@@ -452,9 +454,11 @@ Routing stage
 -------------
 
 .. seealso::
-    `Routing stage explanation <https://docs.quantum.ibm.com/guides/transpiler-stages#routing-stage>`__
+    `Routing stage explanation`__
         Higher-level user-facing explanation of the routing stage in the IBM Quantum guide.
 
+__ https://quantum.cloud.ibm.com/docs/guides/transpiler-stages#routing-stage
+
 The routing stage ensures that the virtual connectivity graph of the circuit is compatible with the
 hardware connectivity graph of the target.  In simpler terms, the routing stage makes sure that all
 two-qubit gates in the circuit are mapped to hardware qubits that have a defined two-qubit operation
@@ -598,7 +602,7 @@ Translation stage
     `Translation stage explanation`__
         Higher-level user-facing explanation of the translation stage in the IBM Quantum guide.
 
-.. __: https://docs.quantum.ibm.com/guides/transpiler-stages#translation-stage
+.. __: https://quantum.cloud.ibm.com/docs/guides/transpiler-stages#translation-stage
 
 The translation stage is responsible for rewriting all gates in the circuit into ones that are
 supported by the target ISA.  For example, if a ``cx`` is requested on hardware qubits 0 and 1, but
@@ -673,6 +677,9 @@ At a high level, this starts from the set of gates requested by the circuit, and
 given :class:`.EquivalenceLibrary` (typically the :data:`.SessionEquivalenceLibrary`) to move
 towards the ISA.
 
+For a Clifford+T basis set, the single-qubit rotation gates are approximated using the
+:class:`.SolovayKitaevDecomposition` algorithm.
+
 This is the default translation method.
 
 The optimization level has no effect on this plugin.
@@ -687,7 +694,7 @@ Optimization stage
     `Optimization stage explanation`__
         Higher-level user-facing explanation of the optimization stage in the IBM Quantum guide.
 
-.. __: https://docs.quantum.ibm.com/guides/transpiler-stages#optimization-stage
+.. __: https://quantum.cloud.ibm.com/docs/guides/transpiler-stages#optimization-stage
 
 The optimization stage is for low-level hardware-aware optimizations.  Unlike :ref:`the init stage
 <transpiler-preset-stage-init>`, the input to this stage is a circuit that is already
@@ -700,7 +707,7 @@ as a fix-up pipeline.
 
 Qiskit's built-in optimization plugins are general, and apply well to most real-world ISAs for
 non-error-corrected devices.  The built-in plugins are less well-suited to ISAs that have no
-continuously parametrized single-qubit gate, such as a Clifford+T basis set.
+continuously parametrized single-qubit gate.
 
 When writing :ref:`stage plugins <transpiler-preset-stage-plugins>`, the entry point for
 ``optimization`` is ``qiskit.transpiler.optimization``.  The built-in plugins are:
@@ -720,10 +727,12 @@ When writing :ref:`stage plugins <transpiler-preset-stage-plugins>`, the entry p
 Built-in ``default`` plugin
 ...........................
 
-This varies significantly between optimization levels.
+This varies significantly depending on the optimization level and whether the basis set is of the
+form Clifford+T.
 
 The specifics of this pipeline are subject to change between Qiskit versions. The broad principles
-are described below.
+are described below. First, consider the more common case that the basis set is not of the form
+Clifford+T.
 
 At optimization level 0, the stage is empty.
 
@@ -740,6 +749,8 @@ The optimization loop condition also tries multiple runs and chooses the minimum
 of fluctuating output; this is necessary because matrix-based resynthesis is relatively unstable in
 terms of concrete gates.
 
+For a Clifford+T basis set, two-qubit matrix based resynthesis is not applied.
+
 Optimization level 3 is typically very expensive for large circuits.
 
 

qiskit/transpiler/instruction_durations.py

@@ -74,30 +74,12 @@ class InstructionDurations:
 
         Raises:
             TranspilerError: If dt and dtm is different in the backend.
+            TypeError: If the backend is the wrong type
         """
         # All durations in seconds in gate_length
         if isinstance(backend, BackendV2):
             return backend.target.durations()
-
-        instruction_durations = []
-        backend_properties = backend.properties()
-        if hasattr(backend_properties, "_gates"):
-            for gate, insts in backend_properties._gates.items():
-                for qubits, props in insts.items():
-                    if "gate_length" in props:
-                        gate_length = props["gate_length"][0]  # Throw away datetime at index 1
-                        instruction_durations.append((gate, qubits, gate_length, "s"))
-            for q, props in backend.properties()._qubits.items():
-                if "readout_length" in props:
-                    readout_length = props["readout_length"][0]  # Throw away datetime at index 1
-                    instruction_durations.append(("measure", [q], readout_length, "s"))
-
-        try:
-            dt = backend.configuration().dt
-        except AttributeError:
-            dt = None
-
-        return cls(instruction_durations, dt=dt)
+        raise TypeError("Unsupported backend type: {backend}")
 
     def update(self, inst_durations: "InstructionDurationsType" | None, dt: float = None):
         """Update self with inst_durations (inst_durations overwrite self).

qiskit/transpiler/passes/__init__.py

@@ -91,7 +91,7 @@ Optimizations
    Split2QUnitaries
    RemoveIdentityEquivalent
    ContractIdleWiresInControlFlow
-   LightCone
+   OptimizeCliffordT
 
 Scheduling
 =============
@@ -102,6 +102,7 @@ Scheduling
    TimeUnitConversion
    ALAPScheduleAnalysis
    ASAPScheduleAnalysis
+   ContextAwareDynamicalDecoupling
    PadDynamicalDecoupling
    PadDelay
    ConstrainedReschedule
@@ -226,7 +227,7 @@ from .optimization import OptimizeAnnotated
 from .optimization import RemoveIdentityEquivalent
 from .optimization import Split2QUnitaries
 from .optimization import ContractIdleWiresInControlFlow
-from .optimization import LightCone
+from .optimization import OptimizeCliffordT
 
 # circuit analysis
 from .analysis import ResourceEstimation
@@ -246,6 +247,7 @@ from .synthesis import HighLevelSynthesis
 from .synthesis import HLSConfig
 from .synthesis import SolovayKitaev
 from .synthesis import SolovayKitaevSynthesis
+from .synthesis import CliffordUnitarySynthesis
 from .synthesis import AQCSynthesisPlugin
 
 # circuit scheduling
@@ -257,6 +259,7 @@ from .scheduling import PadDelay
 from .scheduling import ConstrainedReschedule
 from .scheduling import InstructionDurationCheck
 from .scheduling import SetIOLatency
+from .scheduling import ContextAwareDynamicalDecoupling
 
 # additional utility passes
 from .utils import CheckMap

qiskit/transpiler/passes/layout/apply_layout.py

@@ -48,11 +48,11 @@ class ApplyLayout(TransformationPass):
             TranspilerError: if no layout is found in ``property_set`` or no full physical qubits.
         """
         layout = self.property_set["layout"]
-        if not layout:
+        if layout is None:
             raise TranspilerError(
                 "No 'layout' is found in property_set. Please run a Layout pass in advance."
             )
-        if len(layout) != (1 + max(layout.get_physical_bits())):
+        if len(layout) != (1 + max(layout.get_physical_bits(), default=-1)):
             raise TranspilerError("The 'layout' must be full (with ancilla).")
 
         post_layout = self.property_set["post_layout"]

qiskit/transpiler/passes/layout/dense_layout.py

@@ -19,7 +19,8 @@ import rustworkx
 from qiskit.transpiler.layout import Layout
 from qiskit.transpiler.basepasses import AnalysisPass
 from qiskit.transpiler.exceptions import TranspilerError
-from qiskit.transpiler.passes.layout import disjoint_utils
+from qiskit.transpiler.target import Target
+from qiskit._accelerate import disjoint_utils
 
 from qiskit._accelerate.dense_layout import best_subset
 
@@ -66,11 +67,30 @@ class DenseLayout(AnalysisPass):
             raise TranspilerError(
                 "A coupling_map or target with constrained qargs is necessary to run the pass."
             )
-        layout_components = disjoint_utils.run_pass_over_connected_components(
-            dag,
-            self.coupling_map if self.target is None else self.target,
-            self._inner_run,
-        )
+        if self.target is not None:
+            layout_components = disjoint_utils.run_pass_over_connected_components(
+                dag,
+                self.target,
+                self._inner_run,
+            )
+            if layout_components is None:
+                target = Target.from_configuration(
+                    basis_gates=["u", "cx"], coupling_map=self.coupling_map
+                )
+                layout_components = disjoint_utils.run_pass_over_connected_components(
+                    dag,
+                    target,
+                    self._inner_run,
+                )
+        else:
+            target = Target.from_configuration(
+                basis_gates=["u", "cx"], coupling_map=self.coupling_map
+            )
+            layout_components = disjoint_utils.run_pass_over_connected_components(
+                dag,
+                target,
+                self._inner_run,
+            )
         layout_mapping = {}
         for component in layout_components:
             layout_mapping.update(component)

qiskit/transpiler/passes/layout/disjoint_utils.py

@@ -12,143 +12,12 @@
 
 """This module contains common utils for disjoint coupling maps."""
 from __future__ import annotations
-from collections import defaultdict
-from typing import List, Callable, TypeVar, Dict, Union
-import uuid
+from typing import Union
 
-import rustworkx as rx
-from qiskit.dagcircuit import DAGOpNode
-
-from qiskit.circuit import Qubit, Barrier, Clbit
 from qiskit.dagcircuit.dagcircuit import DAGCircuit
-from qiskit.dagcircuit.dagnode import DAGOutNode
 from qiskit.transpiler.coupling import CouplingMap
 from qiskit.transpiler.target import Target
 from qiskit.transpiler.exceptions import TranspilerError
-from qiskit.transpiler.passes.layout import vf2_utils
-
-T = TypeVar("T")
-
-
-def run_pass_over_connected_components(
-    dag: DAGCircuit,
-    components_source: Union[Target, CouplingMap],
-    run_func: Callable[[DAGCircuit, CouplingMap], T],
-) -> List[T]:
-    """Run a transpiler pass inner function over mapped components."""
-    if isinstance(components_source, Target):
-        coupling_map = components_source.build_coupling_map(filter_idle_qubits=True)
-    else:
-        coupling_map = components_source
-    cmap_components = coupling_map.connected_components()
-    # If graph is connected we only need to run the pass once
-    if len(cmap_components) == 1:
-        if dag.num_qubits() > cmap_components[0].size():
-            raise TranspilerError(
-                "A connected component of the DAGCircuit is too large for any of the connected "
-                "components in the coupling map."
-            )
-        return [run_func(dag, cmap_components[0])]
-    dag_components = separate_dag(dag)
-    mapped_components = map_components(dag_components, cmap_components)
-    out_component_pairs = []
-    for cmap_index, dags in mapped_components.items():
-        # Take the first dag from the mapped dag components and then
-        # compose it with any other dag components that are operating on the
-        # same coupling map connected component. This results in a subcircuit
-        # of possibly disjoint circuit components which we will run the layout
-        # pass on.
-        out_dag = dag_components[dags.pop()]
-        for dag_index in dags:
-            dag = dag_components[dag_index]
-            out_dag.add_qubits(dag.qubits)
-            out_dag.add_clbits(dag.clbits)
-            for qreg in dag.qregs:
-                out_dag.add_qreg(qreg)
-            for creg in dag.cregs:
-                out_dag.add_creg(creg)
-            out_dag.compose(dag, qubits=dag.qubits, clbits=dag.clbits)
-        out_component_pairs.append((out_dag, cmap_components[cmap_index]))
-    res = [run_func(out_dag, cmap) for out_dag, cmap in out_component_pairs]
-    return res
-
-
-def map_components(
-    dag_components: List[DAGCircuit], cmap_components: List[CouplingMap]
-) -> Dict[int, List[int]]:
-    """Returns a map where the key is the index of each connected component in cmap_components and
-    the value is a list of indices from dag_components which should be placed onto it."""
-    free_qubits = {index: len(cmap.graph) for index, cmap in enumerate(cmap_components)}
-    out_mapping = defaultdict(list)
-
-    for dag_index, dag in sorted(
-        enumerate(dag_components), key=lambda x: x[1].num_qubits(), reverse=True
-    ):
-        for cmap_index in sorted(
-            range(len(cmap_components)), key=lambda index: free_qubits[index], reverse=True
-        ):
-            # TODO: Improve heuristic to involve connectivity and estimate
-            # swap cost
-            if dag.num_qubits() <= free_qubits[cmap_index]:
-                out_mapping[cmap_index].append(dag_index)
-                free_qubits[cmap_index] -= dag.num_qubits()
-                break
-        else:
-            raise TranspilerError(
-                "A connected component of the DAGCircuit is too large for any of the connected "
-                "components in the coupling map."
-            )
-    return out_mapping
-
-
-def split_barriers(dag: DAGCircuit):
-    """Mutate an input dag to split barriers into single qubit barriers."""
-    for node in dag.op_nodes(Barrier):
-        num_qubits = len(node.qargs)
-        if num_qubits == 1:
-            continue
-        if node.label:
-            barrier_uuid = f"{node.op.label}_uuid={uuid.uuid4()}"
-        else:
-            barrier_uuid = f"_none_uuid={uuid.uuid4()}"
-        split_dag = DAGCircuit()
-        split_dag.add_qubits([Qubit() for _ in range(num_qubits)])
-        for i in range(num_qubits):
-            split_dag.apply_operation_back(
-                Barrier(1, label=barrier_uuid),
-                qargs=(split_dag.qubits[i],),
-                check=False,
-            )
-        dag.substitute_node_with_dag(node, split_dag)
-
-
-def combine_barriers(dag: DAGCircuit, retain_uuid: bool = True):
-    """Mutate input dag to combine barriers with UUID labels into a single barrier."""
-    qubit_indices = {bit: index for index, bit in enumerate(dag.qubits)}
-    uuid_map: dict[str, DAGOpNode] = {}
-    for node in dag.op_nodes(Barrier):
-        if node.label:
-            if "_uuid=" in node.label:
-                barrier_uuid = node.label
-            else:
-                continue
-            if barrier_uuid in uuid_map:
-                other_node = uuid_map[barrier_uuid]
-                num_qubits = len(other_node.qargs) + len(node.qargs)
-                if not retain_uuid:
-                    if isinstance(node.label, str) and node.label.startswith("_none_uuid="):
-                        label = None
-                    elif isinstance(node.label, str) and "_uuid=" in node.label:
-                        label = "_uuid=".join(node.label.split("_uuid=")[:-1])
-                    else:
-                        label = barrier_uuid
-                else:
-                    label = barrier_uuid
-                new_op = Barrier(num_qubits, label=label)
-                new_node = dag.replace_block_with_op([node, other_node], new_op, qubit_indices)
-                uuid_map[barrier_uuid] = new_node
-            else:
-                uuid_map[barrier_uuid] = node
 
 
 def require_layout_isolated_to_component(
@@ -183,37 +52,3 @@ def require_layout_isolated_to_component(
                 f"{dag.find_bit(inst.qargs[1]).index} needs to interact with the "
                 f"qubit {dag.find_bit(inst.qargs[0]).index} and they belong to different components"
             )
-
-
-def separate_dag(dag: DAGCircuit) -> List[DAGCircuit]:
-    """Separate a dag circuit into it's connected components."""
-    # Split barriers into single qubit barriers before splitting connected components
-    split_barriers(dag)
-    im_graph, _, qubit_map, __ = vf2_utils.build_interaction_graph(dag)
-    connected_components = rx.weakly_connected_components(im_graph)
-    component_qubits = []
-    for component in connected_components:
-        component_qubits.append({qubit_map[x] for x in component})
-
-    qubits = set(dag.qubits)
-
-    decomposed_dags = []
-    for dag_qubits in component_qubits:
-        new_dag = dag.copy_empty_like()
-        new_dag.remove_qubits(*qubits - dag_qubits)
-        new_dag.global_phase = 0
-        for node in dag.topological_op_nodes():
-            if dag_qubits.issuperset(node.qargs):
-                new_dag.apply_operation_back(node.op, node.qargs, node.cargs, check=False)
-        idle_clbits = []
-        for bit, node in new_dag.input_map.items():
-            succ_node = next(new_dag.successors(node))
-            if isinstance(succ_node, DAGOutNode) and isinstance(succ_node.wire, Clbit):
-                idle_clbits.append(bit)
-        new_dag.remove_clbits(*idle_clbits)
-        combine_barriers(new_dag)
-        decomposed_dags.append(new_dag)
-    # Reverse split barriers on input dag to avoid leaking out internal transformations as
-    # part of splitting
-    combine_barriers(dag, retain_uuid=False)
-    return decomposed_dags