qiskit 1.3.0__cp39-abi3-macosx_11_0_arm64.whl

qiskit/transpiler/passes/scheduling/alignments/reschedule.py

@@ -0,0 +1,250 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2022, 2024.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""Rescheduler pass to adjust node start times."""
+from __future__ import annotations
+from collections.abc import Generator
+
+from qiskit.circuit.gate import Gate
+from qiskit.circuit.delay import Delay
+from qiskit.circuit.measure import Measure
+from qiskit.circuit.reset import Reset
+from qiskit.dagcircuit import DAGCircuit, DAGOpNode, DAGOutNode
+from qiskit.transpiler.basepasses import AnalysisPass
+from qiskit.transpiler.exceptions import TranspilerError
+from qiskit.transpiler.target import Target
+
+
+class ConstrainedReschedule(AnalysisPass):
+    """Rescheduler pass that updates node start times to conform to the hardware alignments.
+
+    This pass shifts DAG node start times previously scheduled with one of
+    the scheduling passes, e.g. :class:`ASAPScheduleAnalysis` or :class:`ALAPScheduleAnalysis`,
+    so that every instruction start time satisfies alignment constraints.
+
+    Examples:
+
+        We assume executing the following circuit on a backend with 16 dt of acquire alignment.
+
+        .. code-block:: text
+
+                 ┌───┐┌────────────────┐┌─┐
+            q_0: ┤ X ├┤ Delay(100[dt]) ├┤M├
+                 └───┘└────────────────┘└╥┘
+            c: 1/════════════════════════╩═
+                                         0
+
+        Note that delay of 100 dt induces a misalignment of 4 dt at the measurement.
+        This pass appends an extra 12 dt time shift to the input circuit.
+
+        .. code-block:: text
+
+                 ┌───┐┌────────────────┐┌─┐
+            q_0: ┤ X ├┤ Delay(112[dt]) ├┤M├
+                 └───┘└────────────────┘└╥┘
+            c: 1/════════════════════════╩═
+                                         0
+
+    Notes:
+
+        Your backend may execute circuits violating these alignment constraints.
+        However, you may obtain erroneous measurement result because of the
+        untracked phase originating in the instruction misalignment.
+    """
+
+    def __init__(
+        self,
+        acquire_alignment: int = 1,
+        pulse_alignment: int = 1,
+        target: Target = None,
+    ):
+        """Create new rescheduler pass.
+
+        The alignment values depend on the control electronics of your quantum processor.
+
+        Args:
+            acquire_alignment: Integer number representing the minimum time resolution to
+                trigger acquisition instruction in units of ``dt``.
+            pulse_alignment: Integer number representing the minimum time resolution to
+                trigger gate instruction in units of ``dt``.
+            target: The :class:`~.Target` representing the target backend, if
+                ``target`` is specified then this argument will take
+                precedence and ``acquire_alignment`` and ``pulse_alignment`` will be ignored.
+        """
+        super().__init__()
+        self.acquire_align = acquire_alignment
+        self.pulse_align = pulse_alignment
+        if target is not None:
+            self.acquire_align = target.acquire_alignment
+            self.pulse_align = target.pulse_alignment
+
+    @classmethod
+    def _get_next_gate(cls, dag: DAGCircuit, node: DAGOpNode) -> Generator[DAGOpNode, None, None]:
+        """Get next non-delay nodes.
+
+        Args:
+            dag: DAG circuit to be rescheduled with constraints.
+            node: Current node.
+
+        Returns:
+            A list of non-delay successors.
+        """
+        for next_node in dag.successors(node):
+            if not isinstance(next_node, DAGOutNode):
+                yield next_node
+
+    def _push_node_back(self, dag: DAGCircuit, node: DAGOpNode):
+        """Update the start time of the current node to satisfy alignment constraints.
+        Immediate successors are pushed back to avoid overlap and will be processed later.
+
+        .. note::
+
+            This logic assumes the all bits in the qregs and cregs synchronously start and end,
+            i.e. occupy the same time slot, but qregs and cregs can take
+            different time slot due to classical I/O latencies.
+
+        Args:
+            dag: DAG circuit to be rescheduled with constraints.
+            node: Current node.
+        """
+        node_start_time = self.property_set["node_start_time"]
+        conditional_latency = self.property_set.get("conditional_latency", 0)
+        clbit_write_latency = self.property_set.get("clbit_write_latency", 0)
+
+        if isinstance(node.op, Gate):
+            alignment = self.pulse_align
+        elif isinstance(node.op, (Measure, Reset)):
+            alignment = self.acquire_align
+        elif isinstance(node.op, Delay) or getattr(node.op, "_directive", False):
+            # Directive or delay. These can start at arbitrary time.
+            alignment = None
+        else:
+            raise TranspilerError(f"Unknown operation type for {repr(node)}.")
+
+        this_t0 = node_start_time[node]
+
+        if alignment is not None:
+            misalignment = node_start_time[node] % alignment
+            if misalignment != 0:
+                shift = max(0, alignment - misalignment)
+            else:
+                shift = 0
+            this_t0 += shift
+            node_start_time[node] = this_t0
+
+        # Compute shifted t1 of this node separately for qreg and creg
+        new_t1q = this_t0 + node.op.duration
+        this_qubits = set(node.qargs)
+        if isinstance(node.op, (Measure, Reset)):
+            # creg access ends at the end of instruction
+            new_t1c = new_t1q
+            this_clbits = set(node.cargs)
+        else:
+            if node.op.condition_bits:
+                # conditional access ends at the beginning of node start time
+                new_t1c = this_t0
+                this_clbits = set(node.op.condition_bits)
+            else:
+                new_t1c = None
+                this_clbits = set()
+
+        # Check immediate successors for overlap
+        for next_node in self._get_next_gate(dag, node):
+            # Compute next node start time separately for qreg and creg
+            next_t0q = node_start_time[next_node]
+            next_qubits = set(next_node.qargs)
+            if isinstance(next_node.op, (Measure, Reset)):
+                # creg access starts after write latency
+                next_t0c = next_t0q + clbit_write_latency
+                next_clbits = set(next_node.cargs)
+            else:
+                if next_node.op.condition_bits:
+                    # conditional access starts before node start time
+                    next_t0c = next_t0q - conditional_latency
+                    next_clbits = set(next_node.op.condition_bits)
+                else:
+                    next_t0c = None
+                    next_clbits = set()
+            # Compute overlap if there is qubits overlap
+            if any(this_qubits & next_qubits):
+                qreg_overlap = new_t1q - next_t0q
+            else:
+                qreg_overlap = 0
+            # Compute overlap if there is clbits overlap
+            if any(this_clbits & next_clbits):
+                creg_overlap = new_t1c - next_t0c
+            else:
+                creg_overlap = 0
+
+            # Shift next node if there is finite overlap in either in qubits or clbits
+            overlap = max(qreg_overlap, creg_overlap)
+            node_start_time[next_node] = node_start_time[next_node] + overlap
+
+    def run(self, dag: DAGCircuit):
+        """Run rescheduler.
+
+        This pass should perform rescheduling to satisfy:
+
+            - All DAGOpNode nodes (except for compiler directives) are placed at start time
+              satisfying hardware alignment constraints.
+            - The end time of a node does not overlap with the start time of successor nodes.
+
+        Assumptions:
+
+            - Topological order and absolute time order of DAGOpNode are consistent.
+            - All bits in either qargs or cargs associated with node synchronously start.
+            - Start time of qargs and cargs may different due to I/O latency.
+
+        Based on the configurations above, the rescheduler pass takes the following strategy:
+
+        1. The nodes are processed in the topological order, from the beginning of
+            the circuit (i.e. from left to right). For every node (including compiler
+            directives), the function ``_push_node_back`` performs steps 2 and 3.
+        2. If the start time of the node violates the alignment constraint,
+            the start time is increased to satisfy the constraint.
+        3. Each immediate successor whose start_time overlaps the node's end_time is
+            pushed backwards (towards the end of the wire). Note that at this point
+            the shifted successor does not need to satisfy the constraints, but this
+            will be taken care of when that successor node itself is processed.
+        4. After every node is processed, all misalignment constraints will be resolved,
+            and there will be no overlap between the nodes.
+
+        Args:
+            dag: DAG circuit to be rescheduled with constraints.
+
+        Raises:
+            TranspilerError: If circuit is not scheduled.
+        """
+
+        if "node_start_time" not in self.property_set:
+            raise TranspilerError(
+                f"The input circuit {dag.name} is not scheduled. Call one of scheduling passes "
+                f"before running the {self.__class__.__name__} pass."
+            )
+
+        node_start_time = self.property_set["node_start_time"]
+
+        for node in dag.topological_op_nodes():
+
+            start_time = node_start_time.get(node)
+
+            if start_time is None:
+                raise TranspilerError(
+                    f"Start time of {repr(node)} is not found. This node is likely added after "
+                    "this circuit is scheduled. Run scheduler again."
+                )
+
+            if start_time == 0:
+                # Every instruction can start at t=0.
+                continue
+
+            self._push_node_back(dag, node)

qiskit/transpiler/passes/scheduling/asap.py

@@ -0,0 +1,175 @@
+# This code is part of Qiskit.
+#
+# (C) Copyright IBM 2020.
+#
+# This code is licensed under the Apache License, Version 2.0. You may
+# obtain a copy of this license in the LICENSE.txt file in the root directory
+# of this source tree or at http://www.apache.org/licenses/LICENSE-2.0.
+#
+# Any modifications or derivative works of this code must retain this
+# copyright notice, and modified files need to carry a notice indicating
+# that they have been altered from the originals.
+
+"""ASAP Scheduling."""
+
+from qiskit.circuit import Delay, Qubit, Measure
+from qiskit.dagcircuit import DAGCircuit
+from qiskit.transpiler.exceptions import TranspilerError
+from qiskit.transpiler.passes.scheduling.base_scheduler import BaseSchedulerTransform
+from qiskit.utils.deprecation import deprecate_func
+
+
+class ASAPSchedule(BaseSchedulerTransform):
+    """ASAP Scheduling pass, which schedules the start time of instructions as early as possible..
+
+    See :class:`~qiskit.transpiler.passes.scheduling.base_scheduler.BaseSchedulerTransform` for the
+    detailed behavior of the control flow operation, i.e. ``c_if``.
+
+    .. note::
+
+        This base class has been superseded by :class:`~.ASAPScheduleAnalysis` and
+        the new scheduling workflow. It will be deprecated and subsequently
+        removed in a future release.
+    """
+
+    @deprecate_func(
+        additional_msg=(
+            "Instead, use :class:`~.ASAPScheduleAnalysis`, which is an "
+            "analysis pass that requires a padding pass to later modify the circuit."
+        ),
+        since="1.1.0",
+    )
+    def __init__(self, *args, **kwargs):
+        super().__init__(*args, **kwargs)
+
+    def run(self, dag):
+        """Run the ASAPSchedule pass on `dag`.
+
+        Args:
+            dag (DAGCircuit): DAG to schedule.
+
+        Returns:
+            DAGCircuit: A scheduled DAG.
+
+        Raises:
+            TranspilerError: if the circuit is not mapped on physical qubits.
+            TranspilerError: if conditional bit is added to non-supported instruction.
+        """
+        if len(dag.qregs) != 1 or dag.qregs.get("q", None) is None:
+            raise TranspilerError("ASAP schedule runs on physical circuits only")
+
+        time_unit = self.property_set["time_unit"]
+
+        new_dag = DAGCircuit()
+        for qreg in dag.qregs.values():
+            new_dag.add_qreg(qreg)
+        for creg in dag.cregs.values():
+            new_dag.add_creg(creg)
+
+        idle_after = {q: 0 for q in dag.qubits + dag.clbits}
+        for node in dag.topological_op_nodes():
+            op_duration = self._get_node_duration(node, dag)
+
+            # compute t0, t1: instruction interval, note that
+            # t0: start time of instruction
+            # t1: end time of instruction
+            if isinstance(node.op, self.CONDITIONAL_SUPPORTED):
+                t0q = max(idle_after[q] for q in node.qargs)
+                if node.op.condition_bits:
+                    # conditional is bit tricky due to conditional_latency
+                    t0c = max(idle_after[bit] for bit in node.op.condition_bits)
+                    if t0q > t0c:
+                        # This is situation something like below
+                        #
+                        #           |t0q
+                        # Q ▒▒▒▒▒▒▒▒▒░░
+                        # C ▒▒▒░░░░░░░░
+                        #     |t0c
+                        #
+                        # In this case, you can insert readout access before tq0
+                        #
+                        #           |t0q
+                        # Q ▒▒▒▒▒▒▒▒▒▒▒
+                        # C ▒▒▒░░░▒▒░░░
+                        #         |t0q - conditional_latency
+                        #
+                        t0c = max(t0q - self.conditional_latency, t0c)
+                    t1c = t0c + self.conditional_latency
+                    for bit in node.op.condition_bits:
+                        # Lock clbit until state is read
+                        idle_after[bit] = t1c
+                    # It starts after register read access
+                    t0 = max(t0q, t1c)
+                else:
+                    t0 = t0q
+                t1 = t0 + op_duration
+            else:
+                if node.op.condition_bits:
+                    raise TranspilerError(
+                        f"Conditional instruction {node.op.name} is not supported in ASAP scheduler."
+                    )
+
+                if isinstance(node.op, Measure):
+                    # measure instruction handling is bit tricky due to clbit_write_latency
+                    t0q = max(idle_after[q] for q in node.qargs)
+                    t0c = max(idle_after[c] for c in node.cargs)
+                    # Assume following case (t0c > t0q)
+                    #
+                    #       |t0q
+                    # Q ▒▒▒▒░░░░░░░░░░░░
+                    # C ▒▒▒▒▒▒▒▒░░░░░░░░
+                    #           |t0c
+                    #
+                    # In this case, there is no actual clbit access until clbit_write_latency.
+                    # The node t0 can be push backward by this amount.
+                    #
+                    #         |t0q' = t0c - clbit_write_latency
+                    # Q ▒▒▒▒░░▒▒▒▒▒▒▒▒▒▒
+                    # C ▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒
+                    #           |t0c' = t0c
+                    #
+                    # rather than naively doing
+                    #
+                    #           |t0q' = t0c
+                    # Q ▒▒▒▒░░░░▒▒▒▒▒▒▒▒
+                    # C ▒▒▒▒▒▒▒▒░░░▒▒▒▒▒
+                    #              |t0c' = t0c + clbit_write_latency
+                    #
+                    t0 = max(t0q, t0c - self.clbit_write_latency)
+                    t1 = t0 + op_duration
+                    for clbit in node.cargs:
+                        idle_after[clbit] = t1
+                else:
+                    # It happens to be directives such as barrier
+                    t0 = max(idle_after[bit] for bit in node.qargs + node.cargs)
+                    t1 = t0 + op_duration
+
+            # Add delay to qubit wire
+            for bit in node.qargs:
+                delta = t0 - idle_after[bit]
+                if (
+                    delta > 0
+                    and isinstance(bit, Qubit)
+                    and self._delay_supported(dag.find_bit(bit).index)
+                ):
+                    new_dag.apply_operation_back(Delay(delta, time_unit), [bit], [])
+                idle_after[bit] = t1
+
+            new_dag.apply_operation_back(node.op, node.qargs, node.cargs)
+
+        circuit_duration = max(idle_after.values())
+        for bit, after in idle_after.items():
+            delta = circuit_duration - after
+            if not (delta > 0 and isinstance(bit, Qubit)):
+                continue
+            if self._delay_supported(dag.find_bit(bit).index):
+                new_dag.apply_operation_back(Delay(delta, time_unit), [bit], [])
+
+        new_dag.name = dag.name
+        new_dag.metadata = dag.metadata
+        new_dag._calibrations_prop = dag._calibrations_prop
+
+        # set circuit duration and unit to indicate it is scheduled
+        new_dag.duration = circuit_duration
+        new_dag.unit = time_unit
+        return new_dag