qiskit 1.1.2__cp38-abi3-macosx_10_9_universal2.whl → 1.2.0rc1__cp38-abi3-macosx_10_9_universal2.whl

qiskit/dagcircuit/dagcircuit.py

@@ -54,6 +54,8 @@ from qiskit.dagcircuit.exceptions import DAGCircuitError
 from qiskit.dagcircuit.dagnode import DAGNode, DAGOpNode, DAGInNode, DAGOutNode
 from qiskit.circuit.bit import Bit
 from qiskit.pulse import Schedule
+from qiskit._accelerate.euler_one_qubit_decomposer import collect_1q_runs_filter
+from qiskit._accelerate.convert_2q_block_matrix import collect_2q_blocks_filter
 
 BitLocations = namedtuple("BitLocations", ("index", "registers"))
 # The allowable arguments to :meth:`DAGCircuit.copy_empty_like`'s ``vars_mode``.
@@ -271,7 +273,7 @@ class DAGCircuit:
 
         duplicate_qubits = set(self.qubits).intersection(qubits)
         if duplicate_qubits:
-            raise DAGCircuitError("duplicate qubits %s" % duplicate_qubits)
+            raise DAGCircuitError(f"duplicate qubits {duplicate_qubits}")
 
         for qubit in qubits:
             self.qubits.append(qubit)
@@ -285,7 +287,7 @@ class DAGCircuit:
 
         duplicate_clbits = set(self.clbits).intersection(clbits)
         if duplicate_clbits:
-            raise DAGCircuitError("duplicate clbits %s" % duplicate_clbits)
+            raise DAGCircuitError(f"duplicate clbits {duplicate_clbits}")
 
         for clbit in clbits:
             self.clbits.append(clbit)
@@ -297,7 +299,7 @@ class DAGCircuit:
         if not isinstance(qreg, QuantumRegister):
             raise DAGCircuitError("not a QuantumRegister instance.")
         if qreg.name in self.qregs:
-            raise DAGCircuitError("duplicate register %s" % qreg.name)
+            raise DAGCircuitError(f"duplicate register {qreg.name}")
         self.qregs[qreg.name] = qreg
         existing_qubits = set(self.qubits)
         for j in range(qreg.size):
@@ -315,7 +317,7 @@ class DAGCircuit:
         if not isinstance(creg, ClassicalRegister):
             raise DAGCircuitError("not a ClassicalRegister instance.")
         if creg.name in self.cregs:
-            raise DAGCircuitError("duplicate register %s" % creg.name)
+            raise DAGCircuitError(f"duplicate register {creg.name}")
         self.cregs[creg.name] = creg
         existing_clbits = set(self.clbits)
         for j in range(creg.size):
@@ -451,17 +453,17 @@ class DAGCircuit:
         """
         if any(not isinstance(clbit, Clbit) for clbit in clbits):
             raise DAGCircuitError(
-                "clbits not of type Clbit: %s" % [b for b in clbits if not isinstance(b, Clbit)]
+                f"clbits not of type Clbit: {[b for b in clbits if not isinstance(b, Clbit)]}"
             )
 
         clbits = set(clbits)
         unknown_clbits = clbits.difference(self.clbits)
         if unknown_clbits:
-            raise DAGCircuitError("clbits not in circuit: %s" % unknown_clbits)
+            raise DAGCircuitError(f"clbits not in circuit: {unknown_clbits}")
 
         busy_clbits = {bit for bit in clbits if not self._is_wire_idle(bit)}
         if busy_clbits:
-            raise DAGCircuitError("clbits not idle: %s" % busy_clbits)
+            raise DAGCircuitError(f"clbits not idle: {busy_clbits}")
 
         # remove any references to bits
         cregs_to_remove = {creg for creg in self.cregs.values() if not clbits.isdisjoint(creg)}
@@ -487,13 +489,13 @@ class DAGCircuit:
         """
         if any(not isinstance(creg, ClassicalRegister) for creg in cregs):
             raise DAGCircuitError(
-                "cregs not of type ClassicalRegister: %s"
-                % [r for r in cregs if not isinstance(r, ClassicalRegister)]
+                "cregs not of type ClassicalRegister: "
+                f"{[r for r in cregs if not isinstance(r, ClassicalRegister)]}"
             )
 
         unknown_cregs = set(cregs).difference(self.cregs.values())
         if unknown_cregs:
-            raise DAGCircuitError("cregs not in circuit: %s" % unknown_cregs)
+            raise DAGCircuitError(f"cregs not in circuit: {unknown_cregs}")
 
         for creg in cregs:
             del self.cregs[creg.name]
@@ -517,17 +519,17 @@ class DAGCircuit:
         """
         if any(not isinstance(qubit, Qubit) for qubit in qubits):
             raise DAGCircuitError(
-                "qubits not of type Qubit: %s" % [b for b in qubits if not isinstance(b, Qubit)]
+                f"qubits not of type Qubit: {[b for b in qubits if not isinstance(b, Qubit)]}"
             )
 
         qubits = set(qubits)
         unknown_qubits = qubits.difference(self.qubits)
         if unknown_qubits:
-            raise DAGCircuitError("qubits not in circuit: %s" % unknown_qubits)
+            raise DAGCircuitError(f"qubits not in circuit: {unknown_qubits}")
 
         busy_qubits = {bit for bit in qubits if not self._is_wire_idle(bit)}
         if busy_qubits:
-            raise DAGCircuitError("qubits not idle: %s" % busy_qubits)
+            raise DAGCircuitError(f"qubits not idle: {busy_qubits}")
 
         # remove any references to bits
         qregs_to_remove = {qreg for qreg in self.qregs.values() if not qubits.isdisjoint(qreg)}
@@ -553,13 +555,13 @@ class DAGCircuit:
         """
         if any(not isinstance(qreg, QuantumRegister) for qreg in qregs):
             raise DAGCircuitError(
-                "qregs not of type QuantumRegister: %s"
-                % [r for r in qregs if not isinstance(r, QuantumRegister)]
+                f"qregs not of type QuantumRegister: "
+                f"{[r for r in qregs if not isinstance(r, QuantumRegister)]}"
             )
 
         unknown_qregs = set(qregs).difference(self.qregs.values())
         if unknown_qregs:
-            raise DAGCircuitError("qregs not in circuit: %s" % unknown_qregs)
+            raise DAGCircuitError(f"qregs not in circuit: {unknown_qregs}")
 
         for qreg in qregs:
             del self.qregs[qreg.name]
@@ -581,13 +583,13 @@ class DAGCircuit:
             DAGCircuitError: the wire is not in the circuit.
         """
         if wire not in self._wires:
-            raise DAGCircuitError("wire %s not in circuit" % wire)
+            raise DAGCircuitError(f"wire {wire} not in circuit")
 
         try:
             child = next(self.successors(self.input_map[wire]))
         except StopIteration as e:
             raise DAGCircuitError(
-                "Invalid dagcircuit input node %s has no output" % self.input_map[wire]
+                f"Invalid dagcircuit input node {self.input_map[wire]} has no output"
             ) from e
         return child is self.output_map[wire]
 
@@ -642,17 +644,17 @@ class DAGCircuit:
             if wire not in amap:
                 raise DAGCircuitError(f"wire {wire} not found in {amap}")
 
-    def _increment_op(self, op):
-        if op.name in self._op_names:
-            self._op_names[op.name] += 1
+    def _increment_op(self, op_name):
+        if op_name in self._op_names:
+            self._op_names[op_name] += 1
         else:
-            self._op_names[op.name] = 1
+            self._op_names[op_name] = 1
 
-    def _decrement_op(self, op):
-        if self._op_names[op.name] == 1:
-            del self._op_names[op.name]
+    def _decrement_op(self, op_name):
+        if self._op_names[op_name] == 1:
+            del self._op_names[op_name]
         else:
-            self._op_names[op.name] -= 1
+            self._op_names[op_name] -= 1
 
     def copy_empty_like(self, *, vars_mode: _VarsMode = "alike"):
         """Return a copy of self with the same structure but empty.
@@ -717,6 +719,34 @@ class DAGCircuit:
 
         return target_dag
 
+    def _apply_op_node_back(self, node: DAGOpNode, *, check: bool = False):
+        additional = ()
+        if _may_have_additional_wires(node):
+            # This is the slow path; most of the time, this won't happen.
+            additional = set(_additional_wires(node.op)).difference(node.cargs)
+
+        if check:
+            self._check_condition(node.name, node.condition)
+            self._check_wires(node.qargs, self.output_map)
+            self._check_wires(node.cargs, self.output_map)
+            self._check_wires(additional, self.output_map)
+
+        node._node_id = self._multi_graph.add_node(node)
+        self._increment_op(node.name)
+
+        # Add new in-edges from predecessors of the output nodes to the
+        # operation node while deleting the old in-edges of the output nodes
+        # and adding new edges from the operation node to each output node
+        self._multi_graph.insert_node_on_in_edges_multiple(
+            node._node_id,
+            [
+                self.output_map[bit]._node_id
+                for bits in (node.qargs, node.cargs, additional)
+                for bit in bits
+            ],
+        )
+        return node
+
     def apply_operation_back(
         self,
         op: Operation,
@@ -743,32 +773,9 @@ class DAGCircuit:
             DAGCircuitError: if a leaf node is connected to multiple outputs
 
         """
-        qargs = tuple(qargs)
-        cargs = tuple(cargs)
-        additional = ()
-
-        if _may_have_additional_wires(op):
-            # This is the slow path; most of the time, this won't happen.
-            additional = set(_additional_wires(op)).difference(cargs)
-
-        if check:
-            self._check_condition(op.name, getattr(op, "condition", None))
-            self._check_wires(qargs, self.output_map)
-            self._check_wires(cargs, self.output_map)
-            self._check_wires(additional, self.output_map)
-
-        node = DAGOpNode(op=op, qargs=qargs, cargs=cargs, dag=self)
-        node._node_id = self._multi_graph.add_node(node)
-        self._increment_op(op)
-
-        # Add new in-edges from predecessors of the output nodes to the
-        # operation node while deleting the old in-edges of the output nodes
-        # and adding new edges from the operation node to each output node
-        self._multi_graph.insert_node_on_in_edges_multiple(
-            node._node_id,
-            [self.output_map[bit]._node_id for bits in (qargs, cargs, additional) for bit in bits],
+        return self._apply_op_node_back(
+            DAGOpNode(op=op, qargs=tuple(qargs), cargs=tuple(cargs), dag=self), check=check
         )
-        return node
 
     def apply_operation_front(
         self,
@@ -799,26 +806,30 @@ class DAGCircuit:
         cargs = tuple(cargs)
         additional = ()
 
-        if _may_have_additional_wires(op):
+        node = DAGOpNode(op=op, qargs=qargs, cargs=cargs, dag=self)
+        if _may_have_additional_wires(node):
             # This is the slow path; most of the time, this won't happen.
-            additional = set(_additional_wires(op)).difference(cargs)
+            additional = set(_additional_wires(node.op)).difference(cargs)
 
         if check:
-            self._check_condition(op.name, getattr(op, "condition", None))
-            self._check_wires(qargs, self.output_map)
-            self._check_wires(cargs, self.output_map)
+            self._check_condition(node.name, node.condition)
+            self._check_wires(node.qargs, self.output_map)
+            self._check_wires(node.cargs, self.output_map)
             self._check_wires(additional, self.output_map)
 
-        node = DAGOpNode(op=op, qargs=qargs, cargs=cargs, dag=self)
         node._node_id = self._multi_graph.add_node(node)
-        self._increment_op(op)
+        self._increment_op(node.name)
 
         # Add new out-edges to successors of the input nodes from the
         # operation node while deleting the old out-edges of the input nodes
         # and adding new edges to the operation node from each input node
         self._multi_graph.insert_node_on_out_edges_multiple(
             node._node_id,
-            [self.input_map[bit]._node_id for bits in (qargs, cargs, additional) for bit in bits],
+            [
+                self.input_map[bit]._node_id
+                for bits in (node.qargs, node.cargs, additional)
+                for bit in bits
+            ],
         )
         return node
 
@@ -950,12 +961,11 @@ class DAGCircuit:
                     # the mapped wire should already exist
                     if m_wire not in dag.output_map:
                         raise DAGCircuitError(
-                            "wire %s[%d] not in self" % (m_wire.register.name, m_wire.index)
+                            f"wire {m_wire.register.name}[{m_wire.index}] not in self"
                         )
                     if nd.wire not in other._wires:
                         raise DAGCircuitError(
-                            "inconsistent wire type for %s[%d] in other"
-                            % (nd.register.name, nd.wire.index)
+                            f"inconsistent wire type for {nd.register.name}[{nd.wire.index}] in other"
                         )
                 # If it's a Var wire, we already checked that it exists in the destination.
             elif isinstance(nd, DAGOutNode):
@@ -964,17 +974,28 @@ class DAGCircuit:
             elif isinstance(nd, DAGOpNode):
                 m_qargs = [edge_map.get(x, x) for x in nd.qargs]
                 m_cargs = [edge_map.get(x, x) for x in nd.cargs]
-                op = nd.op.copy()
-                if (condition := getattr(op, "condition", None)) is not None:
-                    if not isinstance(op, ControlFlowOp):
-                        op = op.c_if(*variable_mapper.map_condition(condition, allow_reorder=True))
+                inst = nd._to_circuit_instruction(deepcopy=True)
+                m_op = None
+                if inst.condition is not None:
+                    if inst.is_control_flow():
+                        m_op = inst.operation
+                        m_op.condition = variable_mapper.map_condition(
+                            inst.condition, allow_reorder=True
+                        )
                     else:
-                        op.condition = variable_mapper.map_condition(condition, allow_reorder=True)
-                elif isinstance(op, SwitchCaseOp):
-                    op.target = variable_mapper.map_target(op.target)
-                dag.apply_operation_back(op, m_qargs, m_cargs, check=False)
+                        m_op = inst.operation.c_if(
+                            *variable_mapper.map_condition(inst.condition, allow_reorder=True)
+                        )
+                elif inst.is_control_flow() and isinstance(inst.operation, SwitchCaseOp):
+                    m_op = inst.operation
+                    m_op.target = variable_mapper.map_target(m_op.target)
+                if m_op is None:
+                    inst = inst.replace(qubits=m_qargs, clbits=m_cargs)
+                else:
+                    inst = inst.replace(operation=m_op, qubits=m_qargs, clbits=m_cargs)
+                dag._apply_op_node_back(DAGOpNode.from_instruction(inst), check=False)
             else:
-                raise DAGCircuitError("bad node type %s" % type(nd))
+                raise DAGCircuitError(f"bad node type {type(nd)}")
 
         if not inplace:
             return dag
@@ -1327,9 +1348,9 @@ class DAGCircuit:
         for nd in node_block:
             block_qargs |= set(nd.qargs)
             block_cargs |= set(nd.cargs)
-            if (condition := getattr(nd.op, "condition", None)) is not None:
+            if (condition := getattr(nd, "condition", None)) is not None:
                 block_cargs.update(condition_resources(condition).clbits)
-            elif isinstance(nd.op, SwitchCaseOp):
+            elif nd.name in CONTROL_FLOW_OP_NAMES and isinstance(nd.op, SwitchCaseOp):
                 if isinstance(nd.op.target, Clbit):
                     block_cargs.add(nd.op.target)
                 elif isinstance(nd.op.target, ClassicalRegister):
@@ -1359,10 +1380,10 @@ class DAGCircuit:
                 "Replacing the specified node block would introduce a cycle"
             ) from ex
 
-        self._increment_op(op)
+        self._increment_op(op.name)
 
         for nd in node_block:
-            self._decrement_op(nd.op)
+            self._decrement_op(nd.name)
 
         return new_node
 
@@ -1411,7 +1432,7 @@ class DAGCircuit:
             node_wire_order = list(node.qargs) + list(node.cargs)
             # If we're not propagating it, the number of wires in the input DAG should include the
             # condition as well.
-            if not propagate_condition and _may_have_additional_wires(node.op):
+            if not propagate_condition and _may_have_additional_wires(node):
                 node_wire_order += [
                     wire for wire in _additional_wires(node.op) if wire not in node_cargs
                 ]
@@ -1433,7 +1454,7 @@ class DAGCircuit:
                 raise DAGCircuitError(
                     f"bit mapping invalid: {input_dag_wire} and {our_wire} are different bit types"
                 )
-        if _may_have_additional_wires(node.op):
+        if _may_have_additional_wires(node):
             node_vars = {var for var in _additional_wires(node.op) if isinstance(var, expr.Var)}
         else:
             node_vars = set()
@@ -1450,11 +1471,7 @@ class DAGCircuit:
         reverse_wire_map = {b: a for a, b in wire_map.items()}
         # It doesn't make sense to try and propagate a condition from a control-flow op; a
         # replacement for the control-flow op should implement the operation completely.
-        if (
-            propagate_condition
-            and not isinstance(node.op, ControlFlowOp)
-            and (op_condition := getattr(node.op, "condition", None)) is not None
-        ):
+        if propagate_condition and not node.is_control_flow() and node.condition is not None:
             in_dag = input_dag.copy_empty_like()
             # The remapping of `condition` below is still using the old code that assumes a 2-tuple.
             # This is because this remapping code only makes sense in the case of non-control-flow
@@ -1463,7 +1480,7 @@ class DAGCircuit:
             # in favour of the new-style conditional blocks.  The extra logic in here to add
             # additional wires into the map as necessary would hugely complicate matters if we tried
             # to abstract it out into the `VariableMapper` used elsewhere.
-            target, value = op_condition
+            target, value = node.condition
             if isinstance(target, Clbit):
                 new_target = reverse_wire_map.get(target, Clbit())
                 if new_target not in wire_map:
@@ -1533,7 +1550,7 @@ class DAGCircuit:
             )[0]
             self._multi_graph.add_edge(pred._node_id, succ._node_id, contracted_var)
 
-        # Exlude any nodes from in_dag that are not a DAGOpNode or are on
+        # Exclude any nodes from in_dag that are not a DAGOpNode or are on
         # wires outside the set specified by the wires kwarg
         def filter_fn(node):
             if not isinstance(node, DAGOpNode):
@@ -1573,7 +1590,7 @@ class DAGCircuit:
         node_map = self._multi_graph.substitute_node_with_subgraph(
             node._node_id, in_dag._multi_graph, edge_map_fn, filter_fn, edge_weight_map
         )
-        self._decrement_op(node.op)
+        self._decrement_op(node.name)
 
         variable_mapper = _classical_resource_map.VariableMapper(
             self.cregs.values(), wire_map, add_register=self.add_creg
@@ -1583,28 +1600,34 @@ class DAGCircuit:
         for old_node_index, new_node_index in node_map.items():
             # update node attributes
             old_node = in_dag._multi_graph[old_node_index]
-            if isinstance(old_node.op, SwitchCaseOp):
+            m_op = None
+            if not old_node.is_standard_gate() and isinstance(old_node.op, SwitchCaseOp):
                 m_op = SwitchCaseOp(
                     variable_mapper.map_target(old_node.op.target),
                     old_node.op.cases_specifier(),
                     label=old_node.op.label,
                 )
-            elif getattr(old_node.op, "condition", None) is not None:
+            elif old_node.condition is not None:
                 m_op = old_node.op
-                if not isinstance(old_node.op, ControlFlowOp):
+                if old_node.is_control_flow():
+                    m_op.condition = variable_mapper.map_condition(m_op.condition)
+                else:
                     new_condition = variable_mapper.map_condition(m_op.condition)
                     if new_condition is not None:
                         m_op = m_op.c_if(*new_condition)
-                else:
-                    m_op.condition = variable_mapper.map_condition(m_op.condition)
-            else:
-                m_op = old_node.op
             m_qargs = [wire_map[x] for x in old_node.qargs]
             m_cargs = [wire_map[x] for x in old_node.cargs]
-            new_node = DAGOpNode(m_op, qargs=m_qargs, cargs=m_cargs, dag=self)
+            old_instruction = old_node._to_circuit_instruction()
+            if m_op is None:
+                new_instruction = old_instruction.replace(qubits=m_qargs, clbits=m_cargs)
+            else:
+                new_instruction = old_instruction.replace(
+                    operation=m_op, qubits=m_qargs, clbits=m_cargs
+                )
+            new_node = DAGOpNode.from_instruction(new_instruction)
             new_node._node_id = new_node_index
             self._multi_graph[new_node_index] = new_node
-            self._increment_op(new_node.op)
+            self._increment_op(new_node.name)
 
         return {k: self._multi_graph[v] for k, v in node_map.items()}
 
@@ -1623,7 +1646,7 @@ class DAGCircuit:
                 be used.
             propagate_condition (bool): Optional, default True.  If True, a condition on the
                 ``node`` to be replaced will be applied to the new ``op``.  This is the legacy
-                behaviour.  If either node is a control-flow operation, this will be ignored.  If
+                behavior.  If either node is a control-flow operation, this will be ignored.  If
                 the ``op`` already has a condition, :exc:`.DAGCircuitError` is raised.
 
         Returns:
@@ -1639,10 +1662,10 @@ class DAGCircuit:
 
         if node.op.num_qubits != op.num_qubits or node.op.num_clbits != op.num_clbits:
             raise DAGCircuitError(
-                "Cannot replace node of width ({} qubits, {} clbits) with "
-                "operation of mismatched width ({} qubits, {} clbits).".format(
-                    node.op.num_qubits, node.op.num_clbits, op.num_qubits, op.num_clbits
-                )
+                f"Cannot replace node of width ({node.op.num_qubits} qubits, "
+                f"{node.op.num_clbits} clbits) with "
+                f"operation of mismatched width ({op.num_qubits} qubits, "
+                f"{op.num_clbits} clbits)."
             )
 
         # This might include wires that are inherent to the node, like in its `condition` or
@@ -1676,17 +1699,17 @@ class DAGCircuit:
 
         if inplace:
             if op.name != node.op.name:
-                self._increment_op(op)
-                self._decrement_op(node.op)
+                self._increment_op(op.name)
+                self._decrement_op(node.name)
             node.op = op
             return node
 
         new_node = copy.copy(node)
         new_node.op = op
         self._multi_graph[node._node_id] = new_node
-        if op.name != node.op.name:
-            self._increment_op(op)
-            self._decrement_op(node.op)
+        if op.name != node.name:
+            self._increment_op(op.name)
+            self._decrement_op(node.name)
         return new_node
 
     def separable_circuits(
@@ -1830,11 +1853,18 @@ class DAGCircuit:
             list[DAGOpNode]: the list of node ids containing the given op.
         """
         nodes = []
+        filter_is_nonstandard = getattr(op, "_standard_gate", None) is None
         for node in self._multi_graph.nodes():
             if isinstance(node, DAGOpNode):
-                if not include_directives and getattr(node.op, "_directive", False):
+                if not include_directives and node.is_directive():
                     continue
-                if op is None or isinstance(node.op, op):
+                if op is None or (
+                    # This middle catch is to avoid Python-space operation creation for most uses of
+                    # `op`; we're usually just looking for control-flow ops, and standard gates
+                    # aren't control-flow ops.
+                    not (filter_is_nonstandard and node.is_standard_gate())
+                    and isinstance(node.op, op)
+                ):
                     nodes.append(node)
         return nodes
 
@@ -1854,7 +1884,7 @@ class DAGCircuit:
         """Get the set of "op" nodes with the given name."""
         named_nodes = []
         for node in self._multi_graph.nodes():
-            if isinstance(node, DAGOpNode) and node.op.name in names:
+            if isinstance(node, DAGOpNode) and node.name in names:
                 named_nodes.append(node)
         return named_nodes
 
@@ -1960,14 +1990,12 @@ class DAGCircuit:
         """
         if not isinstance(node, DAGOpNode):
             raise DAGCircuitError(
-                'The method remove_op_node only works on DAGOpNodes. A "%s" '
-                "node type was wrongly provided." % type(node)
+                f'The method remove_op_node only works on DAGOpNodes. A "{type(node)}" '
+                "node type was wrongly provided."
             )
 
-        self._multi_graph.remove_node_retain_edges(
-            node._node_id, use_outgoing=False, condition=lambda edge1, edge2: edge1 == edge2
-        )
-        self._decrement_op(node.op)
+        self._multi_graph.remove_node_retain_edges_by_id(node._node_id)
+        self._decrement_op(node.name)
 
     def remove_ancestors_of(self, node):
         """Remove all of the ancestor operation nodes of node."""
@@ -2062,14 +2090,11 @@ class DAGCircuit:
             new_layer = self.copy_empty_like(vars_mode=vars_mode)
 
             for node in op_nodes:
-                # this creates new DAGOpNodes in the new_layer
-                new_layer.apply_operation_back(node.op, node.qargs, node.cargs, check=False)
+                new_layer._apply_op_node_back(node, check=False)
 
             # The quantum registers that have an operation in this layer.
             support_list = [
-                op_node.qargs
-                for op_node in new_layer.op_nodes()
-                if not getattr(op_node.op, "_directive", False)
+                op_node.qargs for op_node in new_layer.op_nodes() if not op_node.is_directive()
             ]
 
             yield {"graph": new_layer, "partition": support_list}
@@ -2121,56 +2146,25 @@ class DAGCircuit:
         """
 
         def filter_fn(node):
-            return (
-                isinstance(node, DAGOpNode)
-                and node.op.name in namelist
-                and getattr(node.op, "condition", None) is None
-            )
+            return isinstance(node, DAGOpNode) and node.name in namelist and node.condition is None
 
         group_list = rx.collect_runs(self._multi_graph, filter_fn)
         return {tuple(x) for x in group_list}
 
     def collect_1q_runs(self) -> list[list[DAGOpNode]]:
         """Return a set of non-conditional runs of 1q "op" nodes."""
-
-        def filter_fn(node):
-            return (
-                isinstance(node, DAGOpNode)
-                and len(node.qargs) == 1
-                and len(node.cargs) == 0
-                and isinstance(node.op, Gate)
-                and hasattr(node.op, "__array__")
-                and getattr(node.op, "condition", None) is None
-                and not node.op.is_parameterized()
-            )
-
-        return rx.collect_runs(self._multi_graph, filter_fn)
+        return rx.collect_runs(self._multi_graph, collect_1q_runs_filter)
 
     def collect_2q_runs(self):
         """Return a set of non-conditional runs of 2q "op" nodes."""
 
-        to_qid = {}
-        for i, qubit in enumerate(self.qubits):
-            to_qid[qubit] = i
-
-        def filter_fn(node):
-            if isinstance(node, DAGOpNode):
-                return (
-                    isinstance(node.op, Gate)
-                    and len(node.qargs) <= 2
-                    and not getattr(node.op, "condition", None)
-                    and not node.op.is_parameterized()
-                )
-            else:
-                return None
-
         def color_fn(edge):
             if isinstance(edge, Qubit):
-                return to_qid[edge]
+                return self.find_bit(edge).index
             else:
                 return None
 
-        return rx.collect_bicolor_runs(self._multi_graph, filter_fn, color_fn)
+        return rx.collect_bicolor_runs(self._multi_graph, collect_2q_blocks_filter, color_fn)
 
     def nodes_on_wire(self, wire, only_ops=False):
         """
@@ -2189,7 +2183,7 @@ class DAGCircuit:
         current_node = self.input_map.get(wire, None)
 
         if not current_node:
-            raise DAGCircuitError("The given wire %s is not present in the circuit" % str(wire))
+            raise DAGCircuitError(f"The given wire {str(wire)} is not present in the circuit")
 
         more_nodes = True
         while more_nodes:
@@ -2272,36 +2266,44 @@ class DAGCircuit:
         output_node = self.output_map.get(qubit, None)
         if not output_node:
             raise DAGCircuitError(f"Qubit {qubit} is not part of this circuit.")
-        # Add the qubit to the causal cone.
-        qubits_to_check = {qubit}
-        # Add predecessors of output node to the queue.
-        queue = deque(self.predecessors(output_node))
 
-        # While queue isn't empty
+        qubits_in_cone = {qubit}
+        queue = deque(self.quantum_predecessors(output_node))
+
+        # The processed_non_directive_nodes stores the set of processed non-directive nodes.
+        # This is an optimization to avoid considering the same non-directive node multiple
+        # times when reached from different paths.
+        # The directive nodes (such as barriers or measures) are trickier since when processing
+        # them we only add their predecessors that intersect qubits_in_cone. Hence, directive
+        # nodes have to be considered multiple times.
+        processed_non_directive_nodes = set()
+
         while queue:
-            # Pop first element.
             node_to_check = queue.popleft()
-            # Check whether element is input or output node.
+
             if isinstance(node_to_check, DAGOpNode):
-                # Keep all the qubits in the operation inside a set.
-                qubit_set = set(node_to_check.qargs)
-                # Check if there are any qubits in common and that the operation is not a barrier.
-                if (
-                    len(qubit_set.intersection(qubits_to_check)) > 0
-                    and node_to_check.op.name != "barrier"
-                    and not getattr(node_to_check.op, "_directive")
-                ):
-                    # If so, add all the qubits to the causal cone.
-                    qubits_to_check = qubits_to_check.union(qubit_set)
-            # For each predecessor of the current node, filter input/output nodes,
-            # also make sure it has at least one qubit in common. Then append.
-            for node in self.quantum_predecessors(node_to_check):
-                if (
-                    isinstance(node, DAGOpNode)
-                    and len(qubits_to_check.intersection(set(node.qargs))) > 0
-                ):
-                    queue.append(node)
-        return qubits_to_check
+                # If the operation is not a directive (in particular not a barrier nor a measure),
+                # we do not do anything if it was already processed. Otherwise, we add its qubits
+                # to qubits_in_cone, and append its predecessors to queue.
+                if not getattr(node_to_check.op, "_directive"):
+                    if node_to_check in processed_non_directive_nodes:
+                        continue
+                    qubits_in_cone = qubits_in_cone.union(set(node_to_check.qargs))
+                    processed_non_directive_nodes.add(node_to_check)
+                    for pred in self.quantum_predecessors(node_to_check):
+                        if isinstance(pred, DAGOpNode):
+                            queue.append(pred)
+                else:
+                    # Directives (such as barriers and measures) may be defined over all the qubits,
+                    # yet not all of these qubits should be considered in the causal cone. So we
+                    # only add those predecessors that have qubits in common with qubits_in_cone.
+                    for pred in self.quantum_predecessors(node_to_check):
+                        if isinstance(pred, DAGOpNode) and not qubits_in_cone.isdisjoint(
+                            set(pred.qargs)
+                        ):
+                            queue.append(pred)
+
+        return qubits_in_cone
 
     def properties(self):
         """Return a dictionary of circuit properties."""
@@ -2359,24 +2361,25 @@ class _DAGVarInfo:
         self.out_node = out_node
 
 
-def _may_have_additional_wires(operation) -> bool:
-    """Return whether a given :class:`.Operation` may contain references to additional wires
-    locations within itself.  If this is ``False``, it doesn't necessarily mean that the operation
-    _will_ access memory inherently, but a ``True`` return guarantees that it won't.
+def _may_have_additional_wires(node) -> bool:
+    """Return whether a given :class:`.DAGOpNode` may contain references to additional wires
+    locations within its :class:`.Operation`.  If this is ``True``, it doesn't necessarily mean
+    that the operation _will_ access memory inherently, but a ``False`` return guarantees that it
+    won't.
 
     The memory might be classical bits or classical variables, such as a control-flow operation or a
     store.
 
     Args:
-        operation (qiskit.circuit.Operation): the operation to check.
+        operation (qiskit.dagcircuit.DAGOpNode): the operation to check.
     """
     # This is separate to `_additional_wires` because most of the time there won't be any extra
     # wires beyond the explicit `qargs` and `cargs` so we want a fast path to be able to skip
     # creating and testing a generator for emptiness.
     #
     # If updating this, you most likely also need to update `_additional_wires`.
-    return getattr(operation, "condition", None) is not None or isinstance(
-        operation, (ControlFlowOp, Store)
+    return node.condition is not None or (
+        not node.is_standard_gate() and isinstance(node.op, (ControlFlowOp, Store))
     )