pyxcp 0.25.2__cp314-cp314-win_arm64.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- pyxcp/__init__.py +20 -0
- pyxcp/aml/EtasCANMonitoring.a2l +82 -0
- pyxcp/aml/EtasCANMonitoring.aml +67 -0
- pyxcp/aml/XCP_Common.aml +408 -0
- pyxcp/aml/XCPonCAN.aml +78 -0
- pyxcp/aml/XCPonEth.aml +33 -0
- pyxcp/aml/XCPonFlx.aml +113 -0
- pyxcp/aml/XCPonSxI.aml +66 -0
- pyxcp/aml/XCPonUSB.aml +106 -0
- pyxcp/aml/ifdata_CAN.a2l +20 -0
- pyxcp/aml/ifdata_Eth.a2l +11 -0
- pyxcp/aml/ifdata_Flx.a2l +94 -0
- pyxcp/aml/ifdata_SxI.a2l +13 -0
- pyxcp/aml/ifdata_USB.a2l +81 -0
- pyxcp/asam/__init__.py +0 -0
- pyxcp/asam/types.py +131 -0
- pyxcp/asamkeydll.c +116 -0
- pyxcp/asamkeydll.exe +0 -0
- pyxcp/asamkeydll.sh +2 -0
- pyxcp/checksum.py +732 -0
- pyxcp/cmdline.py +83 -0
- pyxcp/config/__init__.py +1257 -0
- pyxcp/config/legacy.py +120 -0
- pyxcp/constants.py +47 -0
- pyxcp/cpp_ext/__init__.py +0 -0
- pyxcp/cpp_ext/aligned_buffer.hpp +168 -0
- pyxcp/cpp_ext/bin.hpp +105 -0
- pyxcp/cpp_ext/blockmem.hpp +58 -0
- pyxcp/cpp_ext/cpp_ext.cp310-win_arm64.pyd +0 -0
- pyxcp/cpp_ext/cpp_ext.cp311-win_arm64.pyd +0 -0
- pyxcp/cpp_ext/cpp_ext.cp312-win_arm64.pyd +0 -0
- pyxcp/cpp_ext/cpp_ext.cp313-win_arm64.pyd +0 -0
- pyxcp/cpp_ext/cpp_ext.cp314-win_arm64.pyd +0 -0
- pyxcp/cpp_ext/daqlist.hpp +374 -0
- pyxcp/cpp_ext/event.hpp +67 -0
- pyxcp/cpp_ext/extension_wrapper.cpp +131 -0
- pyxcp/cpp_ext/framing.hpp +360 -0
- pyxcp/cpp_ext/helper.hpp +280 -0
- pyxcp/cpp_ext/mcobject.hpp +248 -0
- pyxcp/cpp_ext/sxi_framing.hpp +332 -0
- pyxcp/cpp_ext/tsqueue.hpp +46 -0
- pyxcp/daq_stim/__init__.py +306 -0
- pyxcp/daq_stim/optimize/__init__.py +67 -0
- pyxcp/daq_stim/optimize/binpacking.py +41 -0
- pyxcp/daq_stim/scheduler.cpp +62 -0
- pyxcp/daq_stim/scheduler.hpp +75 -0
- pyxcp/daq_stim/stim.cp310-win_arm64.pyd +0 -0
- pyxcp/daq_stim/stim.cp311-win_arm64.pyd +0 -0
- pyxcp/daq_stim/stim.cp312-win_arm64.pyd +0 -0
- pyxcp/daq_stim/stim.cp313-win_arm64.pyd +0 -0
- pyxcp/daq_stim/stim.cp314-win_arm64.pyd +0 -0
- pyxcp/daq_stim/stim.cpp +13 -0
- pyxcp/daq_stim/stim.hpp +604 -0
- pyxcp/daq_stim/stim_wrapper.cpp +50 -0
- pyxcp/dllif.py +100 -0
- pyxcp/errormatrix.py +878 -0
- pyxcp/examples/conf_can.toml +19 -0
- pyxcp/examples/conf_can_user.toml +16 -0
- pyxcp/examples/conf_can_vector.json +11 -0
- pyxcp/examples/conf_can_vector.toml +11 -0
- pyxcp/examples/conf_eth.toml +9 -0
- pyxcp/examples/conf_nixnet.json +20 -0
- pyxcp/examples/conf_socket_can.toml +12 -0
- pyxcp/examples/run_daq.py +165 -0
- pyxcp/examples/xcp_policy.py +60 -0
- pyxcp/examples/xcp_read_benchmark.py +38 -0
- pyxcp/examples/xcp_skel.py +48 -0
- pyxcp/examples/xcp_unlock.py +38 -0
- pyxcp/examples/xcp_user_supplied_driver.py +43 -0
- pyxcp/examples/xcphello.py +79 -0
- pyxcp/examples/xcphello_recorder.py +107 -0
- pyxcp/master/__init__.py +10 -0
- pyxcp/master/errorhandler.py +677 -0
- pyxcp/master/master.py +2645 -0
- pyxcp/py.typed +0 -0
- pyxcp/recorder/.idea/.gitignore +8 -0
- pyxcp/recorder/.idea/misc.xml +4 -0
- pyxcp/recorder/.idea/modules.xml +8 -0
- pyxcp/recorder/.idea/recorder.iml +6 -0
- pyxcp/recorder/.idea/sonarlint/issuestore/3/8/3808afc69ac1edb9d760000a2f137335b1b99728 +7 -0
- pyxcp/recorder/.idea/sonarlint/issuestore/9/a/9a2aa4db38d3115ed60da621e012c0efc0172aae +0 -0
- pyxcp/recorder/.idea/sonarlint/issuestore/b/4/b49006702b459496a8e8c94ebe60947108361b91 +0 -0
- pyxcp/recorder/.idea/sonarlint/issuestore/index.pb +7 -0
- pyxcp/recorder/.idea/sonarlint/securityhotspotstore/3/8/3808afc69ac1edb9d760000a2f137335b1b99728 +0 -0
- pyxcp/recorder/.idea/sonarlint/securityhotspotstore/9/a/9a2aa4db38d3115ed60da621e012c0efc0172aae +0 -0
- pyxcp/recorder/.idea/sonarlint/securityhotspotstore/b/4/b49006702b459496a8e8c94ebe60947108361b91 +0 -0
- pyxcp/recorder/.idea/sonarlint/securityhotspotstore/index.pb +7 -0
- pyxcp/recorder/.idea/vcs.xml +10 -0
- pyxcp/recorder/__init__.py +96 -0
- pyxcp/recorder/build_clang.cmd +1 -0
- pyxcp/recorder/build_clang.sh +2 -0
- pyxcp/recorder/build_gcc.cmd +1 -0
- pyxcp/recorder/build_gcc.sh +2 -0
- pyxcp/recorder/build_gcc_arm.sh +2 -0
- pyxcp/recorder/converter/__init__.py +445 -0
- pyxcp/recorder/lz4.c +2829 -0
- pyxcp/recorder/lz4.h +879 -0
- pyxcp/recorder/lz4hc.c +2041 -0
- pyxcp/recorder/lz4hc.h +413 -0
- pyxcp/recorder/mio.hpp +1714 -0
- pyxcp/recorder/reader.hpp +138 -0
- pyxcp/recorder/reco.py +278 -0
- pyxcp/recorder/recorder.rst +0 -0
- pyxcp/recorder/rekorder.cp310-win_arm64.pyd +0 -0
- pyxcp/recorder/rekorder.cp311-win_arm64.pyd +0 -0
- pyxcp/recorder/rekorder.cp312-win_arm64.pyd +0 -0
- pyxcp/recorder/rekorder.cp313-win_arm64.pyd +0 -0
- pyxcp/recorder/rekorder.cp314-win_arm64.pyd +0 -0
- pyxcp/recorder/rekorder.cpp +59 -0
- pyxcp/recorder/rekorder.hpp +274 -0
- pyxcp/recorder/setup.py +41 -0
- pyxcp/recorder/test_reko.py +34 -0
- pyxcp/recorder/unfolder.hpp +1354 -0
- pyxcp/recorder/wrap.cpp +184 -0
- pyxcp/recorder/writer.hpp +302 -0
- pyxcp/scripts/__init__.py +0 -0
- pyxcp/scripts/pyxcp_probe_can_drivers.py +20 -0
- pyxcp/scripts/xcp_examples.py +64 -0
- pyxcp/scripts/xcp_fetch_a2l.py +40 -0
- pyxcp/scripts/xcp_id_scanner.py +18 -0
- pyxcp/scripts/xcp_info.py +144 -0
- pyxcp/scripts/xcp_profile.py +26 -0
- pyxcp/scripts/xmraw_converter.py +31 -0
- pyxcp/stim/__init__.py +0 -0
- pyxcp/tests/test_asam_types.py +24 -0
- pyxcp/tests/test_binpacking.py +186 -0
- pyxcp/tests/test_can.py +1324 -0
- pyxcp/tests/test_checksum.py +95 -0
- pyxcp/tests/test_daq.py +193 -0
- pyxcp/tests/test_daq_opt.py +426 -0
- pyxcp/tests/test_frame_padding.py +156 -0
- pyxcp/tests/test_framing.py +262 -0
- pyxcp/tests/test_master.py +2116 -0
- pyxcp/tests/test_transport.py +177 -0
- pyxcp/tests/test_utils.py +30 -0
- pyxcp/timing.py +60 -0
- pyxcp/transport/__init__.py +13 -0
- pyxcp/transport/base.py +484 -0
- pyxcp/transport/base_transport.hpp +0 -0
- pyxcp/transport/can.py +660 -0
- pyxcp/transport/eth.py +254 -0
- pyxcp/transport/sxi.py +209 -0
- pyxcp/transport/transport_ext.hpp +214 -0
- pyxcp/transport/transport_wrapper.cpp +249 -0
- pyxcp/transport/usb_transport.py +229 -0
- pyxcp/types.py +987 -0
- pyxcp/utils.py +127 -0
- pyxcp/vector/__init__.py +0 -0
- pyxcp/vector/map.py +82 -0
- pyxcp-0.25.2.dist-info/METADATA +341 -0
- pyxcp-0.25.2.dist-info/RECORD +154 -0
- pyxcp-0.25.2.dist-info/WHEEL +4 -0
- pyxcp-0.25.2.dist-info/entry_points.txt +9 -0
- pyxcp-0.25.2.dist-info/licenses/LICENSE +165 -0
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import pytest
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from pyxcp import checksum
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"""
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XCP_ADD_11 0x10 0x10
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XCP_ADD_12 0x0F10 0x0F10
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XCP_ADD_14 0x00000F10 0x00000F10
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XCP_ADD_22 0x1800 0x0710
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XCP_ADD_24 0x00071800 0x00080710
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XCP_ADD_44 0x140C03F8 0xFC040B10
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XCP_CRC_16 0xC76A 0xC76A
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XCP_CRC_16_CITT 0x9D50 0x9D50
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XCP_CRC_32 0x89CD97CE 0x89CD97CE
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"""
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TEST = bytes(
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)
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)
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def testAdd11():
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assert checksum.check(TEST, "XCP_ADD_11") == 0x10
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def testAdd12():
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def testCrc16():
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def testCrc16Ccitt():
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def testCrc32():
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def testUserDefined():
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pyxcp/tests/test_daq.py
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#!/usr/bin/env python
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from pyxcp.daq_stim import DaqList
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"channels": [
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{
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"maxDaqList": 1,
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"name": "Key T",
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"priority": 0,
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"properties": {"consistency": "CONSISTENCY_ODT", "daq": True, "packed": False, "stim": False},
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"unit": "EVENT_CHANNEL_TIME_UNIT_1MS",
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},
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{
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"cycle": 10,
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"maxDaqList": 1,
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"name": "10 ms",
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"priority": 1,
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"properties": {"consistency": "CONSISTENCY_ODT", "daq": True, "packed": False, "stim": True},
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"unit": "EVENT_CHANNEL_TIME_UNIT_1MS",
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},
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{
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"cycle": 100,
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"name": "100ms",
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"properties": {"consistency": "CONSISTENCY_ODT", "daq": True, "packed": False, "stim": True},
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"unit": "EVENT_CHANNEL_TIME_UNIT_1MS",
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"cycle": 1,
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"name": "1ms",
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"priority": 3,
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"properties": {"consistency": "CONSISTENCY_ODT", "daq": True, "packed": False, "stim": True},
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"unit": "EVENT_CHANNEL_TIME_UNIT_1MS",
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},
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{
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"cycle": 10,
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"maxDaqList": 1,
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"name": "FilterBypassDaq",
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"priority": 4,
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"properties": {"consistency": "CONSISTENCY_ODT", "daq": True, "packed": False, "stim": True},
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"unit": "EVENT_CHANNEL_TIME_UNIT_1MS",
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},
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{
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"cycle": 10,
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"maxDaqList": 1,
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"name": "FilterBypassStim",
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"priority": 5,
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"properties": {"consistency": "CONSISTENCY_ODT", "daq": False, "packed": False, "stim": True},
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"unit": "EVENT_CHANNEL_TIME_UNIT_1MS",
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},
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],
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"processor": {
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"keyByte": {
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"addressExtension": "AE_DIFFERENT_WITHIN_ODT",
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"identificationField": "IDF_REL_ODT_NUMBER_ABS_DAQ_LIST_NUMBER_BYTE",
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"optimisationType": "OM_DEFAULT",
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},
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"maxDaq": 0,
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"minDaq": 0,
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"properties": {
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"bitStimSupported": False,
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"configType": "DYNAMIC",
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"overloadEvent": False,
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"overloadMsb": True,
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"pidOffSupported": False,
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"prescalerSupported": True,
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"resumeSupported": True,
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"timestampSupported": True,
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},
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},
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"resolution": {
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"granularityOdtEntrySizeDaq": 1,
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"granularityOdtEntrySizeStim": 1,
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"maxOdtEntrySizeDaq": 218,
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"maxOdtEntrySizeStim": 218,
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"timestampMode": {"fixed": False, "size": "S4", "unit": "DAQ_TIMESTAMP_UNIT_10US"},
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"timestampTicks": 10,
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},
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}
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SLAVE_INFO = {
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"addressGranularity": 0,
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"byteOrder": 0,
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"interleavedMode": False,
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"masterBlockMode": True,
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"maxBs": 2,
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"maxCto": 255,
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"maxDto": 1500,
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"maxWriteDaqMultipleElements": 31,
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"minSt": 0,
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"optionalCommMode": True,
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"pgmProcessor": {},
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"protocolLayerVersion": 1,
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"queueSize": 0,
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"slaveBlockMode": True,
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"supportsCalpag": True,
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"supportsDaq": True,
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"supportsPgm": True,
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+
"supportsStim": True,
|
|
105
|
+
"transportLayerVersion": 1,
|
|
106
|
+
"xcpDriverVersionNumber": 25,
|
|
107
|
+
}
|
|
108
|
+
|
|
109
|
+
|
|
110
|
+
class AttrDict(dict):
|
|
111
|
+
def __getattr__(self, name):
|
|
112
|
+
return self[name]
|
|
113
|
+
|
|
114
|
+
|
|
115
|
+
class MockMaster:
|
|
116
|
+
def __init__(self):
|
|
117
|
+
self.slaveProperties = AttrDict(
|
|
118
|
+
{
|
|
119
|
+
"maxDto": 1500,
|
|
120
|
+
"supportsDaq": True,
|
|
121
|
+
}
|
|
122
|
+
)
|
|
123
|
+
|
|
124
|
+
def getDaqInfo(self):
|
|
125
|
+
return DAQ_INFO
|
|
126
|
+
|
|
127
|
+
def freeDaq(self):
|
|
128
|
+
pass
|
|
129
|
+
|
|
130
|
+
def allocDaq(self, daq_count):
|
|
131
|
+
self.daq_count = daq_count
|
|
132
|
+
|
|
133
|
+
def allocOdt(self, daq_num, odt_count):
|
|
134
|
+
pass
|
|
135
|
+
|
|
136
|
+
def allocOdtEntry(self, daq_num, odt_num, entry_count):
|
|
137
|
+
pass
|
|
138
|
+
|
|
139
|
+
def setDaqPtr(self, daqListNumber, odtNumber, odtEntryNumber):
|
|
140
|
+
pass
|
|
141
|
+
|
|
142
|
+
def writeDaq(self, bitOffset, entrySize, addressExt, address):
|
|
143
|
+
pass
|
|
144
|
+
|
|
145
|
+
def setDaqListMode(self, mode, daqListNumber, eventChannelNumber, prescaler, priority):
|
|
146
|
+
pass
|
|
147
|
+
|
|
148
|
+
def startStopDaqList(self, mode, daqListNumber):
|
|
149
|
+
pass
|
|
150
|
+
|
|
151
|
+
def startStopSynch(self, mode):
|
|
152
|
+
pass
|
|
153
|
+
|
|
154
|
+
|
|
155
|
+
DAQ_LISTS = [
|
|
156
|
+
DaqList(
|
|
157
|
+
"list1",
|
|
158
|
+
1,
|
|
159
|
+
False,
|
|
160
|
+
True,
|
|
161
|
+
[
|
|
162
|
+
("channel1", 0x1BD004, 0, "U32"),
|
|
163
|
+
("channel2", 0x1BD008, 0, "U32"),
|
|
164
|
+
("PWMFiltered", 0x1BDDE2, 0, "U8"),
|
|
165
|
+
("PWM", 0x1BDDDF, 0, "U8"),
|
|
166
|
+
("Triangle", 0x1BDDDE, 0, "U8"),
|
|
167
|
+
],
|
|
168
|
+
),
|
|
169
|
+
DaqList(
|
|
170
|
+
"list2",
|
|
171
|
+
3,
|
|
172
|
+
False,
|
|
173
|
+
True,
|
|
174
|
+
[
|
|
175
|
+
("TestWord_002", 0x1BE124, 0, "U16"),
|
|
176
|
+
("TestWord_003", 0x1BE128, 0, "U16"),
|
|
177
|
+
("TestWord_001", 0x1BE120, 0, "U16"),
|
|
178
|
+
("TestWord_003", 0x1BE128, 0, "U16"),
|
|
179
|
+
("TestWord_004", 0x1BE12C, 0, "U16"),
|
|
180
|
+
("TestWord_005", 0x1BE134, 0, "U16"),
|
|
181
|
+
("TestWord_006", 0x1BE134, 0, "U16"),
|
|
182
|
+
("TestWord_007", 0x1BE138, 0, "U16"),
|
|
183
|
+
("TestWord_008", 0x1BE13C, 0, "U16"),
|
|
184
|
+
("TestWord_009", 0x1BE140, 0, "U16"),
|
|
185
|
+
("TestWord_011", 0x1BE148, 0, "U16"),
|
|
186
|
+
],
|
|
187
|
+
),
|
|
188
|
+
]
|
|
189
|
+
|
|
190
|
+
# daq = DaqProcessor(DAQ_LISTS)
|
|
191
|
+
# daq.set_master(MockMaster())
|
|
192
|
+
# daq.setup()
|
|
193
|
+
# daq.start()
|
|
@@ -0,0 +1,426 @@
|
|
|
1
|
+
#!/usr/bin/env python
|
|
2
|
+
|
|
3
|
+
import pytest
|
|
4
|
+
|
|
5
|
+
from pyxcp.cpp_ext.cpp_ext import Bin, DaqList, McObject # # noqa: F401
|
|
6
|
+
from pyxcp.daq_stim.optimize import make_continuous_blocks
|
|
7
|
+
from pyxcp.daq_stim.optimize.binpacking import first_fit_decreasing
|
|
8
|
+
|
|
9
|
+
|
|
10
|
+
DAQ_LISTS_1 = [
|
|
11
|
+
DaqList(
|
|
12
|
+
"test",
|
|
13
|
+
0,
|
|
14
|
+
False,
|
|
15
|
+
False,
|
|
16
|
+
[
|
|
17
|
+
("voltage1", 0x0080051A - 4, 0, "F32"), # 80053a
|
|
18
|
+
("voltage2", 0x0080051E - 4, 0, "F32"),
|
|
19
|
+
("voltage3", 0x00800522 - 4, 0, "F32"),
|
|
20
|
+
("voltage4", 0x00800526 - 4, 0, "F32"),
|
|
21
|
+
("sine_wave", 0x00800512, 0, "F32"),
|
|
22
|
+
],
|
|
23
|
+
),
|
|
24
|
+
]
|
|
25
|
+
|
|
26
|
+
DAQ_LISTS_2 = [
|
|
27
|
+
DaqList(
|
|
28
|
+
"test",
|
|
29
|
+
0,
|
|
30
|
+
False,
|
|
31
|
+
False,
|
|
32
|
+
[
|
|
33
|
+
("voltage1", 0x0080051A, 0, "F32"), # 80053a
|
|
34
|
+
("voltage2", 0x0080051E, 0, "F32"),
|
|
35
|
+
("voltage3", 0x00800522, 0, "F32"),
|
|
36
|
+
("voltage4", 0x00800526, 0, "F32"),
|
|
37
|
+
("sq0", 0x00800516, 0, "U8"),
|
|
38
|
+
("sq1", 0x00800517, 0, "U8"),
|
|
39
|
+
("sine_wave", 0x00800512, 0, "F32"),
|
|
40
|
+
],
|
|
41
|
+
),
|
|
42
|
+
]
|
|
43
|
+
|
|
44
|
+
max_payload_size = 64
|
|
45
|
+
max_payload_size_first = 64
|
|
46
|
+
|
|
47
|
+
EXPECTED_BLOCK_VAR_1_64 = [
|
|
48
|
+
McObject(
|
|
49
|
+
name="",
|
|
50
|
+
address=8389906,
|
|
51
|
+
ext=0,
|
|
52
|
+
data_type="",
|
|
53
|
+
length=20,
|
|
54
|
+
components=[
|
|
55
|
+
McObject(name="sine_wave", address=8389906, ext=0, data_type="F32", length=4, components=[]),
|
|
56
|
+
McObject(name="voltage1", address=8389910, ext=0, data_type="F32", length=4, components=[]),
|
|
57
|
+
McObject(name="voltage2", address=8389914, ext=0, data_type="F32", length=4, components=[]),
|
|
58
|
+
McObject(name="voltage3", address=8389918, ext=0, data_type="F32", length=4, components=[]),
|
|
59
|
+
McObject(name="voltage4", address=8389922, ext=0, data_type="F32", length=4, components=[]),
|
|
60
|
+
],
|
|
61
|
+
)
|
|
62
|
+
]
|
|
63
|
+
|
|
64
|
+
EXPECTED_BLOCK_VAR_1_8 = [
|
|
65
|
+
McObject(
|
|
66
|
+
name="",
|
|
67
|
+
address=8389906,
|
|
68
|
+
ext=0,
|
|
69
|
+
data_type="",
|
|
70
|
+
length=4,
|
|
71
|
+
components=[McObject(name="sine_wave", address=8389906, ext=0, data_type="F32", length=4, components=[])],
|
|
72
|
+
),
|
|
73
|
+
McObject(
|
|
74
|
+
name="",
|
|
75
|
+
address=8389910,
|
|
76
|
+
ext=0,
|
|
77
|
+
data_type="",
|
|
78
|
+
length=4,
|
|
79
|
+
components=[McObject(name="voltage1", address=8389910, ext=0, data_type="F32", length=4, components=[])],
|
|
80
|
+
),
|
|
81
|
+
McObject(
|
|
82
|
+
name="",
|
|
83
|
+
address=8389914,
|
|
84
|
+
ext=0,
|
|
85
|
+
data_type="",
|
|
86
|
+
length=4,
|
|
87
|
+
components=[McObject(name="voltage2", address=8389914, ext=0, data_type="F32", length=4, components=[])],
|
|
88
|
+
),
|
|
89
|
+
McObject(
|
|
90
|
+
name="",
|
|
91
|
+
address=8389918,
|
|
92
|
+
ext=0,
|
|
93
|
+
data_type="",
|
|
94
|
+
length=4,
|
|
95
|
+
components=[McObject(name="voltage3", address=8389918, ext=0, data_type="F32", length=4, components=[])],
|
|
96
|
+
),
|
|
97
|
+
McObject(
|
|
98
|
+
name="",
|
|
99
|
+
address=8389922,
|
|
100
|
+
ext=0,
|
|
101
|
+
data_type="",
|
|
102
|
+
length=4,
|
|
103
|
+
components=[McObject(name="voltage4", address=8389922, ext=0, data_type="F32", length=4, components=[])],
|
|
104
|
+
),
|
|
105
|
+
]
|
|
106
|
+
|
|
107
|
+
EXPECTED_BLOCK_VAR_2_64 = [
|
|
108
|
+
McObject(
|
|
109
|
+
name="",
|
|
110
|
+
address=8389906,
|
|
111
|
+
ext=0,
|
|
112
|
+
data_type="",
|
|
113
|
+
length=6,
|
|
114
|
+
components=[
|
|
115
|
+
McObject(name="sine_wave", address=8389906, ext=0, data_type="F32", length=4, components=[]),
|
|
116
|
+
McObject(name="sq0", address=8389910, ext=0, data_type="U8", length=1, components=[]),
|
|
117
|
+
McObject(name="sq1", address=8389911, ext=0, data_type="U8", length=1, components=[]),
|
|
118
|
+
],
|
|
119
|
+
),
|
|
120
|
+
McObject(
|
|
121
|
+
name="",
|
|
122
|
+
address=8389914,
|
|
123
|
+
ext=0,
|
|
124
|
+
data_type="",
|
|
125
|
+
length=16,
|
|
126
|
+
components=[
|
|
127
|
+
McObject(name="voltage1", address=8389914, ext=0, data_type="F32", length=4, components=[]),
|
|
128
|
+
McObject(name="voltage2", address=8389918, ext=0, data_type="F32", length=4, components=[]),
|
|
129
|
+
McObject(name="voltage3", address=8389922, ext=0, data_type="F32", length=4, components=[]),
|
|
130
|
+
McObject(name="voltage4", address=8389926, ext=0, data_type="F32", length=4, components=[]),
|
|
131
|
+
],
|
|
132
|
+
),
|
|
133
|
+
]
|
|
134
|
+
|
|
135
|
+
EXPECTED_BLOCK_VAR_2_8 = [
|
|
136
|
+
McObject(
|
|
137
|
+
name="",
|
|
138
|
+
address=8389906,
|
|
139
|
+
ext=0,
|
|
140
|
+
data_type="",
|
|
141
|
+
length=6,
|
|
142
|
+
components=[
|
|
143
|
+
McObject(name="sine_wave", address=8389906, ext=0, data_type="F32", length=4, components=[]),
|
|
144
|
+
McObject(name="sq0", address=8389910, ext=0, data_type="U8", length=1, components=[]),
|
|
145
|
+
McObject(name="sq1", address=8389911, ext=0, data_type="U8", length=1, components=[]),
|
|
146
|
+
],
|
|
147
|
+
),
|
|
148
|
+
McObject(
|
|
149
|
+
name="",
|
|
150
|
+
address=8389914,
|
|
151
|
+
ext=0,
|
|
152
|
+
data_type="",
|
|
153
|
+
length=4,
|
|
154
|
+
components=[
|
|
155
|
+
McObject(name="voltage1", address=8389914, ext=0, data_type="F32", length=4, components=[]),
|
|
156
|
+
],
|
|
157
|
+
),
|
|
158
|
+
McObject(
|
|
159
|
+
name="",
|
|
160
|
+
address=8389918,
|
|
161
|
+
ext=0,
|
|
162
|
+
data_type="",
|
|
163
|
+
length=4,
|
|
164
|
+
components=[
|
|
165
|
+
McObject(name="voltage2", address=8389918, ext=0, data_type="F32", length=4, components=[]),
|
|
166
|
+
],
|
|
167
|
+
),
|
|
168
|
+
McObject(
|
|
169
|
+
name="",
|
|
170
|
+
address=8389922,
|
|
171
|
+
ext=0,
|
|
172
|
+
data_type="",
|
|
173
|
+
length=4,
|
|
174
|
+
components=[
|
|
175
|
+
McObject(name="voltage3", address=8389922, ext=0, data_type="F32", length=4, components=[]),
|
|
176
|
+
],
|
|
177
|
+
),
|
|
178
|
+
McObject(
|
|
179
|
+
name="",
|
|
180
|
+
address=8389926,
|
|
181
|
+
ext=0,
|
|
182
|
+
data_type="",
|
|
183
|
+
length=4,
|
|
184
|
+
components=[
|
|
185
|
+
McObject(name="voltage4", address=8389926, ext=0, data_type="F32", length=4, components=[]),
|
|
186
|
+
],
|
|
187
|
+
),
|
|
188
|
+
]
|
|
189
|
+
|
|
190
|
+
BIN_PACKING_VAR1_8 = (
|
|
191
|
+
(
|
|
192
|
+
7,
|
|
193
|
+
3,
|
|
194
|
+
[
|
|
195
|
+
McObject(
|
|
196
|
+
name="",
|
|
197
|
+
address=8389906,
|
|
198
|
+
ext=0,
|
|
199
|
+
data_type="",
|
|
200
|
+
length=4,
|
|
201
|
+
components=[
|
|
202
|
+
McObject(name="sine_wave", address=8389906, ext=0, data_type="F32", length=4, components=[]),
|
|
203
|
+
],
|
|
204
|
+
)
|
|
205
|
+
],
|
|
206
|
+
),
|
|
207
|
+
(
|
|
208
|
+
7,
|
|
209
|
+
3,
|
|
210
|
+
[
|
|
211
|
+
McObject(
|
|
212
|
+
name="",
|
|
213
|
+
address=8389910,
|
|
214
|
+
ext=0,
|
|
215
|
+
data_type="",
|
|
216
|
+
length=4,
|
|
217
|
+
components=[
|
|
218
|
+
McObject(name="voltage1", address=8389910, ext=0, data_type="F32", length=4, components=[]),
|
|
219
|
+
],
|
|
220
|
+
)
|
|
221
|
+
],
|
|
222
|
+
),
|
|
223
|
+
(
|
|
224
|
+
7,
|
|
225
|
+
3,
|
|
226
|
+
[
|
|
227
|
+
McObject(
|
|
228
|
+
name="",
|
|
229
|
+
address=8389914,
|
|
230
|
+
ext=0,
|
|
231
|
+
data_type="",
|
|
232
|
+
length=4,
|
|
233
|
+
components=[
|
|
234
|
+
McObject(name="voltage2", address=8389914, ext=0, data_type="F32", length=4, components=[]),
|
|
235
|
+
],
|
|
236
|
+
)
|
|
237
|
+
],
|
|
238
|
+
),
|
|
239
|
+
(
|
|
240
|
+
7,
|
|
241
|
+
3,
|
|
242
|
+
[
|
|
243
|
+
McObject(
|
|
244
|
+
name="",
|
|
245
|
+
address=8389918,
|
|
246
|
+
ext=0,
|
|
247
|
+
data_type="",
|
|
248
|
+
length=4,
|
|
249
|
+
components=[
|
|
250
|
+
McObject(name="voltage3", address=8389918, ext=0, data_type="F32", length=4, components=[]),
|
|
251
|
+
],
|
|
252
|
+
)
|
|
253
|
+
],
|
|
254
|
+
),
|
|
255
|
+
)
|
|
256
|
+
|
|
257
|
+
BIN_PACKING_VAR2_8 = (
|
|
258
|
+
(
|
|
259
|
+
7,
|
|
260
|
+
1,
|
|
261
|
+
[
|
|
262
|
+
McObject(
|
|
263
|
+
name="",
|
|
264
|
+
address=8389906,
|
|
265
|
+
ext=0,
|
|
266
|
+
data_type="",
|
|
267
|
+
length=6,
|
|
268
|
+
components=[
|
|
269
|
+
McObject(name="sine_wave", address=8389906, ext=0, data_type="F32", length=4, components=[]),
|
|
270
|
+
McObject(name="sq0", address=8389910, ext=0, data_type="U8", length=1, components=[]),
|
|
271
|
+
McObject(name="sq1", address=8389911, ext=0, data_type="U8", length=1, components=[]),
|
|
272
|
+
],
|
|
273
|
+
)
|
|
274
|
+
],
|
|
275
|
+
),
|
|
276
|
+
(
|
|
277
|
+
7,
|
|
278
|
+
3,
|
|
279
|
+
[
|
|
280
|
+
McObject(
|
|
281
|
+
name="",
|
|
282
|
+
address=8389914,
|
|
283
|
+
ext=0,
|
|
284
|
+
data_type="",
|
|
285
|
+
length=4,
|
|
286
|
+
components=[
|
|
287
|
+
McObject(name="voltage1", address=8389914, ext=0, data_type="F32", length=4, components=[]),
|
|
288
|
+
],
|
|
289
|
+
)
|
|
290
|
+
],
|
|
291
|
+
),
|
|
292
|
+
(
|
|
293
|
+
7,
|
|
294
|
+
3,
|
|
295
|
+
[
|
|
296
|
+
McObject(
|
|
297
|
+
name="",
|
|
298
|
+
address=8389918,
|
|
299
|
+
ext=0,
|
|
300
|
+
data_type="",
|
|
301
|
+
length=4,
|
|
302
|
+
components=[
|
|
303
|
+
McObject(name="voltage2", address=8389918, ext=0, data_type="F32", length=4, components=[]),
|
|
304
|
+
],
|
|
305
|
+
)
|
|
306
|
+
],
|
|
307
|
+
),
|
|
308
|
+
(
|
|
309
|
+
7,
|
|
310
|
+
3,
|
|
311
|
+
[
|
|
312
|
+
McObject(
|
|
313
|
+
name="",
|
|
314
|
+
address=8389922,
|
|
315
|
+
ext=0,
|
|
316
|
+
data_type="",
|
|
317
|
+
length=4,
|
|
318
|
+
components=[
|
|
319
|
+
McObject(name="voltage3", address=8389922, ext=0, data_type="F32", length=4, components=[]),
|
|
320
|
+
],
|
|
321
|
+
)
|
|
322
|
+
],
|
|
323
|
+
),
|
|
324
|
+
(
|
|
325
|
+
7,
|
|
326
|
+
3,
|
|
327
|
+
[
|
|
328
|
+
McObject(
|
|
329
|
+
name="",
|
|
330
|
+
address=8389926,
|
|
331
|
+
ext=0,
|
|
332
|
+
data_type="",
|
|
333
|
+
length=4,
|
|
334
|
+
components=[
|
|
335
|
+
McObject(name="voltage4", address=8389926, ext=0, data_type="F32", length=4, components=[]),
|
|
336
|
+
],
|
|
337
|
+
)
|
|
338
|
+
],
|
|
339
|
+
),
|
|
340
|
+
)
|
|
341
|
+
|
|
342
|
+
BIN_PACKING_VAR1_64 = (
|
|
343
|
+
(
|
|
344
|
+
63,
|
|
345
|
+
43,
|
|
346
|
+
[
|
|
347
|
+
McObject(
|
|
348
|
+
name="",
|
|
349
|
+
address=8389906,
|
|
350
|
+
ext=0,
|
|
351
|
+
data_type="",
|
|
352
|
+
length=20,
|
|
353
|
+
components=[
|
|
354
|
+
McObject(name="sine_wave", address=8389906, ext=0, data_type="F32", length=4, components=[]),
|
|
355
|
+
McObject(name="voltage1", address=8389910, ext=0, data_type="F32", length=4, components=[]),
|
|
356
|
+
McObject(name="voltage2", address=8389914, ext=0, data_type="F32", length=4, components=[]),
|
|
357
|
+
McObject(name="voltage3", address=8389918, ext=0, data_type="F32", length=4, components=[]),
|
|
358
|
+
McObject(name="voltage4", address=8389922, ext=0, data_type="F32", length=4, components=[]),
|
|
359
|
+
],
|
|
360
|
+
)
|
|
361
|
+
],
|
|
362
|
+
),
|
|
363
|
+
)
|
|
364
|
+
|
|
365
|
+
BIN_PACKING_VAR2_64 = (
|
|
366
|
+
63,
|
|
367
|
+
41,
|
|
368
|
+
[
|
|
369
|
+
McObject(
|
|
370
|
+
name="",
|
|
371
|
+
address=8389914,
|
|
372
|
+
ext=0,
|
|
373
|
+
data_type="",
|
|
374
|
+
length=16,
|
|
375
|
+
components=[
|
|
376
|
+
McObject(name="voltage1", address=8389914, ext=0, data_type="F32", length=4, components=[]),
|
|
377
|
+
McObject(name="voltage2", address=8389918, ext=0, data_type="F32", length=4, components=[]),
|
|
378
|
+
McObject(name="voltage3", address=8389922, ext=0, data_type="F32", length=4, components=[]),
|
|
379
|
+
McObject(name="voltage4", address=8389926, ext=0, data_type="F32", length=4, components=[]),
|
|
380
|
+
],
|
|
381
|
+
),
|
|
382
|
+
McObject(
|
|
383
|
+
name="",
|
|
384
|
+
address=8389906,
|
|
385
|
+
ext=0,
|
|
386
|
+
data_type="",
|
|
387
|
+
length=6,
|
|
388
|
+
components=[
|
|
389
|
+
McObject(name="sine_wave", address=8389906, ext=0, data_type="F32", length=4, components=[]),
|
|
390
|
+
McObject(name="sq0", address=8389910, ext=0, data_type="U8", length=1, components=[]),
|
|
391
|
+
McObject(name="sq1", address=8389911, ext=0, data_type="U8", length=1, components=[]),
|
|
392
|
+
],
|
|
393
|
+
),
|
|
394
|
+
],
|
|
395
|
+
)
|
|
396
|
+
|
|
397
|
+
|
|
398
|
+
@pytest.mark.parametrize(
|
|
399
|
+
"daq_lists, expected_blocks, payload_size",
|
|
400
|
+
[
|
|
401
|
+
(DAQ_LISTS_1, EXPECTED_BLOCK_VAR_1_64, 64),
|
|
402
|
+
(DAQ_LISTS_1, EXPECTED_BLOCK_VAR_1_8, 8),
|
|
403
|
+
(DAQ_LISTS_2, EXPECTED_BLOCK_VAR_2_64, 64),
|
|
404
|
+
(DAQ_LISTS_2, EXPECTED_BLOCK_VAR_2_8, 8),
|
|
405
|
+
],
|
|
406
|
+
)
|
|
407
|
+
def test_make_continuous_blocks(daq_lists, expected_blocks, payload_size):
|
|
408
|
+
daq_list = daq_lists[0]
|
|
409
|
+
blocks = make_continuous_blocks(daq_list.measurements, payload_size - 1, payload_size - 1)
|
|
410
|
+
for block, expected_block in zip(blocks, expected_blocks):
|
|
411
|
+
assert block == expected_block
|
|
412
|
+
|
|
413
|
+
|
|
414
|
+
@pytest.mark.parametrize(
|
|
415
|
+
"blocks, expected_blocks, payload_size",
|
|
416
|
+
[
|
|
417
|
+
(EXPECTED_BLOCK_VAR_1_8, BIN_PACKING_VAR1_8, 8),
|
|
418
|
+
(EXPECTED_BLOCK_VAR_2_8, BIN_PACKING_VAR2_8, 8),
|
|
419
|
+
(EXPECTED_BLOCK_VAR_1_64, BIN_PACKING_VAR1_64, 64),
|
|
420
|
+
(EXPECTED_BLOCK_VAR_2_64, BIN_PACKING_VAR2_64, 64),
|
|
421
|
+
],
|
|
422
|
+
)
|
|
423
|
+
def test_first_fit_decreasing(blocks, expected_blocks, payload_size):
|
|
424
|
+
res = first_fit_decreasing(blocks, payload_size - 1, payload_size - 1) # noqa: F841
|
|
425
|
+
# for entry in res:
|
|
426
|
+
# print(entry.size, entry.residual_capacity, entry.entries)
|