pyvex 9.2.193__cp310-cp310-macosx_10_12_x86_64.whl

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Files changed (59) hide show
  1. pyvex/__init__.py +92 -0
  2. pyvex/_register_info.py +1800 -0
  3. pyvex/arches.py +94 -0
  4. pyvex/block.py +697 -0
  5. pyvex/const.py +426 -0
  6. pyvex/const_val.py +26 -0
  7. pyvex/data_ref.py +55 -0
  8. pyvex/enums.py +156 -0
  9. pyvex/errors.py +31 -0
  10. pyvex/expr.py +974 -0
  11. pyvex/include/libvex.h +1029 -0
  12. pyvex/include/libvex_basictypes.h +236 -0
  13. pyvex/include/libvex_emnote.h +142 -0
  14. pyvex/include/libvex_guest_amd64.h +252 -0
  15. pyvex/include/libvex_guest_arm.h +224 -0
  16. pyvex/include/libvex_guest_arm64.h +203 -0
  17. pyvex/include/libvex_guest_mips32.h +175 -0
  18. pyvex/include/libvex_guest_mips64.h +173 -0
  19. pyvex/include/libvex_guest_offsets.h +941 -0
  20. pyvex/include/libvex_guest_ppc32.h +298 -0
  21. pyvex/include/libvex_guest_ppc64.h +343 -0
  22. pyvex/include/libvex_guest_riscv64.h +148 -0
  23. pyvex/include/libvex_guest_s390x.h +201 -0
  24. pyvex/include/libvex_guest_tilegx.h +149 -0
  25. pyvex/include/libvex_guest_x86.h +322 -0
  26. pyvex/include/libvex_ir.h +3113 -0
  27. pyvex/include/libvex_s390x_common.h +123 -0
  28. pyvex/include/libvex_trc_values.h +99 -0
  29. pyvex/include/pyvex.h +96 -0
  30. pyvex/lib/libpyvex.dylib +0 -0
  31. pyvex/lifting/__init__.py +18 -0
  32. pyvex/lifting/gym/README.md +7 -0
  33. pyvex/lifting/gym/__init__.py +5 -0
  34. pyvex/lifting/gym/aarch64_spotter.py +40 -0
  35. pyvex/lifting/gym/arm_spotter.py +427 -0
  36. pyvex/lifting/gym/x86_spotter.py +129 -0
  37. pyvex/lifting/libvex.py +117 -0
  38. pyvex/lifting/lift_function.py +304 -0
  39. pyvex/lifting/lifter.py +124 -0
  40. pyvex/lifting/post_processor.py +16 -0
  41. pyvex/lifting/util/__init__.py +14 -0
  42. pyvex/lifting/util/instr_helper.py +422 -0
  43. pyvex/lifting/util/lifter_helper.py +154 -0
  44. pyvex/lifting/util/syntax_wrapper.py +312 -0
  45. pyvex/lifting/util/vex_helper.py +301 -0
  46. pyvex/lifting/zerodivision.py +71 -0
  47. pyvex/native.py +63 -0
  48. pyvex/py.typed +1 -0
  49. pyvex/stmt.py +740 -0
  50. pyvex/types.py +48 -0
  51. pyvex/utils.py +63 -0
  52. pyvex/vex_ffi.py +1453 -0
  53. pyvex-9.2.193.dist-info/METADATA +181 -0
  54. pyvex-9.2.193.dist-info/RECORD +59 -0
  55. pyvex-9.2.193.dist-info/WHEEL +6 -0
  56. pyvex-9.2.193.dist-info/licenses/LICENSE +24 -0
  57. pyvex-9.2.193.dist-info/licenses/pyvex_c/LICENSE +339 -0
  58. pyvex-9.2.193.dist-info/licenses/vex/LICENSE.GPL +340 -0
  59. pyvex-9.2.193.dist-info/licenses/vex/LICENSE.README +23 -0
@@ -0,0 +1,322 @@
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+
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+ /*---------------------------------------------------------------*/
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+ /*--- begin libvex_guest_x86.h ---*/
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+ /*---------------------------------------------------------------*/
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+
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+ /*
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+ This file is part of Valgrind, a dynamic binary instrumentation
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+ framework.
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+
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+ Copyright (C) 2004-2015 OpenWorks LLP
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+ info@open-works.net
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+
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+ This program is free software; you can redistribute it and/or
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+ modify it under the terms of the GNU General Public License as
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+ published by the Free Software Foundation; either version 2 of the
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+ License, or (at your option) any later version.
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+
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+ This program is distributed in the hope that it will be useful, but
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+ WITHOUT ANY WARRANTY; without even the implied warranty of
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+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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+ General Public License for more details.
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+
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+ You should have received a copy of the GNU General Public License
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+ along with this program; if not, write to the Free Software
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+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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+ 02110-1301, USA.
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+
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+ The GNU General Public License is contained in the file COPYING.
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+
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+ Neither the names of the U.S. Department of Energy nor the
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+ University of California nor the names of its contributors may be
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+ used to endorse or promote products derived from this software
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+ without prior written permission.
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+ */
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+
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+ #ifndef __LIBVEX_PUB_GUEST_X86_H
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+ #define __LIBVEX_PUB_GUEST_X86_H
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+
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+ #include "libvex_basictypes.h"
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+ #include "libvex_emnote.h"
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+
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+
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+ /*---------------------------------------------------------------*/
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+ /*--- Vex's representation of the x86 CPU state. ---*/
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+ /*---------------------------------------------------------------*/
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+
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+ /* The integer parts should be pretty straightforward. */
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+
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+ /* Hmm, subregisters. The simulated state is stored in memory in the
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+ host's byte ordering, so we can't say here what the offsets of %ax,
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+ %al, %ah etc are since that depends on the host's byte ordering,
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+ which we don't know. */
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+
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+ /* FPU. For now, just simulate 8 64-bit registers, their tags, and
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+ the reg-stack top pointer, of which only the least significant
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+ three bits are relevant.
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+
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+ The model is:
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+ F0 .. F7 are the 8 registers. FTOP[2:0] contains the
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+ index of the current 'stack top' -- pretty meaningless, but
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+ still. FTOP is a 32-bit value. FTOP[31:3] can be anything
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+ (not guaranteed to be zero).
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+
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+ When a value is pushed onto the stack, ftop is first replaced by
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+ (ftop-1) & 7, and then F[ftop] is assigned the value.
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+
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+ When a value is popped off the stack, the value is read from
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+ F[ftop], and then ftop is replaced by (ftop+1) & 7.
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+
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+ In general, a reference to a register ST(i) actually references
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+ F[ (ftop+i) & 7 ].
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+
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+ FTAG0 .. FTAG0+7 are the tags. Each is a byte, zero means empty,
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+ non-zero means non-empty.
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+
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+ The general rule appears to be that a read or modify of a register
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+ gets a stack underflow fault if the register is empty. A write of
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+ a register (only a write, not a modify) gets a stack overflow fault
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+ if the register is full. Note that "over" vs "under" is pretty
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+ meaningless since the FP stack pointer can move around arbitrarily,
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+ so it's really just two different kinds of exceptions:
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+ register-empty and register full.
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+
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+ Naturally Intel (in its infinite wisdom) has seen fit to throw in
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+ some ad-hoc inconsistencies to the fault-generation rules of the
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+ above para, just to complicate everything. Known inconsistencies:
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+
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+ * fxam can read a register in any state without taking an underflow
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+ fault.
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+
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+ * fst from st(0) to st(i) does not take an overflow fault even if the
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+ destination is already full.
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+
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+ FPROUND[1:0] is the FPU's notional rounding mode, encoded as per
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+ the IRRoundingMode type (see libvex_ir.h). This just happens to be
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+ the Intel encoding. Note carefully, the rounding mode is only
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+ observed on float-to-int conversions, and on float-to-float
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+ rounding, but not for general float-to-float operations, which are
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+ always rounded-to-nearest.
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+
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+ Loads/stores of the FPU control word are faked accordingly -- on
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+ loads, everything except the rounding mode is ignored, and on
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+ stores, you get a vanilla control world (0x037F) with the rounding
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+ mode patched in. Hence the only values you can get are 0x037F,
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+ 0x077F, 0x0B7F or 0x0F7F. Vex will emit an emulation warning if
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+ you try and load a control word which either (1) unmasks FP
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+ exceptions, or (2) changes the default (80-bit) precision.
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+
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+ FC3210 contains the C3, C2, C1 and C0 bits in the same place they
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+ are in the FPU's status word. (bits 14, 10, 9, 8 respectively).
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+ All other bits should be zero. The relevant mask to select just
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+ those bits is 0x4700. To select C3, C2 and C0 only, the mask is
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+ 0x4500.
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+
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+ SSEROUND[1:0] is the SSE unit's notional rounding mode, encoded as
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+ per the IRRoundingMode type. As with the FPU control word, the
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+ rounding mode is the only part of %MXCSR that Vex observes. On
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+ storing %MXCSR, you will get a vanilla word (0x1F80) with the
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+ rounding mode patched in. Hence the only values you will get are
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+ 0x1F80, 0x3F80, 0x5F80 or 0x7F80. Vex will emit an emulation
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+ warning if you try and load a control word which either (1) unmasks
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+ any exceptions, (2) sets FZ (flush-to-zero) to 1, or (3) sets DAZ
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+ (denormals-are-zeroes) to 1.
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+
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+ Segments: initial prefixes of local and global segment descriptor
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+ tables are modelled. guest_LDT is either zero (NULL) or points in
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+ the host address space to an array of VEX_GUEST_X86_LDT_NENT
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+ descriptors, which have the type VexGuestX86SegDescr, defined
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+ below. Similarly, guest_GDT is either zero or points in the host
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+ address space to an array of VEX_GUEST_X86_GDT_NENT descriptors.
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+ The only place where these are used are in the helper function
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+ x86g_use_seg(). LibVEX's client is responsible for pointing
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+ guest_LDT and guest_GDT at suitable tables. The contents of these
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+ tables are expected not to change during the execution of any given
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+ superblock, but they may validly be changed by LibVEX's client in
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+ between superblock executions.
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+
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+ Since x86g_use_seg() only expects these tables to have
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+ VEX_GUEST_X86_{LDT,GDT}_NENT entries, LibVEX's client should not
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+ attempt to write entries beyond those limits.
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+ */
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+ typedef
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+ struct {
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+ /* Event check fail addr and counter. */
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+ UInt host_EvC_FAILADDR; /* 0 */
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+ UInt host_EvC_COUNTER; /* 4 */
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+ UInt guest_EAX; /* 8 */
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+ UInt guest_ECX;
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+ UInt guest_EDX;
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+ UInt guest_EBX;
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+ UInt guest_ESP;
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+ UInt guest_EBP;
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+ UInt guest_ESI;
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+ UInt guest_EDI; /* 36 */
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+
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+ /* 4-word thunk used to calculate O S Z A C P flags. */
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+ UInt guest_CC_OP; /* 40 */
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+ UInt guest_CC_DEP1;
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+ UInt guest_CC_DEP2;
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+ UInt guest_CC_NDEP; /* 52 */
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+ /* The D flag is stored here, encoded as either -1 or +1 */
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+ UInt guest_DFLAG; /* 56 */
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+ /* Bit 21 (ID) of eflags stored here, as either 0 or 1. */
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+ UInt guest_IDFLAG; /* 60 */
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+ /* Bit 18 (AC) of eflags stored here, as either 0 or 1. */
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+ UInt guest_ACFLAG; /* 64 */
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+
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+ /* EIP */
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+ UInt guest_EIP; /* 68 */
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+
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+ /* FPU */
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+ ULong guest_FPREG[8]; /* 72 */
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+ UChar guest_FPTAG[8]; /* 136 */
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+ UInt guest_FPROUND; /* 144 */
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+ UInt guest_FC3210; /* 148 */
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+ UInt guest_FTOP; /* 152 */
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+
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+ /* SSE */
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+ UInt guest_SSEROUND; /* 156 */
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+ U128 guest_XMM0; /* 160 */
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+ U128 guest_XMM1;
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+ U128 guest_XMM2;
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+ U128 guest_XMM3;
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+ U128 guest_XMM4;
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+ U128 guest_XMM5;
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+ U128 guest_XMM6;
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+ U128 guest_XMM7;
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+
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+ /* Segment registers. */
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+ UShort guest_CS;
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+ UShort guest_DS;
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+ UShort guest_ES;
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+ UShort guest_FS;
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+ UShort guest_GS;
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+ UShort guest_SS;
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+ /* LDT/GDT stuff. */
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+ ULong guest_LDT; /* host addr, a VexGuestX86SegDescr* */
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+ ULong guest_GDT; /* host addr, a VexGuestX86SegDescr* */
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+
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+ /* Emulation notes */
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+ UInt guest_EMNOTE;
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+
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+ /* For clflush/clinval: record start and length of area */
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+ UInt guest_CMSTART;
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+ UInt guest_CMLEN;
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+
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+ /* Used to record the unredirected guest address at the start of
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+ a translation whose start has been redirected. By reading
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+ this pseudo-register shortly afterwards, the translation can
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+ find out what the corresponding no-redirection address was.
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+ Note, this is only set for wrap-style redirects, not for
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+ replace-style ones. */
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+ UInt guest_NRADDR;
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+
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+ /* Used for Darwin syscall dispatching. */
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+ UInt guest_SC_CLASS;
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+
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+ /* Needed for Darwin (but mandated for all guest architectures):
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+ EIP at the last syscall insn (int 0x80/81/82, sysenter,
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+ syscall). Used when backing up to restart a syscall that has
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+ been interrupted by a signal. */
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+ UInt guest_IP_AT_SYSCALL;
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+
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+ /* Padding to make it have an 16-aligned size */
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+ UInt padding1;
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+ }
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+ VexGuestX86State;
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+
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+ #define VEX_GUEST_X86_LDT_NENT /*64*/ 8192 /* use complete LDT */
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+ #define VEX_GUEST_X86_GDT_NENT /*16*/ 8192 /* use complete GDT */
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+
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+
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+ /*---------------------------------------------------------------*/
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+ /*--- Types for x86 guest stuff. ---*/
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+ /*---------------------------------------------------------------*/
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+
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+ /* VISIBLE TO LIBRARY CLIENT */
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+
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+ /* This is the hardware-format for a segment descriptor, ie what the
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+ x86 actually deals with. It is 8 bytes long. It's ugly. */
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+
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+ typedef struct {
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+ union {
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+ struct {
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+ UShort LimitLow;
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+ UShort BaseLow;
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+ UInt BaseMid : 8;
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+ UInt Type : 5;
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+ UInt Dpl : 2;
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+ UInt Pres : 1;
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+ UInt LimitHi : 4;
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+ UInt Sys : 1;
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+ UInt Reserved_0 : 1;
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+ UInt Default_Big : 1;
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+ UInt Granularity : 1;
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+ UInt BaseHi : 8;
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+ } Bits;
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+ struct {
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+ UInt word1;
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+ UInt word2;
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+ } Words;
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+ }
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+ LdtEnt;
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+ } VexGuestX86SegDescr;
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+
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+
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+ /*---------------------------------------------------------------*/
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+ /*--- Utility functions for x86 guest stuff. ---*/
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+ /*---------------------------------------------------------------*/
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+
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+ /* ALL THE FOLLOWING ARE VISIBLE TO LIBRARY CLIENT */
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+
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+ /* Initialise all guest x86 state. The FPU is put in default mode. */
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+ extern
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+ void LibVEX_GuestX86_initialise ( /*OUT*/VexGuestX86State* vex_state );
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+
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+
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+ /* Extract from the supplied VexGuestX86State structure the
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+ corresponding native %eflags value. */
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+ extern
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+ UInt LibVEX_GuestX86_get_eflags ( /*IN*/const VexGuestX86State* vex_state );
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+
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+ /* Put eflags into the given state. */
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+ extern
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+ void LibVEX_GuestX86_put_eflags ( UInt eflags,
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+ /*MOD*/VexGuestX86State* vex_state );
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+
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+ /* Set the carry flag in the given state to 'new_carry_flag', which
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+ should be zero or one. */
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+ extern
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+ void
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+ LibVEX_GuestX86_put_eflag_c ( UInt new_carry_flag,
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+ /*MOD*/VexGuestX86State* vex_state );
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+
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+ /* Do x87 save from the supplied VexGuestX86State structure and store the
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+ result at the given address which represents a buffer of at least 108
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+ bytes. */
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+ extern
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+ void LibVEX_GuestX86_get_x87 ( /*IN*/VexGuestX86State* vex_state,
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+ /*OUT*/UChar* x87_state );
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+
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+ /* Do x87 restore from the supplied address and store read values to the given
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+ VexGuestX86State structure. */
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+ extern
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+ VexEmNote LibVEX_GuestX86_put_x87 ( /*IN*/UChar* x87_state,
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+ /*MOD*/VexGuestX86State* vex_state);
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+
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+ /* Return mxcsr from the supplied VexGuestX86State structure. */
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+ extern
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+ UInt LibVEX_GuestX86_get_mxcsr ( /*IN*/VexGuestX86State* vex_state );
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+
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+ /* Modify the given VexGuestX86State structure according to the passed mxcsr
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+ value. */
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+ extern
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+ VexEmNote LibVEX_GuestX86_put_mxcsr ( /*IN*/UInt mxcsr,
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+ /*MOD*/VexGuestX86State* vex_state);
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+
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+ #endif /* ndef __LIBVEX_PUB_GUEST_X86_H */
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+
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+ /*---------------------------------------------------------------*/
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+ /*--- libvex_guest_x86.h ---*/
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+ /*---------------------------------------------------------------*/