pyvex 9.2.173__py3-none-win_amd64.whl → 9.2.175__py3-none-win_amd64.whl

pyvex/__init__.py

@@ -3,7 +3,7 @@ PyVEX provides an interface that translates binary code into the VEX intermediat
 For an introduction to VEX, take a look here: https://docs.angr.io/advanced-topics/ir
 """
 
-__version__ = "9.2.173"
+__version__ = "9.2.175"
 
 from . import const, expr, stmt
 from .arches import (

{pyvex-9.2.173.dist-info → pyvex-9.2.175.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.4
 Name: pyvex
-Version: 9.2.173
+Version: 9.2.175
 Summary: A Python interface to libVEX and VEX IR
 License-Expression: BSD-2-Clause AND GPL-2.0-only
 License-File: LICENSE
@@ -106,7 +106,7 @@ print(irsb.tyenv.types)
 print(irsb.tyenv.types[0])
 ```
 
-Keep in mind that this is a *syntactic* respresentation of a basic block. That is, it'll tell you what the block means, but you don't have any context to say, for example, what *actual* data is written by a store instruction.
+Keep in mind that this is a *syntactic* representation of a basic block. That is, it'll tell you what the block means, but you don't have any context to say, for example, what *actual* data is written by a store instruction.
 
 ## VEX Intermediate Representation
 
@@ -114,7 +114,7 @@ To deal with widely diverse architectures, it is useful to carry out analyses on
 An IR abstracts away several architecture differences when dealing with different architectures, allowing a single analysis to be run on all of them:
 
 - **Register names.** The quantity and names of registers differ between architectures, but modern CPU designs hold to a common theme: each CPU contains several general purpose registers, a register to hold the stack pointer, a set of registers to store condition flags, and so forth. The IR provides a consistent, abstracted interface to registers on different platforms. Specifically, VEX models the registers as a separate memory space, with integer offsets (i.e., AMD64's `rax` is stored starting at address 16 in this memory space).
-- **Memory access.** Different architectures access memory in different ways. For example, ARM can access memory in both little-endian and big-endian modes. The IR must abstracts away these differences.
+- **Memory access.** Different architectures access memory in different ways. For example, ARM can access memory in both little-endian and big-endian modes. The IR must abstract away these differences.
 - **Memory segmentation.** Some architectures, such as x86, support memory segmentation through the use of special segment registers. The IR understands such memory access mechanisms.
 - **Instruction side-effects.** Most instructions have side-effects. For example, most operations in Thumb mode on ARM update the condition flags, and stack push/pop instructions update the stack pointer. Tracking these side-effects in an *ad hoc* manner in the analysis would be crazy, so the IR makes these effects explicit.
 

{pyvex-9.2.173.dist-info → pyvex-9.2.175.dist-info}/RECORD

@@ -1,4 +1,4 @@
-pyvex/__init__.py,sha256=UXAGicGYOZD3nbH8fy2gHYauT94qD1ulqkvvGfhO8Bw,1854
+pyvex/__init__.py,sha256=e4Z3pYwAHVhZs5gShEn-Se_9QNSyLwZ4tE7kZe9DCrM,1854
 pyvex/_register_info.py,sha256=obrahVpfLzJ4TdawSLha-xNdyv6zA87NKlTC2JwsR6I,49630
 pyvex/arches.py,sha256=Fp7cV3dW3Ld1qz3kHcjt-cGfH9ghbCXhXwyhOacGJIY,3657
 pyvex/block.py,sha256=ofh5x420DxA2SqWUpu8wN-o6qYfSiXhb6CmKpLiskAE,25391
@@ -27,7 +27,7 @@ pyvex/include/libvex_ir.h,sha256=mM7u19u1rZIuF3KXCGhg2gbdHG4e1nWbvGt0wbZp1GI,122
 pyvex/include/libvex_s390x_common.h,sha256=97CQbrtTdzYUHMsbJ0pn_cfCu16uFTaf97P1yX-4vqg,5025
 pyvex/include/libvex_trc_values.h,sha256=xO2pEbnlVXQijRUE_E5VWHCkEjG5XPaCG_MkpLeDvjQ,4451
 pyvex/include/pyvex.h,sha256=Gn_TGMXO5l6-1nSnwLvANMfQhE3YdBTyLgSuCbAWy0Q,1962
-pyvex/lib/pyvex.dll,sha256=qKRHxVLsPVA102BTHoX364bb3wp7EwXPUblzqEboTkY,2716160
+pyvex/lib/pyvex.dll,sha256=oLAovQ9QJQiyGnqAcyzj0G-dIYTAw5ak6lL6jC6mutA,2716160
 pyvex/lib/pyvex.lib,sha256=DHI7Q-UdH3_VjaAfkzXfPJs5saYTm2hdc6BgXthNo-0,11464
 pyvex/lifting/__init__.py,sha256=qJulYcyrKrWF7rNcm62rg7g2Jkuem0OFAC2N23Wblfo,689
 pyvex/lifting/gym/__init__.py,sha256=4MMhN4POLhKNjrSIY3KBV5PGn8uHiUHcY_7Wnnmc6DM,204
@@ -51,10 +51,10 @@ pyvex/stmt.py,sha256=spT_JF1Jj6PxhH3ER2XW8i2JFGdhGRW4GYGHX3UJH10,22290
 pyvex/types.py,sha256=9m0fgYoRF7VVb5tByClPdqkAGi-nm-G7Uhqjs5YW_DQ,1005
 pyvex/utils.py,sha256=2yjR371Jdg6YbVAG8v4_1TvvYN0EAjNZspCTfa0WXZo,1429
 pyvex/vex_ffi.py,sha256=P7KM3c7cvlD1Q_pblFSFZekEHyFdRERAAPNs9cF1NCQ,69736
-pyvex-9.2.173.dist-info/METADATA,sha256=7z_bkR4S40ollTBwsiEjA9hxva9jDfHDDnmovPZtavU,10193
-pyvex-9.2.173.dist-info/WHEEL,sha256=7cuQBrKlgrMjywT6nmSZIIhuOog1xNCTkMyVVbw2aow,103
-pyvex-9.2.173.dist-info/licenses/LICENSE,sha256=cgL_ho5B1NH8UxwtBuqThRWdjear8b7hktycaS1sz6g,1327
-pyvex-9.2.173.dist-info/licenses/pyvex_c/LICENSE,sha256=gXf5dRMhNSbfLPYYTY_5hsZ1r7UU1OaKQEAQUhuIBkM,18092
-pyvex-9.2.173.dist-info/licenses/vex/LICENSE.GPL,sha256=5tagCVBeNF_pSeExAzT8sHR_KNrihWdZ3hAqtmtyLLQ,18011
-pyvex-9.2.173.dist-info/licenses/vex/LICENSE.README,sha256=l2bDDkbW7bgEzAwFYtTEUto7yT_Aph9Sc5EZ1uNYWts,996
-pyvex-9.2.173.dist-info/RECORD,,
+pyvex-9.2.175.dist-info/METADATA,sha256=cvKkCpNgFTktkiPO2tRz6TBNxlgqQ5njz4UF_ASGPWg,10191
+pyvex-9.2.175.dist-info/WHEEL,sha256=7cuQBrKlgrMjywT6nmSZIIhuOog1xNCTkMyVVbw2aow,103
+pyvex-9.2.175.dist-info/licenses/LICENSE,sha256=cgL_ho5B1NH8UxwtBuqThRWdjear8b7hktycaS1sz6g,1327
+pyvex-9.2.175.dist-info/licenses/pyvex_c/LICENSE,sha256=gXf5dRMhNSbfLPYYTY_5hsZ1r7UU1OaKQEAQUhuIBkM,18092
+pyvex-9.2.175.dist-info/licenses/vex/LICENSE.GPL,sha256=5tagCVBeNF_pSeExAzT8sHR_KNrihWdZ3hAqtmtyLLQ,18011
+pyvex-9.2.175.dist-info/licenses/vex/LICENSE.README,sha256=l2bDDkbW7bgEzAwFYtTEUto7yT_Aph9Sc5EZ1uNYWts,996
+pyvex-9.2.175.dist-info/RECORD,,